JP2811911B2 - Serial data transmission device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a serial data transmission device, and more particularly, to a reduction in the number of wires between a transmission device and a reception device.

<Conventional technology> For example, when measuring using a recorder, if you want to turn on / off an external circuit (for example, 250V AC / 1A, 30V DC / 2A) at a location away from the recorder according to the magnitude relationship between the measured value and the alarm set value There is.

When the number of measurement channels is small, a plurality of relays having a predetermined current capacity can be provided inside the recorder, and an external circuit can be taken in and connected to the inside of the recorder. However, the number of measurement channels increases (for example, 30 Channel) and the internal space of the recorder.

Therefore, conventionally, a relay box containing a plurality of relays that are opened and closed in accordance with an alarm output signal of a recorder and whose contacts are connected to a part of an external circuit has been used.

FIG. 3 is a block diagram showing an example of a conventional data transmission portion having such a configuration, and FIG. 4 is a timing chart for explaining the operation of FIG.

The recorder functions as the serial data transmission device 1, and includes a CPU 2, a clock generation circuit 3, and a shift register 4. The relay box functions as the serial data receiving device 5 and has a shift register 6.

In such a configuration, the CPU 2 of the transmission device 1 controls the clock generation circuit 3 and the shift register 4. The clock generation circuit 3 outputs the clock signal CLK as shown in FIG. 4A to the shift register 4 and also outputs the clock signal CLK to the shift register 6 of the receiving device 5 via the clock line. Alarm output signals generated by a not-shown portion of the recorder 1 are sequentially stored in the shift register 4 in accordance with the clock signal CLK, and the stored alarm output signals are serial data DATA as shown in FIG. 8, the shift register 6 of the receiving device 5
Is output to The CPU 2 outputs a strobe STRB as shown in FIG. 4B to the shift register 6 via the strobe line 9 every time a series of data transmission is completed. The shift register 6 latches the data DATA sequentially stored according to the clock CLK according to the strobe signal STRB.
The data thus latched in the shift register 6
DATA is used as a drive signal for a relay (not shown).

<Problem to be solved by the invention> However, according to such a conventional configuration, the transmitting device 1
And three signal lines 7, 8, and 9 are required between the
There is a problem that the wiring cost increases.

The present invention focuses on such a point, and an object of the present invention is to provide a serial data transmission device capable of reducing the number of signal lines without lowering the reliability of data transmission.

<Means for Solving the Problems> In a serial data transmission device of the present invention, a serial data transmission device and a serial data reception device are connected by a data line and a clock line, and the serial data reception device transmits data via a data line. A shift register in which data to be transmitted is sequentially stored in accordance with a clock signal transmitted through a clock line, and constantly monitoring a clock signal transmitted through the clock line to detect that the clock signal is not transmitted for a certain period of time. And a watchdog timer for outputting a strobe signal for latching data in the shift register.

<Operation> The watchdog timer of the serial data receiving device detects that no clock signal is input from the serial data transmitting device for a certain period of time, determines that a series of data transfer is completed, generates a strobe signal, and outputs the strobe signal to the internal shift register. Output.

As a result, data sequentially stored in the shift register inside the serial data receiving device according to the clock signal is latched.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The same parts as those in FIG. 3 are denoted by the same reference numerals. In the figure, a receiving device 5 is provided with a watchdog timer 10 that constantly monitors a clock signal CLK transmitted via a clock line 7 in addition to a shift register 6. The watchdog timer 10 detects that the clock signal CLK has not been transmitted for a certain period of time,
And outputs a strobe signal STRB for latching data DATA. Incidentally, as the clock line 7 and the data line 8 in this embodiment, for example, an optical signal line is used.

FIG. 2 is a timing chart for explaining the operation of FIG.

Normal Operation First, the transmitting device 1 transmits the data DATA shown in (a) and the clock signal CLK shown in (b) to the receiving device 5. The shift register 6 of the receiving device 5 sequentially stores the transmitted data DATA in accordance with the clock signal CLK. On the other hand, the clock signal CLK is not transmitted to the receiving device 5 after the transmission of a series of data DATA is completed until the start of the next series of data transmission. The watchdog timer 10 constantly monitors the clock signal CLK, and determines that a series of data transmissions has been completed by detecting that the clock signal CLK has not arrived for a predetermined time T set in advance. Then, a strobe signal STRB shown in (c) is generated and output to the shift register 6. As a result, the shift register 6 latches a series of stored data DATA. Note that the time T may be set slightly longer than the cycle of the clock signal CLK.

Operation at the Time of Abnormal Consider a case where the power of the receiving device 5 is turned on while the power of the transmitting device 1 is turned on first and the transmitting device 1 is transmitting data DATA.

In this case, the data DATA received first by the receiving device 5 becomes abnormal data, but the data DATA received second and subsequent times.
Becomes normal data.

Next, consider a case where a sudden noise component jumps into the clock line 7.

In this case as well, the data at the time the noise
Since the synchronization between DATA and the clock signal CLK is out of synchronization, the received data becomes abnormal, but the data DATA received after the second time becomes normal.

In the above embodiment, the clock line 7 and the data line 8 are used.
As an example, an optical signal line is used, but an electric signal line may be used. However, when an electric signal line is used, since a ground line is required, the conventional configuration requires a total of four signal lines, but the present invention can reduce the number to three.

In the above embodiment, the example of serial data transmission between the recorder and the relay box has been described. However, the present invention is also effective for other similar systems using simple serial data transmission.

<Effects of the Invention> As described above, according to the present invention, a serial data transmission device capable of reducing the number of signal lines without deteriorating the reliability of data transmission can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing an example of a data transmission portion of a conventional device,
FIG. 4 is a timing chart for explaining the operation of FIG. 1. Serial data transmission device (recorder) 2. CP
U, 3 ... clock generation circuit, 4,6 ... shift register,
5: Serial data receiving device, 7: Clock signal line, 8: Data line, 10: Watchdog timer.

Claims (1)

(57) [Claims] 1. A serial data transmitting device and a serial data receiving device are connected by a data line and a clock line, and the serial data receiving device includes a clock transmitting data transmitted via the data line via the clock line. A shift register sequentially stored according to a signal, and a clock signal transmitted via a clock line is constantly monitored, and a strobe signal for latching data in the shift register is output by detecting that the clock signal is not transmitted for a predetermined time. A serial data transmission device comprising: a watchdog timer.