JPS6137658B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a check device that automatically checks the functions of an input/output circuit connected to, for example, a digital computer.

Conventionally, input/output circuits (interface circuits), which are provided between digital computers and peripheral devices and have the role of processing transmission data in a form suitable for the functions of both devices in a predetermined manner and passing it on, have been used for, for example, serial-to-parallel conversion of data. Perform the action. To check whether such an input/output circuit is operating normally, as shown in FIG. Connect it to the output circuit 4 and check it by supplying a serial pseudo signal from the tester 2 to the input/output circuit 4 serial-to-parallel converter circuit 5 by manually switching the switch, or as shown in Fig. 2. , a circuit 6 that generates a pseudo signal in the input/output circuit 4 connected to the computer 3;
By switching the internal switch 7 from the peripheral device 8, this pseudo signal is supplied to the serial-parallel conversion circuit 5, and the operation of the circuit 5 is checked.

As mentioned above, conventional input/output circuit checks are performed by connecting a tester to the device to be checked, or by providing a test signal obtained by switching a switch inside the device to be checked. When checking, the operator must leave the original computer system operation and perform manual operations such as operating test equipment and switches, which is not only troublesome but also reduces system efficiency.

The present invention was made in view of the above circumstances, and
Automatically checks whether the input/output circuit is functioning properly based on the check data sent from the computer, regardless of whether there is data transferred between the peripheral device and the computer, without reducing system efficiency. An object of the present invention is to provide an input/output circuit checking device that can perform checks on input/output circuits.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows a case where the check device of the present invention is applied to a computer system. In FIG. 3, 11 is a digital computer including a central processing unit, and 12 is this computer 11.
The peripheral device 13 is an input/output circuit that periodically transmits data to the peripheral device 12. After the transfer data of a predetermined bit length sent from the peripheral device 12 is subjected to a predetermined data processing in the input/output circuit 13, The data is transferred to the computer 11 via the common bus. The input/output circuit 13 is a branch circuit (represented by a wire connection in the figure) that guides and branches serial transfer data transmitted from the peripheral device 12 and supplies one of the branch signals to a serial-parallel conversion circuit to be described later. and a detection circuit 28 which introduces the other signal branched by this branch circuit, detects a period in which transfer data exists, and derives a control signal to the gate circuit so as to close at least the gate circuit (described later) during this period. Then, a gate operation is performed using a control signal from the detection circuit 28 and a clock from a clock oscillator (not shown), and check data of a predetermined bit length sent from the computer 11 in response to the device number signal of the peripheral device is processed. Register 19 to store
a gate circuit 20 that serially reads the check data from the gate circuit 20; an OR circuit 21 that ORs the serial check data read from the gate circuit 20 and the serial transfer data sent from the peripheral device 12; , this OR circuit 21
a serial-parallel conversion circuit 22 that converts serial data output from the computer 11 into parallel data based on the equipment number signal from the computer 11;
and has.

The detection circuit 28 includes a retrigger monostable multivibrator (hereinafter referred to as a retrigger monomulti) 15 that detects the period of serial transfer data transmitted from the peripheral device 12, and a serial another retrigger monomulti 16 that is set to a time width corresponding to the period of the transfer data and detects the presence or absence of serial transfer data;
An OR circuit 17 that takes the logical sum of the outputs of both of these monomultis 15 and 16, and is driven after a predetermined time by the output from this OR circuit 17, or automatically at a constant cycle when the output of the OR circuit 17 disappears. and a timer circuit 18 that outputs a gate signal (control signal) for a predetermined period. The input/output circuit 13 includes a control circuit that interrupts the computer 11 with a request signal when transmitting data from a large number of peripheral devices to the computer 11.

On the other hand, the computer 11 has a register 24 storing check data, a register 25 storing check data sent from the input/output circuit 13, and the contents of both registers 24 and 25 according to the control timing from the control circuit 26. It has a comparator 27 that compares whether or not the signals match. As a result of the comparison, if the contents of both registers 24 and 25 do not match, the comparator 27 sends a mismatch signal to the control circuit 26, and the control circuit 26 receives this mismatch signal and sends out an error signal. Further, this control circuit 26 receives a request signal after the conversion of the conversion circuit 22 is completed, and controls the check data to be sent from the register 24 to the input/output circuit 13 at a predetermined timing.

Next, the operation of the check device constructed as described above will be explained with reference to the time chart shown in FIG. Now, when serial transfer data with a predetermined bit length as shown in FIG. A pulse having a time width t1 approximately corresponding to the transfer data length as shown in b is output. This re-trigger mono multi 15
At the rising edge of the output pulse, another retrigger monomulti 16 operates as shown in FIG. 4c, and a pulse having a time width t2 approximately corresponding to the period of serial transfer data is output. In FIG. 4, the other re-trigger mono-multi 16 continues to operate due to the output pulse of the next re-trigger mono-multi 15. Further, the time width t2 is set on the assumption that the idle time between serial transfer data is known in advance since serial transfer data is sent periodically.

Since the output pulse of the retrigger monomulti 15 is supplied to the timer circuit 18 via the OR circuit 17, the falling edge of the output pulse of the retrigger monomulti 15 is output from the timer circuit 18 as shown in FIG. 4d. After a delay of time t3, a gate signal having a time width t4 is output. This gate signal is of course set to the idle time between the serial transfer data, and has a time width t4 corresponding to the bit length of the serial check data CD1 to CD4 shown in FIG. 4e.
has. Further, the delay setting time t3 in the timer circuit 18 is set in consideration of the time t5 for converting serial transfer data into parallel transfer data in the serial-parallel conversion circuit 22 as shown in FIG. Timer 1 from 17
When there is no input to 8, a gate signal is automatically output every time t3.

On the other hand, serial transfer data D1 sent from the peripheral device 12 is supplied to the serial-parallel conversion circuit 22 via the OR circuit 21, where it is converted from serial data to parallel data at processing time t5 shown in FIG. 6f. Conversion processing is performed. When this conversion process is completed, a request signal shown in FIG. 6h is sent from the control circuit of the input/output circuit 13 to the computer 11 via the common bus 14 to generate an interrupt. When the computer 11 becomes ready to receive data, the necessary peripheral equipment 12 is sent from the computer 11 via the common bus 14 as shown in FIG. 6i.
The device number is sent to the input/output circuit 13. Based on this equipment number, serial-parallel conversion circuit 2
2 to 4g, the parallel data output to the input bus 23 is read into the computer 11 via the common bus 14 and stored in a storage circuit (not shown). On the other hand, when the device number is sent from the computer 11 to the input/output circuit 13,
The check data stored in the register 24 in the computer 11 is stored in the register 19 of the input/output circuit 13 via the common bus 14. The check data stored in this register 19 is sequentially read out to the gate 20 by a shift clock generated in the gate 20 by the gate signal of the timer circuit 18 shown in FIG. Serial check data CD1 as shown in FIG. 4e is output.
Serial check data from this gate 20
CD1 is supplied to the serial-to-parallel conversion circuit 22 via the OR circuit 21, where it is converted from serial check data to parallel check data at serial-to-parallel conversion processing time t5 shown in FIG. 4f. When the processing in the serial-parallel conversion circuit 22 is completed, a request signal shown in FIG.
1 and interrupts the computer 11. When the computer 11 becomes interrupt-enabled, it supplies the device number of the peripheral device 12 to the serial-to-parallel conversion circuit 22 of the input/output circuit 13 through the common bus 14, as shown in FIG. As shown in g, parallel check data is read out to the input bus 23 and sent to the register 25 of the computer 11 via the common bus 14.
Store in. After the check data is stored in this register 25, the control circuit 26
The register 24 storing the check data and the register 25 storing the check data sent from the input/output circuit 13 are compared in bit parallel by the comparison circuit 27 according to the timing signal from the input/output circuit 13. If the contents of the registers 24 and 25 match, it means that the serial-to-parallel conversion circuit 22 of the input/output circuit 13 is functioning normally, so the computer 11 moves on to accept new data from the peripheral device 12. . When the comparison operation is completed, a reset signal is output from the control circuit 26 to reset the register 25. On the other hand, if the comparison results show that the contents of both registers 24 and 25 are different, the comparison circuit 27 transfers the mismatch signal to the control circuit 25.
6, the control circuit 26 receives this mismatch signal, sends out an error signal, and uses this error signal to cause a display circuit (not shown) to display an error. When the operator sees this error display, the operator stops the system operation and takes measures to deal with the error. The serial transfer data D2 shown in FIG. 4a and the serial check data CD2 shown in FIG. 4e are also converted into parallel data and transferred to the computer 11 by the same operation as described above.

Next, the case when serial transfer data is not transmitted from the peripheral device 12, that is, the case after D2 will be explained. The serial transfer data D2 causes the retrigger monomulti 15 to operate as shown in FIG. , since there is no new data after data D2, the level becomes "0" after a predetermined time t2, as shown in FIG. 4c. By inverting the retrigger monomulti 16 to the "0" level, it is detected that there is no transfer data. When no transfer data is detected by the retrigger monomulti 16, the timer circuit 18 is activated by the inverted output of the monomulti 16 via the OR circuit 17. As shown in FIG. 4d, the timer circuit 18 generates a gate signal having a period t4 for serially reading out check data from the register 19 at a period of (t3+t4) while the state of no data transfer is detected. Occur.

Until the transfer data is sent from the peripheral device 12, only the check data CD3 and CD4 are supplied from the register 19 to the serial-parallel conversion circuit 22 via the gate 20 and the OR circuit 21 by the same operation as described above. Here, the serial check data is converted into parallel check data and transferred to the computer 11. The computer 11 checks whether the serial-to-parallel conversion circuit 22 of the input/output circuit 13 is functioning normally by comparing the transferred check data with the sent check data as described above.

According to the above-described check device, the input/output circuit 1
3. Checking whether the function is normal or not can be done automatically and easily by using the check data from the computer 11, instead of the conventional check that requires human operations such as connecting a test machine or switching a switch. Ru. In addition, when there is data transferred from a peripheral device, it is checked using the free time between transferred data, so it does not affect the computer system operation or system efficiency, and the transferred data is Since the input/output circuit is checked even when there is no input/output circuit, a reliable check device can be achieved.

As described above, according to the present invention, when there is data to be transferred between the peripheral device and the computer, the gap between the transferred data is used to
If there is no data to be transferred, the function of the input/output circuit is checked based on the check data sent from the computer periodically.
It is possible to provide a check device that can automatically diagnose the function of input/output circuits without reducing system efficiency.

[Brief explanation of the drawing]

1 and 2 are configuration explanatory diagrams showing a conventional input/output circuit check device, respectively, FIG. 3 is a configuration explanatory diagram showing an embodiment of the input/output circuit check device according to the present invention, and FIG. 4 3 is a timing diagram shown for explaining the operation of FIG. 3. FIG. 11...computer, 12...peripheral equipment, 13...
Input/output circuit, 15, 16...retrigger mono multi,
18...Timer circuit, 20...Gate, 19,2
4, 25...Register, 22...Serial-to-parallel conversion circuit, 27...Comparison circuit, 28...Detection circuit.

Claims (1)

[Claims] 1 A converting means for converting a first signal of a first form supplied from the outside into a signal of a second form, a detecting means for detecting the presence or absence of the first signal, and a first signal for storing check data. 1 register, an output means to which check data is supplied from the first register and output the check data in the first form; and a register to which the check data from the output means and the output signal of the detection means are supplied. 1 signal, the gate is opened after a predetermined time longer than the signal length of the first signal after the first signal is detected, and when there is no first signal, the gate is opened periodically. gate means that opens the check data from the output means and supplies the check data from the output means as a second signal to the conversion means; and a second register that stores conversion output data corresponding to the second signal of the conversion means. and a comparison means for comparing data stored in the second register and the first register to detect whether or not the data match.