JP2808130B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a CMD (Charge) in which a source / drain current is modulated by an amount of charge generated and accumulated by light irradiation.
The present invention relates to a solid-state imaging device using an imaging element such as a modulation device as a pixel.

[Conventional technology]

Conventionally, various types of solid-state imaging devices including an imaging element having an MIS-type light receiving / accumulating unit are known.
2. Description of the Related Art There is a solid-state imaging device using an imaging element having an MIS type light receiving / accumulating unit and having an internal amplification function. One example is a solid-state imaging device using a CMD imaging device proposed by the present applicant. Japanese Patent Application Laid-Open No. 61-84059 and International Electron Device Meeting (IEDM) held in 1986, 353- “A NEW MOS IMAGE SENSOR OPE” on page 356
The content is disclosed in a paper entitled "RATING IN A NON-DESTRUCTIVE READOUT MODE".

Next, a conventional solid-state imaging device using such a CMD imaging device will be described with reference to the circuit diagram of FIG. First, CMD1-11, 1-12,... 1-mn constituting each pixel are arranged in a matrix, and a video bias V _DD (> 0) is commonly applied to each drain. The gate terminals of the CMDs arranged in the X direction are connected to the row lines 2-1, 2-2,... 2-m, respectively, and the source terminals of the CMDs arranged in the Y direction are the column lines 3-1 and 2-1. 3-2,..., 3-n.
The column lines 3-1, 3-2,... 3-n are respectively connected to column selecting transistors 4-1, 4-2,... 4-n and anti-selecting transistors 5-1, 5-2,. .. Are commonly connected to a signal line 6 and a reference line 7 grounded to GND via 5-n. The signal line 6 is connected to a current-voltage conversion type preamplifier 12 whose input is virtually grounded, and an output terminal 9 of the preamplifier 12 reads out a negative video signal in a time series. ... 2-m are connected to the vertical scanning circuit 10 to output signals Φ _G1 , Φ _{G2 ,.}
, And the column selection transistors 4-1, 4-2,..., 4-
n and counterclockwise selection transistor 5-1, a gate terminal of the ...... 5-n is connected to the horizontal scanning circuit 11, respectively signal _{Φ S1, Φ S2, ...... Φ} Sn and the respective inverted signals Is applied.
Each CMD is formed on the same substrate, and a substrate voltage V _SUB is applied to the substrate.

FIG. 10 is a signal waveform diagram for explaining the operation of the solid-state imaging device using the CMD imaging device shown in FIG. The signals Φ _G1 , applied to the row lines 2-1, 2-2,.
Φ _G2, ...... Φ _Gm is read gate voltage V _RD and the reset voltage V _RST, the overflow voltage V _OF, consists reserved voltage V _INT, during a horizontal effective period of the video signal in the non-selected rows are reserved voltage V _INT, Overflow voltage V _OF during horizontal retrace
In the selected row, the read gate voltage V _RD is used during the horizontal effective period of the video signal, and the reset voltage V _RST is used during the horizontal blanking period. Also, the column selection transistors 4-1 and 4-
2,... Φ _S1 , Φ _S2 ,.
... Φ _Sn is a signal for selecting the column lines 3-1, 3-2,..., 3-n.
4-2,..., 4-n turned off, anti-selection transistors 5-1, 5
... 5-n are turned on, the high level turns on the column selection transistors 4-1, 4-2,..., 4-n, and the anti-selection transistors 5-1, 5-2,. The voltage is set so that n is turned off, and the optical signal of each CMD pixel is sequentially read out to the signal line 6, amplified by the preamplifier 12 and output.

[Problems to be solved by the invention]

However, in the above-mentioned conventional solid-state imaging device, since the overflow operation of all pixels is performed during the horizontal retrace period, the following problem occurs. That is, the current discharged from the source of each pixel at the time of the overflow operation is almost the same as that at the time of signal reading, and therefore, these currents are supplied to each column line 3-1, 3-2,... When flowing into the commonly connected reference lines 7 via 1,5-2,..., 5-n, the current value becomes extremely large. Therefore, the power consumption increases, and the potential of each column line 3-1, 3-2,. There is a problem that is not performed.

The present invention has been made to solve the above-described problems in the conventional solid-state imaging device, and has a low power consumption and a CMD imaging device capable of performing overflow operation and reset operation with good characteristics or an imaging device similar thereto. It is an object to provide a solid-state imaging device using an element.

[Means and actions for solving the problem]

In order to solve the above problems, the present invention includes, as a component of one pixel, a transistor whose source / drain current is modulated by the amount of charge generated and accumulated by light irradiation, and arranging the pixels in a matrix. In a solid-state imaging device using a solid-state imaging device provided with a means for selecting the pixel and reading out a signal in a peripheral portion thereof, a terminal to which a drain or a source of each pixel is connected, and a reference for a source or a drain of each pixel during operation. When the terminal that gives the level is set to the video bias potential and the ground potential for the valid period of the video signal, respectively, while performing the overflow operation of the accumulated charge and the reset operation of the accumulated charge during the horizontal retrace period, The two terminals are set to the same potential through switching means individually connected to the respective terminals so that the potential difference between the two terminals is zero. It is intended to be configured so that.

With this configuration, the difference between the drain voltage and the source voltage of each pixel is reduced during the period in which the overflow operation and the reset operation are performed during the horizontal blanking period, and the source current of the pixel flowing through the above operation is extremely reduced. Can be smaller. As a result, a solid-state imaging device using a CMD imaging device or an imaging device similar to the CMD imaging device capable of realizing overflow operation and reset operation with low power consumption and favorable characteristics can be obtained.

〔Example〕

 Hereinafter, embodiments will be described.

FIG. 1 is a circuit diagram showing a first embodiment of a solid-state imaging device according to the present invention. Parts having the same functions as those of the conventional solid-state imaging device shown in FIG. The description is omitted. In this embodiment, the drain terminal 21 common to all pixels is connected to a switch 23 which opens and closes in synchronization with the horizontal retrace period of the video signal, and the valid period of the video signal is lower than the video bias potential V _DD (> 0). The power supply has an intermediate potential V ₀ (0 <V ₀ <V _DD ) between V _DD and GND during the retrace period of the video signal.
It is configured to be connected to a power supply. The reference line 7 is connected to a switch 22 which opens and closes in synchronization with the horizontal retrace period of the video signal.
D and the return period of the video signal is the intermediate potential V ₀ between V _DD and GND.
It is configured to be connected to a power supply. The signal line 6 is connected to a virtual grounded current-voltage conversion amplifier 12, so that the potential is maintained at GND.

Next, the operation of the solid-state imaging device thus configured will be described. During the valid period of the video signal, the common drain terminal 21 is at the potential _VDD supplied from the video bias power supply via the switch 23, and the reference line 7 is connected to GND via the switch 22. ,
The same operation as the conventional solid-state imaging device shown in FIGS. 9 and 10 is performed.

On the other hand, during the blanking period of the video signal, the drain terminal 21 is connected to the power supply of the intermediate potential V ₀ via the switch 23, and the source of each pixel is also connected to the intermediate potential V ₀ via the reference line 7 and the switch 22. ₀ power supply connected. For this reason, during the overflow operation of the excess accumulated charge and the reset operation of the accumulated charge during the blanking period of the video signal, the potential difference between the drain and the source of each pixel becomes zero and the source current does not flow.

FIG. 2 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG. Row line 2-1, 2-2, ...
The signals Φ _G1 , Φ _G2 ,... Φ _Gm applied to 2-m are composed of a read gate voltage V _RD1 , a reset voltage V _RST1 , an overflow voltage V _OF1 , and a storage voltage V _INT1 . The storage voltage V _INT1 during the horizontal valid period, the overflow voltage V _OF1 during the horizontal flyback period, and the read gate voltage V _RD1 during the horizontal valid period of the video signal in the selected row.
During the horizontal blanking period, the reset voltage V _RST1 is _maintained . The operation of the column selection transistors 4-1, 4-2,... 4-n and the anti-selection transistors 5-1, 5-2,. This is exactly the same as the conventional solid-state imaging device shown. Φ _D is a potential waveform applied to the common drain terminal 21 and Φ _REF is a potential waveform applied to the reference line 7.

Next, setting of the read voltage V _RD1 , the reset voltage V _RST1 , the overflow voltage V _OF1 , and the accumulation voltage V _INT1 will be described in comparison with the case of the conventional solid-state imaging device shown in FIGS. 9 and 10. At the time of reading and accumulation, the drain potential of each pixel is the video bias potential V _DD , and the source potential is each of the column lines 3-1, 3-2,.
Alternatively, it is kept at the GND potential via the reference line 7. Therefore, the read potential and the storage potential are V _RD = V
_The same effect can be obtained by setting the same value as in the case of the conventional solid-state imaging device shown in FIGS. 9 and 10, such as _RD1 , _VINT = _VINT1 .

On the other hand, the overflow operation is performed by the accumulated holes passing over the potential barrier formed in the channel by the drain and source electrodes of the CMD constituting each pixel, and is shown in FIGS. 9 and 10. In order to obtain the same overflow effect as in the conventional example, the overflow voltage V _OF1 in the present embodiment is connected to the power supply of the intermediate potential V ₀ via the switch 23 and the source is connected to the reference line 7 via the switch 23. because it is also connected to the power supply of the intermediate potential V ₀ which via 22, an amount corresponding to the potential barrier against holes is changed, it must be changed from the value of the conventional example.

The reset operation is performed by a mechanism in which holes accumulated directly under the gate graze the source end facing the gate and are discharged toward the substrate by a drift electric field. Therefore, in the reset operation, the gate voltage with respect to the source terminal becomes a problem. Therefore in order to obtain a case same reset effect as in the conventional example shown in Fig. 9 and Fig. 10, since the source potential than the conventional example is increased in correspondence to an intermediate potential V _0, correspondingly If a reset voltage V _RST1 (V _RST1 > V _RST ) higher than that of the conventional example is applied, a reset effect similar to that of the conventional example can be obtained in this embodiment.

Next, a second embodiment will be described. FIG. 3 is a circuit configuration diagram of a second embodiment of the present invention. Parts having the same functions as those of the conventional example shown in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. . In this embodiment, the drain terminal 21 common to all pixels is connected to a switch 24 that opens and closes in synchronization with the horizontal retrace period of the video signal, and the valid period of the video signal is lower than the video bias potential V _DD (> 0). It is connected to the power supply and to GND during the retrace period of the video signal. The reference line 7 is always connected to GND. The signal line 6 is connected to a virtual grounded current-voltage conversion amplifier 12, and the potential is
It is configured to be kept at GND.

During the valid period of the video signal, the drain terminal 21 is at the potential _VDD supplied from the video bias power supply via the switch 24, and the reference line 7 is at the G level.
Since it is connected to the ND, the same operation as in the conventional example shown in FIGS. 9 and 10 is performed.

On the other hand, during the blanking period of the video signal, the drain terminal 21 is connected to GND via the switch 24, and the source of each pixel is connected to GND via the reference line 7. Therefore, during a period in which the overflow operation of the excess accumulated charge and the reset operation of the accumulated charge are performed during the blanking period of the video signal, the potential difference between the drain and the source of each pixel becomes zero, and no source current flows.

FIG. 4 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG. Row line 2-1, 2-2, ...
The signals Φ _G1 , Φ _G2 ,... Φ _Gm applied to the 2-m are composed of a read gate voltage V _RD2 , a reset voltage V _RST2 , an overflow voltage V _OF2 , and a storage voltage V _INT2. During the horizontal valid period, the accumulated voltage V _INT2 becomes the overflow voltage V _OF2 during the horizontal _flyback period, and the read gate voltage V during the horizontal valid period of the video signal in the selected row.
_RD2 becomes the reset voltage V _RST2 during the horizontal retrace period. The operation of the column selection transistors 4-1, 4-2,... 4-n and the anti-selection transistors 5-1, 5-2,. This is exactly the same as the conventional example shown.

Next, the setting of the read voltage V _RD2 , the reset voltage V _RST2 , the overflow voltage V _OF2 , and the storage voltage V _INT2 will be described in comparison with the case of the conventional example shown in FIGS. 9 and 10. At the time of readout and accumulation, the drain potential of each pixel is the video bias potential V _DD , and the source potential is via each column line 3-1, 3-2,... 3-n and the signal line 6 or the reference line 7. It is kept at GND potential. Therefore, the read potential and the storage potential are V _RD = V _RD2 , V _INT = V
_The same effect can be obtained by setting the same value as in the case of the conventional example shown in FIGS. 9 and 10 like _INT2 .

On the other hand, the overflow operation is performed by the accumulated holes passing over the potential barrier formed in the channel by the drain and source electrodes of the CMD constituting each pixel, and is shown in FIGS. 9 and 10. In order to obtain the same overflow effect as in the conventional example, the overflow voltage V _OF2 in the present embodiment is applied by connecting the drain to the GND via the switch 21 and the source to the GND via the reference line 7. Therefore, the value of the conventional example is reduced by the lower potential barrier against holes.
Must change from V _OF . That is, V _OF2 <V
Must be set to _OF .

The reset operation is performed by a mechanism in which holes accumulated directly under the gate graze the source end facing the gate and are discharged toward the substrate by a drift electric field. Therefore, in the reset operation, the gate voltage with respect to the source terminal becomes a problem. Therefore, in order to obtain the same reset effect as that of the conventional example shown in FIGS. 9 and 10, the same reset voltage as that of the conventional example, that is, V _RST2 = V _RST
With this setting, a reset effect similar to that of the conventional example can be obtained in this embodiment.

According to the present embodiment, when the overflow operation and the reset operation are performed, since the excessive current does not flow through the reference line 7, the optimal overflow operation and the reset operation are performed. Furthermore, according to this embodiment, the signals Φ _G1 , Φ _G2 ,
...... reserved voltage V _INT2 and the reset voltage V _RST2 which determines the maximum amplitude of [Phi _Gm is, in order to obtain the same effect as the conventional example is quite good Kotor becomes the same as the conventional example. For this reason, it is possible to use the same device as the conventional CMD solid-state imaging device and improve the performance only by changing the external driving method.

Next, a third embodiment will be described. FIG. 5 is a circuit configuration diagram of a third embodiment of the present invention, in which parts having the same functions as in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. In this embodiment, the reference line 7 is
Switch 25 that opens and closes in synchronization with the horizontal retrace period of the video signal
Via the video bias potential during the retrace period of the video signal
The power supply of V _DD (> 0) is configured to be connected to GND during the valid period of the video signal. The drain terminal 21 common to all pixels is always connected to the power supply of the video bias potential V _DD (> 0). The signal line 6 is connected to a virtual grounded current-voltage conversion amplifier 12, so that the potential is kept at GND.

Since the reference line 7 is connected to GND via the switch 25 and the drain terminal 21 is at the video bias potential V _DD during the valid period of the video signal, FIGS. 9 and 10 The operation is exactly the same as that of the conventional example shown in FIG.

On the other hand, during the blanking period of the video signal, the source of each pixel is at the video bias potential V _DD via the reference line 7 and the switch 25, and the drain terminal 21 common to all pixels is at the video bias potential. Connected to V _DD power supply. For this reason, during the overflow operation of the excess accumulated charge and the reset operation of the accumulated charge during the blanking period of the video signal, the potential difference between the drain and the source of each pixel becomes zero and the source current does not flow.

FIG. 6 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG. Row line 2-1, 2-2, ...
Signal [Phi _G1 applied to ... _{2-m, Φ G2, ......} Φ Gm is read gate voltage V _RD3, the reset voltage V _{RST 3,} the overflow voltage V _OF3, consists reserved voltage V _INT3, the video signal is in the non-selected row During the horizontal valid period, the accumulated voltage V _INT3 becomes the overflow voltage V _OF3 during the horizontal _flyback period, and the read gate voltage V during the horizontal valid period of the video signal in the selected row.
_RD3 becomes the reset voltage V _RST3 during the horizontal retrace period. The operation of the column selection transistors 4-1, 4-2,... 4-n and the anti-selection transistors 5-1, 5-2,. This is exactly the same as the conventional example shown.

Next, the setting of the read voltage V _RD3 , the reset voltage V _RST3 , the overflow voltage V _OF3 , and the accumulation voltage V _INT3 will be described in comparison with the case of the conventional example shown in FIGS. 9 and 10. At the time of reading and accumulation, the drain potential of each pixel is set to the video bias potential V _DD , and the source potential is set to each column line 3-1, 3-2,... 3-n and the signal line 6 or the reference line 7. It is kept at the GND potential via.
Therefore, the read potential and the storage potential are V _RD = V _RD3 , V _INT =
If _VINT3 is set to the same value as in the case of the conventional example shown in FIGS. 9 and 10, the same effect can be obtained.

On the other hand, the overflow operation is performed by the accumulated holes passing over the potential barrier formed in the channel by the drain and source electrodes of the CMD constituting each pixel, and is shown in FIGS. 9 and 10. In order to obtain the same overflow effect as that of the conventional example, the overflow voltage V _OF3 in this embodiment is applied to the source, and the video bias potential V _DD is applied to the source via each column line, the reference line 7 and the switch 25. Runode amount corresponding to the potential barrier is raised with respect to the hole must be changed from the value V _oF conventional example. That is, V _OF3 > V
Must be set to _OF .

The reset operation is performed by a mechanism in which holes accumulated directly under the gate graze the source end facing the gate and are discharged toward the substrate by a drift electric field. Therefore, in the reset operation, the gate voltage with respect to the source terminal becomes a problem. Therefore, in order to obtain the same reset effect as in the case of the conventional example shown in FIGS. 9 and 10, the source potential, which is the GND potential in the conventional example, becomes the video bias potential V _{DD in the} present embodiment. Therefore, if a reset voltage higher than that of the conventional example is applied, a reset effect similar to that of the conventional example can be obtained in the present embodiment. That is, it is necessary to set V _RST3 > V _RST .

According to the present embodiment, when the overflow operation and the reset operation are performed, since the excessive current does not flow through the reference line 7, the optimal overflow operation and the reset operation are performed. Furthermore, according to this embodiment, it is possible to supply a video bias which greatly affects the quality of a video signal to the drain terminal 21 in a DC manner, so that the drain bias in each pixel becomes extremely stable, and It is characterized in that a high quality image signal can be obtained.

Next, a fourth embodiment will be described. FIG. 7 is a circuit configuration diagram of a fourth embodiment of the present invention. Portions having the same functions as in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. FIG. 8 is a signal waveform diagram for explaining the operation of the solid-state imaging device using the CMD solid-state imaging device shown in FIG. This embodiment is characterized in that the intermediate potential V ₀ in the first embodiment is set as follows: V ₀ = V ₀₀ ≡V _DD · C _D / (C _D + C _R ) (1) is there. Here C _D is the parasitic capacitance (not shown) of the drain terminal 21, C _R is a parasitic capacitance (not shown) of the reference line 7. In order to switch these terminals every horizontal retrace period, these terminals need to be charged or discharged. The energy required for one charge or discharge is Therefore, when the intermediate potential is set according to the equation (1), the energy U consumed during charging / discharging is minimized, and Take the value of

According to the present embodiment, the effect that the power consumption caused by charging / discharging the drain terminal 21 and the reference line 7 common to all pixels every horizontal retrace period can be reduced as compared with the other embodiments.

The above embodiments have been described using the N-channel CMD solid-state imaging device. However, if the relationship of each bias is reversed, the same effect can be obtained even when the P-channel CMD solid-state imaging device is used. It is clear that it can be obtained.
In each of the above embodiments, the solid-state imaging device using the CMD solid-state imaging device has been described. However, like the SIT solid-state imaging device disclosed in Japanese Patent Application Laid-Open No. In a solid-state imaging device including, as a component of one pixel, a transistor in which a current flowing between a source and a drain is modulated by an amount of charge generated and accumulated by irradiation, a reset operation of accumulated charge during a period in which no signal is taken out from the pixel. The present invention can be applied to a solid-state imaging device using a solid-state imaging device that performs an overflow operation of an excessively accumulated charge, and an effect equivalent to that described in the above embodiment can be obtained. It is clear.

〔The invention's effect〕

As described above with reference to the embodiments, according to the present invention, a conventional solid-state imaging device is used because an excessive current does not flow when performing a reset operation of accumulated charges and an overflow operation of excessively accumulated charges. As a result, a solid-state imaging device can be obtained in which not only low power consumption can be achieved but also an optimal reset operation of accumulated charges and an overflow operation of excessively accumulated charges are performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the solid-state imaging device according to the present invention. FIG. 2 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG. FIG. 4 is a circuit diagram showing a second embodiment of the present invention. FIG. 4 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG.
FIG. 5 is a circuit diagram showing a third embodiment of the present invention, and FIG.
FIG. 7 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG. 5, FIG. 7 is a circuit configuration diagram showing a fourth embodiment of the present invention, and FIG. 9 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG. 9, FIG. 9 is a circuit configuration diagram showing a configuration example of a conventional solid-state imaging device, and FIG.
FIG. 4 is a signal waveform diagram for describing an operation of the solid-state imaging device illustrated in FIG. In the figure, 1-11, 1-12,..., 1-mn are CMD pixels,
1,2-2,... 2-m is a row line, 3-1,3-2,.
.., 4-n are column selection transistors, 5-1, 5-2,..., 5-n are anti-selection transistors, 6 is a signal line, and 7 is a reference. A line, 9 is an output terminal, 10 is a vertical scanning circuit, 11 is a horizontal scanning circuit, 21 is a drain terminal, and 22, 23, 24, and 25 indicate changeover switches.

Claims (6)

(57) [Claims] 1. A pixel comprising, as a component of one pixel, a transistor whose source / drain current is modulated by an amount of charge generated and accumulated by light irradiation, the pixels are arranged in a matrix, and the pixels are arranged in a peripheral portion thereof. In a solid-state imaging device using a solid-state imaging device provided with means for selecting and reading a signal,
The terminal to which the drain or source of each pixel is connected, and the terminal that gives the reference level of the source or drain of each pixel during operation, the effective period of the video signal is set to a video bias potential and a ground potential, respectively. When performing an overflow operation of the charge accumulated excessively during the horizontal retrace period and a reset operation of the accumulated charge, the potential difference between the two terminals is set to zero through switching means individually connected to the terminals. A solid-state imaging device configured to be set to an equipotential. 2. A method according to claim 1, wherein a transistor whose source / drain current is modulated by an amount of charge generated and accumulated by light irradiation is included as a component of one pixel, said pixels are arranged in a matrix, and said pixels are arranged in a peripheral portion thereof. In a solid-state imaging device using a solid-state imaging device provided with means for selecting and reading a signal,
The terminal to which the drain or source of each pixel is connected, and the terminal that gives the reference level of the source or drain of each pixel during operation, the effective period of the video signal is set to a video bias potential and a ground potential, respectively. When performing an overflow operation of the charge excessively accumulated during the horizontal retrace period and a reset operation of the accumulated charge, the terminal for providing the reference level of the source or drain of each pixel during the operation is connected to the switching means connected to the terminal. A solid-state imaging device configured to be set to a video bias potential via the power supply. 3. A transistor having a source / drain current modulated by an amount of charge generated and accumulated by light irradiation as a component of one pixel, the pixels are arranged in a matrix, and the pixels are arranged in a peripheral portion thereof. In a solid-state imaging device using a solid-state imaging device provided with means for selecting and reading a signal,
The terminal to which the drain or source of each pixel is connected, and the terminal that gives the reference level of the source or drain of each pixel during operation, the effective period of the video signal is set to a video bias potential and a ground potential, respectively. When performing an overflow operation of charges accumulated excessively in the horizontal retrace period and a reset operation of accumulated charges, the terminal to which the drain or the source is connected is set to the ground potential through switching means connected to the terminal. A solid-state imaging device characterized by the following. 4. The solid-state imaging device according to claim 1, wherein the potential applied to both terminals when performing an overflow operation of an excessively accumulated charge and a reset operation of the accumulated charge is a video bias potential. the V _DD, when C _D parasitic capacitance of the drain or terminal whose source is connected, the parasitic capacitance of the terminal for providing a reference level of the source and the drain of each pixel during the operation was C _R, V _DD · C _D / (C _D + C _R )
A solid-state imaging device having an intermediate potential between a video bias potential and a ground potential determined by: 5. The solid-state imaging device according to claim 1, wherein both a terminal to which a drain or a source of each pixel is connected and a terminal which provides a reference level of the source or drain of each pixel during operation are horizontal return. When set to the ground potential during the line period, the overflow voltage during the horizontal retrace period, the terminal to which the drain or source of each pixel is connected during any of the effective period of the video signal and the horizontal retrace period, and A solid-state imaging device characterized in that, during operation, a terminal for providing a reference level of a source or a drain of each pixel is set lower than a case where the terminal is fixed to a video bias potential and a ground potential, respectively. 6. The solid-state imaging device according to claim 2, wherein both the terminal to which the drain or the source of each pixel is connected and the terminal which gives the reference level of the source or the drain of each pixel during operation are in a horizontal blanking period. When the video bias potential is set to the overflow voltage during the horizontal retrace period, the drain or source of each pixel is connected to the terminal to which the drain or source of each pixel is connected during the effective period of the video signal and the horizontal retrace period, and A solid-state imaging device, wherein a terminal for providing a reference level of a source or a drain of each pixel during operation is set higher than a case where the terminal is fixed to a video bias potential and a ground potential, respectively.