JPH10243301A - Charge-to-voltage converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge-to-voltage converting circuit with which conversion efficiency is improved by suppressing the amplitude of the reset pulse. SOLUTION: A charge-to-voltage converting part 1 coverts a signal charge to a voltage signal. A clamp transistor 2 receives the voltage signal and generates a clamp signal of a fixed voltage level by a clamp pulse from the outside. A reset transistor 3 receives the supply of the clamp signal and resets the charge-to-voltage converting part 1 at a fixed voltage level for each pixel corresponding to the external reset pulse. An image signal output part 4 performs the impedance conversion of the voltage signal and outputs it as an image signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-to-voltage conversion circuit, and more particularly to a charge-to-voltage conversion circuit that converts a signal charge into a voltage signal in an image pickup device using a CCD and outputs it as an image signal.

[0002]

2. Description of the Related Art A CCD (Charge Coupled Device), which is a solid-state image sensor, is widely used in television cameras and video cameras as a converter for converting an optical image into an electric signal.

The CCD has a structure in which a large number of electrodes are sequentially arranged on a p-type semiconductor substrate via a silicon oxide film. Then, the value of the voltage applied to each electrode is moved in order, and the signal charge having a magnitude proportional to the value of the incident light stored under the electrode is accumulated and transferred repeatedly to move the signal charge. Thereafter, the signal charge is sent to a charge-voltage conversion circuit, where the charge is converted into a voltage, and is output as an image signal.

FIG. 10 is a configuration diagram of a charge-to-voltage conversion circuit having a conventional floating diffusion amplifier (FDA) configuration. The signal charges transferred by the horizontal CCD (H-CCD) are injected into a floating diffusion (FD) 1a via an output gate (HOG), where they are converted into a voltage signal.

The reset transistor Qrs resets the FD 1a for each pixel in response to a reset pulse φRG applied to the reset gate RG,
Further, the voltage is clamped to the reset drain voltage VRD (= VDD) applied to the reset drain. The voltage signal obtained by the FD 1a is output to a source follower circuit 4 as an output circuit.
The impedance is converted by “a” and is derived as an output signal OUT.

Here, the above FD1a includes Crd, Cp
Parasitic capacitances such as w, Cog, Crg, Cdg, and Cgs are attached. Crd is a parasitic capacitance between the drain terminal of the reset transistor Qrs and the FD 1a. When the connection point between the gate terminal of the first-stage drive transistor Qd of the source follower circuit 4a and the FD 1a is a node N, Cp
w is the parasitic capacitance between the node N and the ground, Cog is the parasitic capacitance between the node N and the gate terminal of the HOG, Crg
Is a parasitic capacitance between the node N and the gate terminal of the reset transistor Qrs, and Cdg and Cgs are parasitic capacitances between the node N and the drain terminal and the source terminal of the drive transistor Qd. These parasitic capacitances cause a reduction in conversion efficiency.

Therefore, conventionally, in order to increase the conversion efficiency of the charge-voltage conversion circuit, the size of the reset transistor Qrs has been reduced, the parasitic capacitance added to the FD 1a has been reduced, and the conversion efficiency has been improved.

[0008]

However, when the size of the reset transistor Qrs is reduced as described above,
The short channel effect and the narrow channel effect occur, and there is a problem that the reset pulse amplitude must be increased in order to secure the dynamic range of the reset operation of the FD 1a.

For example, when the maximum value of the CCD output signal amplitude is 0.
If the voltage is 6V, the short channel effect and the narrow channel effect do not occur at the gate terminal of the reset transistor Qrs, and if the gain is about 1, the required reset pulse amplitude becomes 0.6V + variation component. However, the required reset pulse amplitude is actually 2 V or more due to the short channel effect and the narrow channel effect.

Further, when the reset drain signal is a DC bias, there is a problem that the parasitic capacitance (= Crd) between the FD 1a and the reset drain terminal hinders the improvement of the conversion efficiency.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and an object of the present invention is to provide a charge-voltage conversion circuit that suppresses a short channel effect and a narrow channel effect to reduce the reset pulse amplitude. .

Another object of the present invention is to provide a charge-voltage conversion circuit that reduces the parasitic capacitance between the FD and the reset drain to improve the conversion efficiency.

[0013]

According to the present invention, there is provided a charge-voltage conversion circuit for converting a signal charge into a voltage signal in an image sensor using a CCD and outputting the signal as an image signal. A charge-to-voltage conversion unit that converts charge into the voltage signal, a clamp transistor that receives a feedback of the voltage signal, generates a clamp signal that is clamped to a constant voltage level by an external clamp pulse, and the clamp signal. And a reset transistor that resets the charge-voltage converter to the constant voltage level for each pixel by an external reset pulse, and an image signal that performs impedance conversion of the voltage signal and outputs the image signal as the image signal And an output unit.

Here, the charge-voltage converter converts the signal charge into a voltage signal. The clamp transistor receives the voltage signal and generates a clamp signal that is clamped to a constant voltage level by an external clamp pulse. The reset transistor receives the supply of the clamp signal and resets the charge-voltage converter to a constant voltage level for each pixel by an external reset pulse. The image signal output unit performs impedance conversion of the voltage signal and outputs the result as an image signal.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of a charge-voltage conversion circuit according to the present invention. The charge-voltage converter 1 converts the transferred signal charges into a voltage signal. The clamp transistor 2 receives the supply of the voltage signal generated by the charge-voltage converter 1 by feedback. Then, a clamp signal that is clamped to a constant voltage level by an external clamp pulse is generated.

Upon receiving the clamp signal, the reset transistor 3 resets the charge-voltage converter 1 to the same constant voltage level as the clamp signal for each pixel by an external reset pulse. The image signal output section 4 performs impedance conversion of the voltage signal and outputs the image signal as an image signal.

Next, the operation will be described. FIG. 2 is a flowchart showing the operation procedure of the charge-voltage conversion circuit of the present invention. [S1] The charge-voltage converter 1 converts signal charges into voltage signals. [S2] The image signal output section 4 performs impedance conversion of the voltage signal and outputs the image signal as an image signal. [S3] The clamp transistor 2 receives the voltage signal and generates a clamp signal clamped to a constant voltage level by an external clamp pulse. [S4] The reset transistor 3 receives the supply of the clamp signal, and resets the charge-voltage converter 1 to the same constant voltage level as the clamp signal for each pixel by an external reset pulse.

Next, a first embodiment of the present invention will be described. FIG. 3 is a configuration diagram of the first embodiment. Horizontal CCD
The signal charges transferred by the (H-CCD) are injected into a floating diffusion (FD) 1a via an output gate (HOG), where they are converted into a voltage signal. The voltage signal obtained by the FD 1a is subjected to impedance conversion by a source follower circuit 4a, which is an image signal output unit 4, and is derived as an image signal OUT. Also,
Clamp transistor Qc and reset transistor Qr
Are connected in cascode, and connected to the FD 1a at the node N.

A signal obtained by capacitively coupling the output of the drive transistor Qd of the first stage of the source follower circuit 4a with the capacitor C1 is superimposed on the reset drain RD, and the DC level is clamped to the power supply VDD by the clamp transistor Qc and the reset pulse. give.

Since the clamp pulse and the reset pulse are common via the reset gate RG, the FD 1a is always reset to the VDD level. During the accumulation period of the FD1a in which the reset pulse is at the L level, the clamp transistor Qc is also turned off, the potential of the reset drain RD changes in proportion to the potential of the FD1a, and Vds of the reset transistor Qr becomes constant.

As a result, the execution amplitude does not decrease due to the short channel effect or the narrow channel effect of the reset gate RG. Clamp transistor Qc is FD
Since it is capacitively separated from 1a, the transistor size can be increased so that it can operate even with a low-amplitude clamp pulse. As a result, the ON / OFF operation of the clamp transistor Qc can be performed at a low amplitude, and the amplitude of the clamp pulse can be reduced. Further, the reset transistor Qr
Of the reset drains RD and F
The apparent capacity (= Crd) between D1a can be reduced, and the conversion efficiency is improved. Next, a second embodiment of the present invention will be described. FIG. 4 is a configuration diagram of the second embodiment. Second
In the embodiment, the drive transistor Qd of the first embodiment is used.
Cascode-connected to the feedback transistor Qf, and the output of the drive transistor Qd is connected to the capacitor C1.
The signal capacitively coupled by the feedback transistor Qf
I'm also hanging on the gate.

As a result, the apparent capacitance (= Cdg) between the drain and the gate of the drive transistor Qd can be reduced, and the conversion efficiency is dramatically improved. Further, since a signal to be fed back can be shared, high performance can be realized by adding one transistor.

Further, it is possible to reduce the reset gate pulse amplitude by making Vds of the reset gate RG constant. Next, a third embodiment of the present invention will be described. FIG. 5 is a configuration diagram of the third embodiment. In the first and second embodiments described above, the amplitude of the reset pulse can be reduced only when the Vth between the clamp transistor Qc and the reset transistor Qr always has a strong correlation. However, when the correlation is weak, the reset pulse is reset by the variation. It is necessary to increase the pulse amplitude.

Therefore, the third embodiment is different from the second embodiment in that the clamp pulse input terminal of the clamp transistor Qc and the reset pulse input terminal of the reset transistor Qr are capacitively coupled by the capacitor C2 to provide a clamp pulse. The configuration is such that a bias adjustment circuit 5a is added to the input terminal.

As a result, the variation in Vth of the clamp transistor Qc can be completely absorbed, and both a reduction in the amplitude of the reset pulse and an improvement in the conversion efficiency by reducing Crd and Cdg are realized. Further, the configuration of the bias adjustment circuit 5a may use a low clamp circuit utilizing a memory effect.

Next, a fourth embodiment of the present invention will be described. FIG. 6 is a configuration diagram of the fourth embodiment. The fourth embodiment is different from the third embodiment in that the reset transistor Qr
And the bias adjusting circuit 5b is capacitively coupled by a capacitor C3. Thereby, it is possible to cope with Vth variation of the reset gate RG. Further, it is possible to achieve both a reduction in the reset gate pulse amplitude by making Vds of the reset gate RG constant and an improvement in conversion efficiency by reducing Crd and Cdg.

Next, a fifth embodiment of the present invention will be described. FIG. 7 is a configuration diagram of the fifth embodiment. In the fifth embodiment, a bias circuit having an adjustment function using a memory effect is used instead of operating with the clamp transistor Qc. The bias circuit 6 includes a buffer transistor Q
b. The drive terminal of the buffer transistor Qb is connected to VDD, the other end of the load resistor R1 is connected to GND, and the source terminal is connected to the reset drain RD of the reset transistor Qr.

Here, a constant current source 6 is used instead of the load resistor R1.
b may be used. The constant current source 6b has better linearity of input / output characteristics. Then, the gate terminal of the buffer transistor Qb is connected to the drain terminal via the resistor R2 so that the specific gate bias is applied by the reset drain bias circuit (RDi) 6a.

Thus, the Vth variation of the RG can be canceled by adjustment, so that the amplitude of the reset pulse can be reduced. Also, Vds of the reset gate RG
Reduction of reset gate pulse amplitude by stabilization and C
It is possible to improve conversion efficiency by reducing rd and Cdg.

Further, since the average value is clamped to VDD, there is no need to worry about the dynamic range of the clamp transistor Qc. Next, a sixth embodiment of the present invention will be described. FIG. 8 is a configuration diagram of the sixth embodiment. The sixth embodiment has a configuration using a bias circuit 6-1 in which the buffer transistor Qb is also used as the feedback transistor Qf. This achieves high conversion efficiency, low reset pulse amplitude, and prevention of the burden of adjustment work while reducing the circuit scale.

Further, since the Vth variation of RG can be canceled by adjustment, the amplitude of the reset pulse can be reduced. Further, the reset pulse amplitude is reduced by making Vds of the reset gate RG constant, and Crd, Cd
The conversion efficiency can be improved by reducing g.

Furthermore, since the average value is clamped to VDD, there is no need to worry about the dynamic range of the clamp transistor Qc. Next, a CCD area sensor will be described as an application example of the charge-voltage conversion circuit of the present invention. FIG. 9 is a configuration diagram of the CCD area sensor 10.
The imaging area 11 includes a sensor unit 12 and a vertical CCD (V-C
CD) 13. The sensor units 12 are arranged in a matrix and convert incident light into signal charges having a charge amount corresponding to the light amount. The V-CCDs 13 are provided in a vertical column between the sensor units 12, and vertically transfer signal charges read from the respective sensor units 12.

The horizontal CCD (H-CCD) 14 sequentially and horizontally transfers signal charges transferred from the plurality of V-CCDs 13 in line units. A charge-voltage conversion circuit 20 according to the present invention is provided at an end on the transfer destination side of the H-CCD 14 via an output gate (OG). The voltage signal obtained by the charge-voltage conversion is subjected to impedance conversion by the source follower circuit 4a, and is derived as an output signal OUT.

[0034]

As described above, the charge-voltage converter of the present invention feeds back the voltage signal converted from the signal charge by the charge-voltage converter to generate a clamp signal clamped at a constant voltage level. The charge-voltage converter is reset to a constant voltage level based on the clamp signal.

As a result, the occurrence of the short channel effect and the narrow channel effect at the gate terminal of the reset transistor is suppressed, so that the amplitude of the input reset pulse can be reduced. In addition, since the parasitic capacitance between the charge-voltage converter and the drain terminal of the reset transistor is reduced, the conversion efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a charge-voltage conversion circuit of the present invention.

FIG. 2 is a flowchart showing an operation procedure of the charge-voltage conversion circuit of the present invention.

FIG. 3 is a configuration diagram of a first embodiment.

FIG. 4 is a configuration diagram of a second embodiment.

FIG. 5 is a configuration diagram of a third embodiment.

FIG. 6 is a configuration diagram of a fourth embodiment.

FIG. 7 is a configuration diagram of a fifth embodiment.

FIG. 8 is a configuration diagram of a sixth embodiment.

FIG. 9 is a configuration diagram of a CCD area sensor.

FIG. 10 is a configuration diagram of a conventional charge-voltage conversion circuit having an FDA configuration.

[Explanation of symbols]

1 ... Charge-voltage converter, 2 ... Clamp transistor,
3 ... Reset transistor, 4 ... Image signal output unit.

Claims (9)

[Claims] A charge-voltage converter for converting a signal charge into a voltage signal in an image sensor using a CCD and outputting the signal charge as an image signal; a charge-voltage converter for converting the signal charge into the voltage signal; A clamp transistor that receives a supply of the voltage signal and generates a clamp signal that is clamped to a constant voltage level by an external clamp pulse; A charge-to-voltage conversion circuit comprising: a reset transistor that resets the pixel to the constant voltage level for each pixel by a reset pulse; and an image signal output unit that performs impedance conversion of the voltage signal and outputs the image signal as the image signal. . 2. The charge-voltage conversion circuit according to claim 1, wherein the clamp pulse input to the clamp transistor and the reset pulse input to the reset transistor have a common supply source. 3. The charge-voltage conversion circuit according to claim 1, wherein different DC biases are applied to a gate terminal of the clamp transistor and a gate terminal of the reset transistor. 4. A bias adjusting circuit for applying the DC bias to the gate terminal of the clamp transistor,
4. A DC bias adjusting function.
The charge-voltage conversion circuit according to any one of the preceding claims. 5. The charge-voltage conversion circuit according to claim 4, wherein the bias adjustment circuit has the DC bias adjustment function using a memory effect. 6. The charge-voltage conversion circuit according to claim 1, wherein said clamp transistor is larger in size than said reset transistor. 7. The charge-voltage conversion circuit according to claim 1, wherein the voltage signal is superimposed on a reset drain signal of the clamp transistor via a bias circuit. 8. The charge-voltage conversion circuit according to claim 7, wherein said bias circuit has a DC bias adjustment function using a memory effect. 9. The charge-voltage conversion circuit according to claim 1, wherein a drain terminal of the reset transistor is connected to a power supply terminal of a drive transistor connected to the charge-voltage conversion unit.