JPH07236091A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To improve speed signal output and to reduce noise by converting an electric charge generated by a light receiving element, a picture element, into a signal voltage by a voltage generation means and outputting the signal voltage converted into the signal current by a voltage/current conversion means to an output signal line. CONSTITUTION:The output signal voltage from a picture element MOS transistor 1 obtained by the source follower operation between a picture element MOS transistor 1 and a load MOS transistor 12 is held in a sample-and-hold circuit 12. It is converted into the signal current by a horizontal driving MOS transistor 14 and is outputted to a horizontal signal line 16. In short, the horizontal driving MOS transistor 14 is designed so that the channel width is wider than that of the picture element MOS transistor 1 and the mutual conductance becomes wider than that of the picture element MOS transistor 1. Then, the signal current of the horizontal signal line 16 is increased. Thus, the conversion gain of the current/voltage conversion circuit to be connected is decreased and the load resistance can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to an amplification type solid-state image pickup device.

[0002]

2. Description of the Related Art In response to a demand for higher resolution of a solid-state image pickup device, development of an internal amplification type solid-state image pickup device for amplifying optical signal charges for each pixel is in progress. The main components of this internal amplification type solid-state imaging device are electrostatic induction transistors (S
Various image pickup device structures such as IT), amplification type MOS imager (AMI), charge modulation device (CMD), BASIS using a bipolar transistor in a pixel are known.

On the other hand, the following amplification type solid-state image pickup device also
That is one. In this amplification type solid-state imaging device, holes (signal charges) obtained by photoelectric conversion are converted into n-channel MO.
It is stored in a p-type potential well of an S transistor (pixel MOS transistor), and a change in channel current based on a potential change in the p-type potential well (that is, a change in backgate potential) is output as a pixel signal. There is.

FIG. 8 shows an example of a conventional amplification type solid-state image pickup device. In this amplification type solid-state imaging device 10, a plurality of pixel transistors, for example, pixel MOS transistors [unit pixels (cells)] 1 are arranged in a matrix as shown in FIG.
The gate of each pixel MOS transistor 1 is connected to a vertical selection line 3 selected by a vertical scanning circuit 2 including a shift register, the drain thereof is connected to a power supply V _DD , and the source thereof is connected to a vertical signal line 4. Connected. Each vertical signal line 4 is connected to a horizontal signal line 6 via a horizontal MOS switch 5. 7 is a horizontal scanning circuit consisting of a shift register or the like, the scanning signal phi _H from the horizontal scanning circuit 7
[Φ _H1, ... φ _Hn, φ _{Hn + 1,} ...] are sequentially supplied to the gate of the horizontal MOS switch 5. The horizontal scanning circuit 7, the horizontal MOS switch 5, and the horizontal signal line 6 constitute a horizontal scanning output circuit 9.

In this amplification type solid-state imaging device 10, a unit pixel, that is, a pixel MOS transistor 1 is vertically selected by a scanning signal φ _V [φ _V1, ... φ _Vi, φ _{Vi + 1,} ...] From a vertical scanning circuit 2. By sequentially turning on the horizontal MOS switch 5 selected through the line 3 and connected to the horizontal scanning circuit 7, the current signal converted by the pixel MOS transistor 1 is directly output to the horizontal signal line 6 through the vertical signal line 4. .

As another example of the horizontal scanning output circuit 9 in the amplification type solid-state image pickup device, there is a capacitive load operation system (not shown), and there is also a system in which a voltage signal is output as a charge to a horizontal signal line.

[0007]

By the way, in the above-mentioned solid-state image pickup device 10, fixed pattern noise (FPN) peculiar to the amplification type solid-state image pickup device in which each pixel has an amplifying action is generated. That is, for example, in the case of a pixel MOS transistor, fixed pattern noise occurs due to the variation in Vth of each pixel. An image storage device such as a frame memory is required to remove this fixed pattern noise.

On the other hand, in the solid-state image pickup device, the number of pixels is increased and the chip size is reduced, so that the size of the amplification type pixel transistor is reduced. As a result, the conductance of the pixel transistor is inevitably reduced.

In the solid-state imaging device 10 of FIG. 6 described above, the current signal converted by the pixel MOS transistor 1 is directly output to the horizontal signal line 6 through the vertical signal line 4, so that the pixel MOS transistor 1 can be miniaturized. As the conductance becomes smaller as a result, the signal current amount becomes smaller and the SN becomes worse. Further, since the vertical signal line 4 and the horizontal signal line 6 are connected to each other, the parasitic capacitance becomes large due to the capacitance of the vertical signal line 4 and the capacitance of the horizontal signal line 6, and the reading speed of the pixel signal becomes slow.

Further, in the case of the amplification type solid-state image pickup device which outputs the voltage signal to the horizontal signal line by the capacitive load operation system, since the output circuit is composed of a high impedance MOS transistor, The reading speed becomes slow. If the load resistance is reduced, the speed increases but the SN deteriorates.

In view of the above points, the present invention provides a solid-state image pickup device capable of outputting pixel signals at high speed and with low noise.

The present invention also provides a solid-state image pickup device capable of removing fixed pattern noise.

[0013]

A solid-state image pickup device according to a first aspect of the present invention includes a plurality of light receiving elements 1 and voltage generating means (1, 12) for converting charges generated in the light receiving elements 1 into a voltage.
When a voltage-current conversion unit 14 to output the voltage to the output signal line 16 is converted into a signal current, a demodulation means 18 for demodulating the signal current into a signal voltage, and a light-receiving element 1 is first power supply V _DD It has a first MOS transistor connected between it and the vertical signal line 4, the vertical signal line 4 is grounded via the load element 12, and the voltage-current conversion means 14 is connected to the first power source or the second power source. The second MOS transistor is connected to the output signal line 16, and the gate voltage of the second MOS transistor is connected to the voltage generating means (1, 12). The mutual conductance is set to be larger than the mutual conductance of the first MOS transistor 1.

A second invention is the solid-state image pickup device according to the first invention, wherein the demodulating means 18 includes a bipolar transistor 19.

A third invention is the solid-state image pickup device according to the first or second invention, wherein the second MOS transistor 14 is provided.
Is set to be larger than the channel width of the first MOS transistor 1.

A solid-state image pickup device according to a fourth aspect of the invention corresponds to a plurality of light receiving elements 1, voltage generating means (1, 12) for converting charges generated in the light receiving elements 1 into a voltage, and each light receiving element 1. First and second sample and hold circuits 13A and 1A
3B, and the pixel signal output voltage held in the first and second sample hold circuits 13A and 13B and the pixel signal output voltage after pixel reset, respectively, are converted into currents, and
And the first output to the second output signal lines 16A and 16B
And second voltage-current conversion means 14A and 14B, and the first
And first and second demodulating means 18A (or 32A) and 18B (or 32B) for demodulating the respective signal currents from the second and current voltage-current converting means 14A and 14B into signal voltages.
And the second demodulation means 18B (or 32) from the pixel signal output voltage demodulated by the first demodulation means 18A (or 32A).
The subtraction circuit 26 for subtracting the pixel signal output voltage after the pixel reset demodulated in B) is provided.

[0017]

According to the first aspect of the invention, the light receiving element 1 serving as a pixel is provided.
By converting the electric charges generated in 1 into a signal voltage in the voltage generating means (1, 12), converting the signal voltage into a signal current in the voltage / current converting means 14 and outputting the signal current to the output signal line 16, the pixel signal is converted. It can output at high speed with low noise. That is, the internal capacitance of the image pickup device viewed from the output terminal t ₁ is only the capacitance of the output signal line 16, and the operation can be performed at higher speed. By using a transistor having a large conductance as the voltage-current conversion means 14, the amount of signal current of the output signal line 16 is increased, noise is reduced, and a signal output with good SN can be obtained. Further, by including the demodulation means 18, the signal current flowing through the output signal line 16 is demodulated as a signal voltage and output.

The light receiving element 1 can be composed of a first MOS transistor. Then, the vertical signal line 4 is grounded via the load element 12, and the first MOS transistor 1 and the load element 12 constitute a voltage generating means.
The charges of the light receiving element 1 can be converted into a voltage.

The voltage-current converting means 14 is composed of a second MOS transistor connected between the output signal line 16 and the first power source or the second power source, and its gate electrode is a voltage generating means (1, 12). ), The signal voltage from the voltage generating means (1, 12) can be converted into a signal current in the second MOS transistor 14.

The signal current amount can be increased by making the mutual conductance of the second MOS transistor 14 which is the voltage / current converting means larger than the mutual conductance of the first MOS transistor 1 which is the light receiving element. It is possible to further reduce noise. That is, the load resistance at the time of demodulating the signal current into the signal voltage by the demodulation means 18 also becomes a noise generation source, but the load resistance can be reduced and the noise can be reduced by increasing the current amount.

According to a second aspect of the invention, in the solid-state image pickup device according to the first aspect of the invention, by using the demodulating means 18 including the bipolar transistor 19, that is, by using the grounded base circuit by the bipolar transistor 19, a low input impedance is obtained. / It has the characteristics of high output impedance and is optimal as a circuit that converts current into voltage.

In a third invention, the above-mentioned first or second
In the solid-state imaging device according to the invention described above, the channel width of the second MOS transistor 14 which is the voltage-current conversion means is made larger than the channel width of the first MOS transistor 1 which is the light receiving element, so that The amount of current increases, that is, the mutual conductance increases, and noise can be further reduced.

In the fourth invention, the pixel signal voltage (pixel signal voltage including a normal signal component and an FPN (fixed pattern noise) component) in the light receiving element 1 is held in the first sample hold circuit 13A, and the pixel is reset. The subsequent pixel signal voltage, that is, the FPN component voltage is held in the second sample hold circuit 13B.

This pixel signal voltage and F after pixel reset
The PN component voltages are respectively the first and second voltage-current conversion means 1
4A and 14B convert the signals into currents, and the respective signal currents are converted into first and second demodulating means 18A (or 32A).
And 18B (or 32B).

This first demodulating means 18A (or 32A)
The pixel signal output voltage demodulated by the second demodulation means 18
By supplying the FPN component voltage demodulated by B (or 32B) to the subtraction circuit 26, the pixel output signal from which the FPN component has been removed, that is, a normal signal component can be extracted from the subtraction circuit 26.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of an amplification type solid-state image pickup device according to the present invention. In the figure, 1 is a unit pixel (cell)
, A pixel transistor, in this example, a pixel MOS transistor is shown, and a plurality of pixel MOS transistors 1 are arranged in a matrix. 2 is a vertical scanning circuit composed of a shift register or the like, 3 is a pixel M for each row
A vertical selection line connected to the gate of the OS transistor 1 is connected to the vertical scanning circuit 2 and a vertical scanning signal, that is, a vertical scanning pulse φ _V [φ _V1, ... φ _Vi, φ _{Vi + 1} , ... Sequentially given.

The source of the pixel MOS transistor 1 is connected to the vertical signal line 4, and the drain thereof is connected to the power supply V _DD . A load MOS transistor 12 is connected between each vertical signal line 4 and ground, and a bias voltage V _GB is applied to the gate of the load MOS transistor 12.

A sample hold circuit 13 for holding a signal voltage is further connected to each vertical signal line 4, and the output terminal of the sample hold circuit 13 converts the signal voltage into a signal current by a voltage-current conversion means, for example, a MOS. It is connected to the gate of the transistor, that is, the horizontal drive MOS transistor 14.

The drain of the horizontal drive MOS transistor 14 is connected to the power supply V _DD (or another power supply), and the source thereof is connected to the horizontal signal line 16 via the horizontal MOS switch 15.
Connected to. Reference numeral 7 denotes a horizontal scanning circuit composed of a shift register or the like. A horizontal scanning signal from the horizontal scanning circuit 7, that is, a horizontal scanning pulse φ _H [φ _H1, ... φ _Hn, φ
_{Hn + 1,} ...] are sequentially applied to the gates of the horizontal MOS switches.

Here, the horizontal drive MOS transistor 14
Has a channel width larger than that of the pixel MOS transistor. As a result, the mutual conductance of the horizontal drive MOS transistor 14 becomes larger than the mutual conductance of the pixel MOS transistor 1.

A horizontal scanning output circuit 17 is constituted by the load MOS transistor 12, the sample hold circuit 13, the horizontal driving MOS transistor 14, the horizontal MOS switch 15, and the horizontal scanning circuit 7.

The output terminal t ₁ of the horizontal signal line has a current-voltage conversion circuit (that is, a demodulation circuit) 1 for converting a signal current into a signal voltage.
8 are connected. The current-voltage conversion circuit 18 can be configured by a grounded base circuit using a bipolar transistor 19, as shown in FIG. 2A, for example. For example, when the horizontal drive MOS transistor 14 is an n-channel MOS transistor, a grounded base circuit using a pnp bipolar transistor is formed.

That is, the output terminal t ₁ of the horizontal signal line 16 is connected to the emitter of the pnp bipolar transistor 19, its base is grounded via the bias power supply V _B , and its collector is connected to the load resistor R and the load resistor R. The output terminal t _out is derived from the connection point of. The bias potential V _{B applied} to the base determines the operating potential of the horizontal signal line 16, and is set to a voltage lower by 1 to 2 V than the output voltage range of the pixel MOS transistor 1.

As the current-voltage conversion circuit 18, in addition to the grounded base circuit using the bipolar transistor of FIG. 2A,
A current-voltage conversion circuit can be configured using the operational amplifier 23 shown in FIG. 2B. That is, the horizontal signal line 16 is connected to the inverting input terminal of the operational amplifier 23, the bias power supply V _B is connected to the non-inverting input terminal to determine the operating potential of the horizontal signal line 16, and the inverting input terminal and the output terminal are connected. Resistance R
₀ is connected.

Of course, the current-voltage conversion circuit 18 can be composed of other circuits.

FIG. 7 is a sectional view showing the semiconductor structure of the unit pixel (that is, pixel MOS transistor) 1. In this figure, 31 is a semiconductor substrate of the first conductivity type, for example, p type, 3
Reference numeral 2 is a photoelectrically converted signal charge, which is a p-type well region for accumulating holes 33 in this example, and 34 is a second conductivity type or n-type well region. An n-type source region 35 and a drain region 36 are formed in the p-type well region 32, and, for example, a thin-film polycrystal capable of transmitting light through the gate insulating film on the p-type well region 32 between the regions 35 and 36. A gate electrode 37 made of silicon is formed. The gate electrode 37 is connected to the vertical selection line 3. Reference numeral 38 is a source electrode connected to the vertical signal line 4, and 39 is a drain electrode connected to the power supply V _DD . The holes 33 accumulated by photoelectric conversion in the p-type well region 32 immediately below the gate electrode 37 control the channel current (drain current) during the read operation, and the amount of change in the channel current becomes a signal output.

Next, the operation of the amplification type solid-state image pickup device 21 will be described.

First, the vertical scanning pulse φ _v [φ _V1, ... φ _Vi , φ from the vertical scanning circuit 2 is sequentially applied to the vertical selection line 3 of each row.
_{Vi + 1,} ...] Is applied, and the pixel MOS transistors 1 in each row are sequentially activated. That is, during the horizontal blanking period, for example, the selection pulse φ _Vi of the selection line 3 in the i-th row becomes high level, and the pixel MOS transistor 1 in the i-th row is in the operating state.

Then, the signal voltage obtained by the source follower circuit composed of the pixel MOS transistor 1 in this operating state and the load MOS transistor 12 connected to the vertical signal line 4 is the sample and hold circuit φ _SH. Held at 13. The signal voltage held in the sample hold circuit 13 is applied to the gate of the horizontal drive MOS transistor 14, and the horizontal drive MOS transistor 14 converts the signal voltage into a signal current. That is,
During the horizontal scanning period, a horizontal scanning pulse φ _H [φ _H1, ... φ _Hn, φ _{Hn + 1,} ...
The OS switches 15 are sequentially turned on, and the source currents of the horizontal drive MOS transistors 14, which are determined according to the signal voltage from the sample hold circuit 13, are respectively supplied to the horizontal MOS switch 1.
5 to the horizontal signal line 16.

The output signal current output to the horizontal signal line 16 is demodulated into a voltage by the current-voltage conversion circuit 18,
This demodulated signal voltage is output as a signal output.

According to the amplification type solid-state imaging device 21 described above, the output signal voltage from the pixel MOS transistor 1 obtained by the source follower operation of the pixel MOS transistor 1 and the load MOS transistor 12 is held in the sample hold circuit 12, Since the horizontal drive MOS transistor 15 converts the signal current into a signal current and outputs the signal current to the horizontal signal line 16, the pixel signal can be output at high speed and with low noise.

That is, by configuring the horizontal drive MOS transistor 14 so that its channel width is larger than that of the pixel MOS transistor 1, and thus its transconductance is larger than that of the pixel MOS transistor 1. The signal current of the horizontal signal line 18 increases. Therefore, the conversion gain of the current-voltage conversion circuit 18 can be reduced, that is, the load resistance that is a noise generation source can be reduced, and noise can be reduced.

Further, since the vertical signal source 4 and the horizontal signal line 16 are not connected by the horizontal drive MOS transistor 14, the internal capacitance of the image pickup device viewed from the output terminal t ₁ becomes only the capacitance of the horizontal signal line 16 and the parasitic capacitance. Becomes smaller, and as a result, pixel signals can be output at high speed.

3 to 5 show fixed pattern noise (FP
It is another embodiment of the amplification type solid-state imaging device according to the present invention, which enables removal of N).

In FIG. 3, reference numeral 1 denotes a light receiving element which constitutes a unit pixel (cell), for example, a pixel transistor, in this example, a pixel MOS transistor, and a plurality of pixel MOS transistors 1 are arranged in a matrix. 2 is a vertical scanning circuit composed of a shift register or the like, 3 is a pixel MOS for each row
A vertical selection line connected to the gate of the transistor 1 and connected to the vertical scanning circuit 2, and vertical scanning signals, that is, vertical scanning pulses φ _v [φ _V1, ... φ _Vi , φ _{Vi + 1,} ... Given.

The source of the pixel MOS transistor 1 is connected to the vertical signal line 4, and the drain thereof is connected to the power supply V _DD . A load MOS transistor 12 is connected between each vertical signal line 4 and ground, and a bias voltage V _GB is applied to the gate of the load MOS transistor 12.

A first sample hold circuit 13A for holding a signal voltage is connected to each vertical signal line 4, and an output terminal of the sample hold circuit 13A has a first voltage current for converting the signal voltage into a signal current. Conversion means, eg MOS
It is connected to the gate of the transistor, that is, the first horizontal drive MOS transistor 14A.

First horizontal drive MOS transistor 14A
Is connected to the power supply V _DD (or another power supply), and the source is connected to the first horizontal signal line 16A via the first horizontal MOS switch 15A.

Each vertical signal line 4 has a similar connection circuit configuration in parallel with the connection circuit of the first sample hold circuit 13A, the first horizontal drive MOS transistor 14A and the first horizontal MOS switch 15A. The second sample-hold circuit 13B, the second horizontal drive MOS transistor 14B, and the second horizontal MOS switch 15B that it has are connected.

That is, the second sample and hold circuit 13B for holding the signal voltage is connected to the vertical signal line 4, and the output terminal of the second sample and hold circuit 13B converts the signal voltage into the signal current. Conversion means, eg MOS
It is connected to the gate of the transistor, that is, the second horizontal drive MOS transistor 14B. The drain of the second horizontal drive MOS transistor 14B is connected to the power supply V _DD (or another power supply), and the source thereof is connected to the second horizontal signal line 16B via the second horizontal MOS switch 15B.

As will be described later, the first sample hold circuit 13A holds the pixel signal output of the pixel MOS transistor 1 (that is, the signal output including the signal component and the FPN component), and the second sample hold circuit 13B resets the pixel. The pixel signal output of only the subsequent FPN component is held.

Each first and second horizontal MOS switch 15
The gates of A and 15B are commonly connected and connected to the horizontal scanning circuit 7 including a shift register and the like.

Here, the horizontal drive MOS transistor 14
A and 14B are configured such that their channel width is larger than that of the pixel MOS transistor 1. As a result, the mutual conductance of the horizontal drive MOS transistors 14A and 14B becomes larger than the mutual conductance of the pixel MOS transistor 1.

First and second horizontal signal lines 16A and 16
The output terminals t _A1 and t _B1 of _B are connected to the horizontal signal lines 16A and 16B.
The signal currents respectively output from the
It is connected to a noise removing circuit 25 for removing the N component. The noise removal circuit 25 includes first and second current-voltage conversion circuits (that is, demodulation circuits), for example, first and second base ground circuits 18A and 18B using bipolar transistors, as shown in FIG. Subtraction circuit 26 connected to the first and second grounded base circuits 18A and 18B
And is configured.

That is, the output terminals t _A1 and t _{B1 of} the first and second horizontal signal lines 16A and 16B are connected to the respective bipolar transistors 19A and 19B constituting the first and second base ground circuits 18A and 18B. It is connected to the emitter, its base is grounded via a common bias power supply 27, and its collector is connected to a predetermined power supply V _EE via load resistors 20A and 20B, respectively. The connection points a and b between the collectors of the bipolar transistors 19A and 19B and the load resistors 20A and 20B are connected to the subtraction circuit, for example, the input terminal of the differential amplifier 26.

Similar to the above example, the bipolar transistor 1
Base ground circuits 18A and 18B using 9A and 19B
Has a characteristic of low input impedance / high output impedance, and is optimal as a circuit for converting current into voltage. Horizontal drive MOS transistors 14A and 14B are n
In the case of a channel MOS transistor, it is possible to demodulate an output signal current into a voltage with a grounded base circuit using pnp bipolar transistors 19A and 19B. The bias power supply 27 determines the operating potentials of the horizontal signal lines 16A and 16B, and is set to a voltage lower than the output voltage range of the pixel MOS transistor 1 by 1 to 2V.

Next, the amplification type solid-state image pickup device 2 of FIG.
The operation of No. 4 will be described with reference to the timing chart of FIG.

First, the vertical scanning pulse φ _v [φ _V1, ... φ _Vi , φ from the vertical scanning circuit 2 is sequentially applied to the vertical selection line 3 of each row.
_{Vi + 1,} ...] Is applied, and the pixel MOS transistors 1 in each row are sequentially activated. That is, for example, the selection pulse φ _Vi of the selection line 3 in the i-th row becomes the high level M in the read-out period T _A in the first half of the horizontal blanking period HBK, and the pixel M in the i-th row is detected.
The OS transistor 1 becomes active. The pixel signal voltage (pixel signal voltage including the normal signal component and the FPN component) obtained by the source follower circuit composed of the pixel MOS transistor 1 and the load MOS transistor 12 in this operating state is the sample hold pulse φ _SH1. And first
Of the sample and hold circuit 13A. The pixel signal voltage held in the first sample hold circuit 13A enters the gate of the first horizontal drive MOS transistor 14A.

Next, in the pixel reset period T _B in the horizontal blanking period HBK, for example, the selection pulse φ _Vi of the selection line 3 becomes the level H at most, and the reset potential is applied to the gate of the pixel MOS transistor 1 after reading. The accumulated and accumulated signal charges (holes) are removed to the substrate side, and the pixel MOS transistor 1 is reset.

Next, in the latter half period of the horizontal blanking period HBK, that is, in the read period T _C after the pixel reset, the selection pulse φ _Vi of the selection line 3 becomes the high level M again, and the pixel MOS transistor 1 becomes the operating state. The source follower operation is performed with the load MOS transistor 12, and the pixel signal voltage after pixel reset, that is, the FPN component voltage is the sample hold pulse φ _SH2 and the second sample hold circuit 1
Held in 3B. Second sample hold circuit 13B
The FPN component voltage held at is input to the gate of the second horizontal drive MOS transistor 14B.

Then, during the horizontal scanning period, the horizontal scanning pulse φ _H [φ _{H1 ,} ... φ _Hn, φ from the horizontal scanning circuit 7 is _{generated.
Hn + 1,} ...] causes the first and second horizontal MOS switches 15A and 15B to be turned on at the same time, and each signal voltage becomes the first
And second horizontal drive MOS transistors 14A, 14B
Are converted into currents, that is, each pixel signal voltage and FP
First and second horizontal drive MOs determined according to the N component voltage
The source currents of the S transistors 14A and 14B are horizontal MO.
It flows through the S switches 15A and 15B to the first and second horizontal signal lines 16A and 16B, respectively.

[0063] That is, in this embodiment, the FPN component after the pixel signals and pixel resetting of the pixel MOS transistor 1, during each horizontal blanking period HBL, in its first and second halves placed between the pixel reset period T _B The read operation is performed twice.

The pixel signal current output from the first horizontal signal line 16A and the FPN component current output from the second horizontal signal line 16B are the bases of the current-voltage conversion circuit of the noise removal circuit 25. Ground circuit 18A, 18B
To the subtraction circuit 2 and the converted demodulated pixel signal voltage V _det1 and demodulated FPN component voltage V _det2 are converted into a voltage.
6 is input. As a result, the signal output V _out from which the FPN component has been removed is output from the output terminal t _out of the subtraction circuit 26.

_Assuming that the load resistances 20A and 20B of the grounded base circuits 18A and 18B are R, the function of the amplitude of the signal voltage from the pixel MOS transistor 1 is ΔV _pxl , and the demodulated signal voltage amplitude after current-voltage conversion ΔV _det is

[0066]

[ _Formula 1] ΔV _det = R × gm × ΔV _pxl

Can be approximated by However, gm is horizontal drive M
This is the mutual conductance of the OS transistors 14A and 14B.

Finally, how the FPN component is removed is expressed by the following equation.

[0069]

V _det1 = R × gm × (V _pxl + V _fpn −V _th ) + V _OS (pixel signal: V _fpn −V _th > 0) V _det2 = R × gm × (V _fpn −V _th ) V _OS (pixel signal after reset: FPN component) V _out = V _det1 −V _det2 = R × gm × V _pxl

However, V _{det1 and} V _det2 are the grounded base outputs (demodulated signal voltage) at the connection points a and b in FIG. 4, V _pxl + V
_fpn is the output signal voltage of the pixel MOS transistor 1, V
_fpn is the output signal voltage of the pixel MOS transistor 1 after reset, and V _th is the horizontal drive MOS transistors 14A, 1
4B threshold voltage, V _OS is grounded base circuit 18
Offset voltage generated in A and 18B.

As a result, the signal output V _out from which the FPN component V _fpn generated from the pixel MOS transistor 1 is removed is obtained.

FIG. 5 shows another example of the noise removing circuit 25. In this example, the current-voltage conversion circuit is replaced with current-voltage conversion circuits (demodulation circuits) 32A, 32B using operational amplifiers 31A, 31B such as high-band differential amplifiers. That is, the first horizontal signal line 16A is connected to the inverting input terminal of the first operational amplifier 31A, the resistor 33A is connected between the inverting input terminal and the output terminal, and the inverting input terminal of the second operational amplifier 31B is also connected. To the second horizontal signal line 1
6B is connected, and a resistor 33 is provided between the inverting input terminal and the output terminal.
B is connected to the first and second operational amplifiers 31A and 31A
Horizontal signal lines 16A and 16B common to the B non-inverting input terminal
A bias power source 34 for determining the operating potential of is connected. Then, the first and second operational amplifiers 31A,
The output terminal of 31B is connected to the input terminal of the subtraction circuit 26. Of course, the current-voltage conversion circuit can be composed of other circuits.

According to the amplification type solid-state image pickup device 24 according to the embodiments of FIGS. 3 to 5, the pixel signal output voltage held by the first and second sample hold circuits 13A and 13B and the pixel after pixel reset The signal output voltage is input to the gates of the first and second horizontal drive MOS transistors 14A and 14B, converted into currents, and output to the first and second horizontal signal lines 16A and 16B as signal currents. Then, the signal currents are demodulated to signal voltages by the current-voltage conversion circuits 18A and 18B (or 32A and 32B), and the FPN component voltage after pixel reset is subtracted from the demodulated pixel signal voltage through the subtraction circuit 26. As a result, a video signal from which fixed pattern noise (FPN) has been removed can be obtained.

In this embodiment, the sample hold circuit 13
Since the pixel signal voltage is once held in [13A, 13B], the FPN component signal necessary for FPN removal can be read out, and the FPN component can be removed by adding a simple subtraction circuit 26 outside the image sensor. Becomes

Also in this solid-state image pickup device 24, as in the above-described embodiment, the channel widths of the horizontal drive MOS transistors 14A and 14B are made wider than the channel width of the pixel MOS transistor 1 so that the horizontal signal line 16A, The signal current of 16B increases, the conversion gain of the current-voltage conversion circuits 18A and 18B (or 32A and 32B) can be reduced, and noise can be reduced.

The respective capacities inside the image pickup device viewed from the output terminals t _A1 and t _B1 are only the capacities of the horizontal signal lines 16A and 16B, and the operation can be performed at higher speed. Therefore,
The pixel signal can be output at high speed and with low noise.

In the above-mentioned pixel MOS transistor 1, an example in which it is formed on a p-type substrate has been taken as an example, but the present invention is not limited to this, and a pixel structure in which the impurity n-type / p-type is inverted is also applicable. Applicable. In these cases, the same can be applied by only reversing the polarity of the applied voltage.

[0078]

According to the solid-state image pickup device of the first aspect of the present invention, pixel signals can be output at high speed and with low noise.

According to the solid-state image pickup device of the second invention,
By using the demodulation means including the bipolar transistor, it has the characteristics of low input impedance / high output impedance, and is optimal for the case of converting current into voltage.

According to the solid-state image pickup device of the third invention,
It is possible to further reduce noise.

According to the solid-state image pickup device of the fourth invention,
A pixel output signal from which fixed pattern noise (FPN) has been removed can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a solid-state imaging device according to the present invention.

2A is a circuit diagram showing an example of a current-voltage conversion circuit connected to a horizontal signal line of the solid-state imaging device of FIG. B is a circuit diagram showing another example of the current-voltage conversion circuit connected to the horizontal signal line of the solid-state imaging device of FIG. 1.

FIG. 3 is a configuration diagram showing another example of the solid-state imaging device according to the present invention.

FIG. 4 is a circuit diagram showing an example of a noise removal circuit connected to a horizontal signal line of the solid-state imaging device of FIG.

5 is a circuit diagram showing another example of a noise removal circuit connected to the horizontal signal line of the solid-state imaging device of FIG.

FIG. 6 is a timing chart provided for explaining the operation of the solid-state imaging device of FIGS. 3 and 4.

FIG. 7 is a sectional view of a semiconductor structure of a pixel MOS transistor.

FIG. 8 is a configuration diagram showing an example of a conventional solid-state imaging device.

[Description of Reference Signs] 1 pixel MOS transistor 2 vertical scanning circuit 3 vertical selection line 4 vertical signal line 7 horizontal scanning circuit 12 load MOS transistor 13, 13A, 13B sample hold circuit 14, 14A, 14B horizontal drive MOS transistor 15, 15A, 15B Horizontal MOS switch 16, 16A, 16B Horizontal signal line 18, 18A, 18B, 32A, 32B Current-voltage conversion circuit 19A, 19B Bipolar transistor 26 Subtraction circuit 31A, 31B Operational amplifier

Claims (4)

[Claims] 1. A plurality of light receiving elements, a voltage generating means for converting charges generated in the light receiving elements into a voltage, a voltage-current converting means for converting the voltage into a signal current and outputting it to an output signal line, Demodulation means for demodulating a signal current into a signal voltage is provided, and the light receiving element has a first MOS transistor connected between a first power source and a vertical signal line, and the vertical signal line is connected via a load element. Grounded, above first
The MOS transistor and the load element constitute the voltage generating means, and the voltage / current converting means is a second MOS transistor connected between the first power supply or the second power supply and the output signal line. A gate electrode of the second MOS transistor is connected to the voltage generating means, and the mutual conductance of the second MOS transistor is larger than the mutual conductance of the first MOS transistor. Imaging device. 2. The solid-state imaging device according to claim 1, wherein the demodulation means includes a bipolar transistor. 3. The solid-state imaging device according to claim 1, wherein the channel width of the second MOS transistor is larger than the channel width of the first MOS transistor. 4. A plurality of light receiving elements, a voltage generating means for converting charges generated in the light receiving elements into a voltage, first and second sample and hold circuits corresponding to the respective light receiving elements, and the first and the second. The first and second voltage currents that convert the pixel signal output voltage and the pixel signal output voltage after pixel reset, which are respectively held in the second sample and hold circuit, into currents and output to the first and second output signal lines Conversion means, first and second demodulation means for demodulating the respective signal currents from the first and second voltage-current conversion means into signal voltages, and pixel signals demodulated by the first demodulation means A solid-state imaging device comprising: a subtraction circuit that subtracts the pixel signal output voltage after pixel reset demodulated by the second demodulation means from the output voltage.