JP2799712B2 - DA converter - Google Patents

Description

The present invention relates to a DA for converting a signal taking a discrete value into a continuous signal.
It relates to converters, and also to technology that is effective when applied to convert multi-bit digital signals into analog signals at high speed in semiconductor integrated circuits.
The present invention relates to a technology that is effective when used in a color signal processing device such as I (large-scale semiconductor integrated circuit device).

[Related Art] For example, in a DA converter used in a color signal processing device such as a color palette LSI, it is a major issue to reduce noise of a DA-converted analog signal and to increase the conversion speed.

Noise included in the DA-converted analog signal includes quantization noise determined by the number of bits of the DA-converted digital signal, and noise other than the quantization noise. Quantization noise is noise caused by a digital signal having a discrete value, and can be reduced as the number of bits of the digital signal increases.
However, noise other than quantization noise cannot be reduced even if the number of bits of the digital signal is increased, but rather tends to increase. In addition, there is a tendency for the conversion speed to increase as the conversion speed increases.

Here, the present inventors can operate at high speed with low noise.
The DA conversion technology was discussed. The following is not a known technique, but is a technique studied by the present inventors, and the outline thereof is as follows.

FIG. 8 shows an outline of a DA converter studied by the present inventors.

The D / A converter shown in the figure is a current addition type D / A converter, and includes a reference current source 1 and a plurality of (2 ^{n -1} ) constant current circuits 2-0.
~ 2 (n-1) constant current circuit rows 2, a plurality of (2 ^n-1
), A load switching resistor RL, a plurality of (2 ^{n -1} ) latch circuits 4-0 to 4- (n-1). ) have such a latch circuit array 4 composed of a plurality of constant current circuit 2 _-0 ~2 _- (n ^-1) from the current 2 ⁰ flows are weighted, respectively, I _0, 2 ¹ · I _0, ‥‥, 2
^By switching ⁿ⁻¹ · I ₀ to one of the load resistance RL side and the ground potential side in accordance with each bit data of the input digital signal DIN (D0 to Dn−1), the load resistance RL An analog signal Aout converted into a voltage is obtained from both ends. Thus, a plurality of (2n-1) -bit input digital signals Din (D0 to Dn-1) are converted into analog signals Aout and output (for example, see "Nikkei Electronics" published by Nikkei McGraw-Hill).
January 13, 1986, no. 386, pp. 209-217).

Constant current circuit 2-0~2- (n-1), respectively, the predetermined element size: p-channel type MOS transistor Mp (Mp × 2 ⁰ with (W / L channel width / channel length), Mp × 2 ¹ ,
M, Mp × 2 ^2n-2 , Mp × 2 ^n-1 ). Each constant current circuit 2-0~2- (n-1) is by the current mirror operation performed through the p-channel type MOS transistor Mp _0, the reference current I ₀ of the reference current source 1 and MOS transistor Mp A constant current of a magnitude determined by the size (W / L) flows. Thereby, each of the constant current circuits 2-0 to 0
2- (n-1), respectively, p-channel MOS transistor ^{(Mp × 2 0, Mp ×} 2 1, ‥‥, Mp × 2 2n-2, Mp × 2 n-1) size (W / L) depending on the constant current 2 ⁰ are weighted to the twofold, I _0, 2 ¹ · I _0, ‥‥, so that the flow of 2 ^n-1 · I ₀ from the power supply Vcc.

Each of the current switching circuits 3-0 to 3- (n-1) is constituted by a pair of n-channel MOS transistors MpA and MpB which are turned on / off complementarily to each other, and comprises a plurality of constant currents 2-0 to 2 - current 2 ⁰ flowing to (n-1) respectively ^{_{from, I 0, 2 1 · I}} 0, ‥‥, an output side 2 ^n-1 · I ₀ load resistance
The current is switched to either RL or the non-output side ground potential.

The latch circuits 4-0 to 4- (n-1) operate in synchronization with a clock CK externally provided as a timing signal, and change the input digital signal Din (D0 to Dn-1) into a positive phase and a negative phase (Q ,). The digital signals Din (D0 to Dn-1) distributed to the normal phase and the negative phase are applied to the MOS transistors M of the current switching circuits 3-0 to 3- (n-1).
nA and MnB are complementarily driven on / off.

[Problems to be Solved by the Invention] However, the present inventors have clarified that the above-described technology has the following problems.

That is, as shown in FIG. 9, there is a problem that large noise different from quantization noise may be generated in the output of the analog signal Aout which is a converted output.

 The problem described above occurs as follows.

That is, in the DA converter shown in FIG. 8, the digital signal Din (D0 to Dn-1) as the conversion input
The current is divided into a positive phase and a negative phase by -0 to 4- (n-1) and input to the current switching circuits 3-0 to 3- (n-1) as a switching control circuit. 4- (n-
Since the transmission time on the positive-phase output Q side and the transmission time on the negative-phase output side in 1) are not always the same, noise is likely to occur when the current switching circuit is switched. The noise at the time of this switching is particularly noticeable when a particularly large current 2 · In ^-1 is switched.

For example, the digital signal Din is 4 bits (n = 4), and the binary value of the digital signal Din is changed from “0111” to “1”.
When the digital signal value changes to “000”, the digital signal value changes only by the minimum value [1], but when the bit value of the most significant digit (the fourth bit) changes from 0 to 1, the digital signal value changes to the most significant digit. corresponding most switching of large currents 2 ³ · I ₀ flows from the constant current circuit 2-3 is performed. This large current 2 ³ · I ₀
As shown in FIG. 9, the analog signal
Aout generates large noise.

FIG. 10 shows a circuit configuration of latch circuits 4-0 to 4- (n-1) used in the DA converter shown in FIG.

In the figure, (a) shows the latch circuit 4-x by symbol symbols, where D is a data input CK is a clock input, and Q, is an output of the latch circuit.

(B) shows a circuit configuration of the latch circuit 4-x by a logic gate. The latch circuit 4-x is a flip-flop type holding circuit assembled by a NAND gate 4A.

(C) shows the circuit configuration of the latch circuit 4-x in further detail. The latch circuit 4-x is composed of a normal inverter B and an inverter 4C with a gate terminal.

The latch circuit 4-x shown in FIG. 10 holds the input data D in synchronization with the clock CK, and distributes the held data to both positive-phase and reverse-phase outputs Q, and outputs the same. At this time, in the circuit shown in FIG. 10 (c), the number of intervening inverters 4B and 4C and the data D are output to the opposite phase output until the data D is transmitted to the positive phase output Q. The number of inverters 4B and 4C intervening before transmission is different from each other. Therefore, the transmission time until the data D appears on the output in synchronization with the clock CK is shifted between the positive-phase output Q and the negative-phase output. This difference in transmission time inside the latch circuit does not cause much problem when the operation of the DA converter is relatively slow.However, in a DA converter that performs a high-speed conversion operation such as a conversion cycle of 10 MHz or more, The influence of the transmission time shift becomes large as noise, for example, as shown in FIG.

An object of the present invention is to provide a technology that enables a high speed and low noise of a DA converter.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

In other words, a digital signal composed of a plurality of bits is distributed to a positive phase and a negative phase, respectively, and the current is switched to either the output side or the non-output side by the digital signal distributed to the positive phase and the negative phase, thereby performing DA conversion. When performing the operation, a circuit means is provided to make the timings of the digital signals distributed to the normal phase and the negative phase uniform.

[Operation] According to the above-described means, since the switching timings of the currents are uniform, noise due to the shift of the switching timing is less likely to occur.

As a result, the object of enabling high speed and low noise of the DA converter is achieved.

EXAMPLES Hereinafter, preferred examples of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals denote the same or corresponding parts.

FIG. 1 shows a schematic configuration of a DA converter to which the technology according to the present invention is applied.

The D / A converter shown in FIG. 1 is a current addition type D / A converter for converting a multi-bit (4-bit) digital signal into an analog signal, and includes a reference current source 1 and a plurality (five) of constant current circuits 2.
A constant current circuit row 2 comprising −0 to 2-4, a current switching circuit row 3 comprising a plurality (five) of current switching circuits 3-0 to 3-4, a load resistor RL, and a plurality (five) of latch circuits 4-0-4
-4 and an input digital signal
The decoding circuit 5 decodes only the upper two bits (D2, D3) of Din (D0, D1, D2, D3).

In the DA converter shown in the figure, first, currents I ₀ , 2I ₀ , and 5 respectively flowing from five constant current circuits 2-0 to 2-4 provided one more than the number of bits of the digital signal Din are provided. Four
I ₀ , 4I ₀ , 4I ₀ are converted to a 4-bit input digital signal Din (D0 to D
By switching one of the load resistance RL side and the ground potential side to flow according to the data value of 3), the voltage is converted from both ends of the load resistance RL and an analog output Aout is obtained. This allows multiple bits (4 bits)
Input digital signal Din (D0-D3) is analog signal Aout
Has been converted to.

Here, the reference current source 11 includes a bipolar transistor Tr1 to which an emitter resistor Re of a predetermined size is connected, and an operational amplifier 1A that supplies a predetermined reference voltage Vref to the base of the bipolar transistor Tr1. The reference current I ₀ arbitrarily set variably by the voltage Vref and the emitter resistance Re is applied to the current mirror image input side p
Flow through the channel MOS transistor Mp _0.

Each of the constant current circuits 2-0 to 2-4 has a p-channel MOS transistor Mp (Mp × 1, Mp × 2, Mp × 4, Mp) having a predetermined element size (W / L: channel width / channel length). ×
4, Mp × 4), the reference current of the reference current source 1
I ₀ is mapped by the current mirror operation performed through the p-channel MOS transistor Mp ₀ , so that the constant currents I ₀ , 2I ₀ , and 4I having magnitudes corresponding to the respective sizes (W / L).
₀ , 4I ₀ and 4I ₀ are supplied from the power supply Vcc.

Each of the current switching circuits 3-0 to 3-4 is constituted by a pair of n-channel MOS transistors MpA and MpB which are turned on / off complementarily to each other, and comprises a plurality of constant current circuits 2-0 to 2-4. Currents I ₀ , 2I ₀ , 4
I ₀ , 4I ₀ , and 4I ₀ are switched to one of the load resistance RL on the output side and the ground potential on the non-output side.

The latch circuits 4-0 to 4-4 operate in synchronization with a clock CK externally supplied as a timing signal, and output lower 2-bit data (D0 to D3) of the input digital signal Din (D0 to d3).
0, D1) and the upper 2 bits of the input digital signal Din (D0 to D3)
Signal Dco obtained by decoding bit data (D2, D3)
ut (Dc1, Dc2, Dc3), a total of five logical signals (D0, D1, D2, D
3) is divided into positive phase and negative phase (Q,) and output. The signals Din (D0, D1) distributed to the normal phase and the negative phase
And Dcout (Dc1, Dc2, Dc3) are connected to the current switching circuits 3-0 to 3-0.
The 3-4 MOS transistors MnA and MnB are complementarily turned on and off.

The decoding circuit 5 receives the input digital signal Din (D0, D1, D2,
Only the upper two bits (D2, D3) in D3) are partially decoded. Dcin is its decode input, and Dcout is its decode output, and the truth value relationship between them is as shown in Table 1 below.

In the above Table 1, the output currents ( _{0 to} 12I ₀ ) are 3, 4, 5,
From the second constant current circuit 2-2, 2-3, 2-4 to the current switching circuit 3
This is a current flowing through the load resistance RL through −2, 3-3, and 3-4. This output current ( _{0 to} 12I ₀ ) corresponds to the input digital signal Di.
It corresponds to the value of the upper 2-bit data (D2, D3) in n (D0, D1, D2, D3). On the other hand, the lower two-bit data (D0, D2) in the input digital signal Din (D0, D1, D2, D3)
1) directly controls the switching of the first and second current switching circuits 3-0 and 3-1 without being decoded. Thus, the output current corresponding to the lower 2-bit data (D0, D1) is as shown in Table 2 below.

As described above, the output current shown in Table 1 (0~12I ₀₎ to the output current shown in Table 2 (3~3I ₀₎ was added currents (0-1
5I ₀ ) flows through the load resistor RL. The current ( _{0 to} 15I ₀ ) flowing through the load resistor RL is converted into a current ( _{0 to} 15RL · I ₀ ) proportional to the magnitude thereof, and the converted voltage is extracted as an analog signal Aout.

Here, when the input digital signal Din (D0 to D3) is 4 bits, the DA converter shown in FIG. 8 is configured to directly control the switching of the current switching circuit by the 4-bit input digital signal. and for which the fourth magnitude of the current flowing through the constant current circuit, the reference current 8 times the size of I ₀ (8I
₀ ) was needed.

On the other hand, in the DA converter shown in FIG. 1, as described above, the input digital signal Din is divided into lower-order bit signals and upper-order bit signals, and the lower-order bit signals do not pass through the decoding circuit 5. , While the higher-order bit signal is weighted with the current through the decoding circuit 5, the largest constant current value that the constant current circuit per one flows is the reference current. It can be made up to four times the size of I ₀ (4I ₀ ).
As a result, the magnitude of the current switched by the current switching circuit can be reduced to four times or less of the reference current I ₀ , and the occurrence of noise accompanying the switching of the large current can be reduced.

FIG. 2 shows the configuration of the latch circuits 4-0 to 4-4 used in the DA converter shown in FIG.

In the figure, (a) shows the latch circuit 4-x by symbol symbols, where D is a data input, CK is a clock input, and Q, is an output of the latch circuit.

(B) shows the circuit configuration of the latch circuit 4-x broken down into blocks.
It is composed of a master-slave type flip-flop by the gate control type latch circuits 4D. G,
Indicates a gate control input.

(C) shows the circuit configuration of the latch circuit 4-x in more detail, and shows three gate-controlled latch circuits 4D.
Are each constituted by a normal inverter B and an inverter 4C with a control terminal.

The latch circuit 4-x shown in FIG. 2 holds the input data D in synchronization with the clock CK, and distributes and holds the held data to both positive-phase and reverse-phase outputs Q. At this time, the latch circuit 4-x shown in the figure has an inverter for inverting and outputting the positive-phase output to the master latch at the preceding stage, and the negative-phase output terminal of the master latch and the positive-phase output. Slave latches having the same number of gates are connected to the terminals, and operate in synchronization with the clock CK. Therefore, the number of inverters 4B and 4C intervening before data D is transmitted to the positive-phase output Q And inverters 4B and 4B intervening until data D is transmitted to the output on the opposite phase side.
Operate so that the number of C is the same as each other. For this reason,
The transmission time until the data D appears on the output in synchronization with the clock CK is the same between the positive-phase output Q and the negative-phase output. As a result, the switching timings of the current switching circuits 3-0 to 3-4, which are complementarily driven on / off by the positive-phase output Q and the negative-phase output of the latch circuit 4-x, become uniform, and Switching between the current-weighted side and the non-weighted side flowing from the constant current circuits 2-0 to 2-4 can be smoothly performed without large noise.

As described above, in the latch circuits 4-0 to 4-4,
Includes a circuit function to make the input timing of Din constant, which causes a delay in digital signal transmission time even in DA converters that perform conversion operations at ultra-high speeds, for example, when the conversion cycle is 100 MHz or more. Noise can be suppressed.

FIG. 3 shows a specific circuit example of the inverters 4B and 4C constituting the above-described latch circuits 4-0 to 4-4.

In the figure, (a) shows a circuit example of a normal inverter circuit 4B, which is composed of CMOS transistors (complementary MOS transistors) Mp1 and Mn1. IN is input, OUT
Is the output.

(B) shows a circuit example of the inverter 4C with a control terminal, which is composed of two sets of CMOS transistors Mp1, Mp2, Mn1, and Mn2. G, are control terminals complementary to each other, and output OU is determined by the input logic level of the control terminal G.
An active state in which the inverted logic of the input IN is output to T, an open state in which the output OUT is disconnected from both the H (high logic level) side and the L (low logic level) side, and the output is fixed to the L side or the H side. Inactive state.

FIG. 4 shows constant current circuits 2-0 to 2-4 and current switching circuits 3-0 to 3--3 used in the DA converter shown in FIG.
The configuration example of No. 4 is shown by the element layout.

In the figure, 6G is a gate electrode, 6S is a source region, 6D
Indicates a drain region. In the layout example shown in the figure, a parallel parasitic capacitance Cpo is generated between the drain region 6D of the p-channel MOS transistor Mp forming the constant current circuit 2-x and the power supply potential Vcc. Further, a parasitic capacitance Cno occurs in parallel between the drain region 6D of the n-channel MOS transistors MnA and MnB forming the current switching circuit 3-x and the ground potential.

FIG. 5 shows the constant current circuits 2-0 to 2-4 and the current switching circuits 3-0 to 3--3 used in the DA converter shown in FIG.
4 is shown by a device layout.

In the layout example shown in FIG.
Parasitic capacitances Cpo and Cno parallel to p, MnA, and MnB drain regions 6D
Had occurred.

On the other hand, in the layout example shown in FIG. 5, the source region 6S is divided into two, and a common drain region 6D is arranged between the two divided source regions 6S. in this case,
Although the channel width W is also divided by half, it is equivalent to two MOS transistors having the divided channel widths connected in parallel. Therefore, the characteristics determined by the so-called W / L are shown in FIG. It is almost equivalent to the one shown.

With such a layout configuration, the constant current circuit 2-x
In the MOS transistor Mp on the side, the capacitance regulated in parallel between the drain region 6D and the power supply potential Vcc is reduced to about half (Cpo / 2) as compared with the case of FIG. In addition, in each of the MOS transistors MnA and MnB on the current switching circuit 3-x side, the parasitic capacitance in parallel between the drain region 6D and the ground potential is about two-thirds as compared with the case of FIG. 3x
Cno / 2). As a result, in the embodiment shown in FIG. 5, the operation can be further speeded up by reducing the transmission delay time constant caused by the parallel parasitic capacitance.

FIG. 6 shows a MOS forming the constant current circuits 2-0 to 2-4.
An example of the structure of a transistor is shown by an element cross section.

In the figure, the p-conductivity-imparting impurity which is ion-implanted to form the source / drain regions 6S, 6D of the MOS transistors Mp, Mp 'is implanted from a finite distance. It cannot be perfectly perpendicular to the plane. For this reason, as shown in FIG. 6, in a cross-sectional structure in which two MOS transistors Mp, Mp 'are formed by distributing and arranging two drain regions 6D, 6D' on both sides of a common source region 6S, The MOS transistor Mp formed on the side of the drain region 6D and the MOS transistor M formed on the side of the other drain region 6D '
Characteristic variations occur between p ′. As a result, it is difficult to equalize the constant currents I ₀ and I ₀ ′ respectively taken out from one drain region 6D and the other drain region 6D ′.

In FIG. 7, MOs forming the constant current circuits 2-0 to 2-4 are shown.
A preferred configuration example of the S transistor is shown by an element cross section.

In the example shown in the figure, each MOS transistor Mp, Mp ',.
Are formed so as to have independent source and drain regions 6S and 6D, respectively. In this case, even if the implantation direction of the p-conductivity-imparting impurity for forming the source / drain regions 6S and 6D is not necessarily perpendicular to the semiconductor substrate surface, the MOS transistor Mp formed together is formed. , Mp ', the variation in the ion implantation state appears similarly. Thus, for example, in the case of two MOS transistors Mp, Mp 'designed to have the same element size, the current I ₀ flowing through one of the Mp and the constant current I ₀ ' flowing through the other Mp ' Can be made the same. Thus, by eliminating the variation in the characteristics, it becomes easier to improve the accuracy of the DA converter.

Although the invention made by the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various changes can be made without departing from the gist of the invention. Absent.

For example, a part or the whole of the constant current circuit or the current switching circuit may be configured as a bipolar transistor. Further, when the latch circuit 4-x and the like are configured by a bipolar / CMOS composite type logic circuit, it is possible to significantly increase the speed as compared with the case where the latch circuit 4-x is configured using only MOS transistors.

In the above description, the case where the invention made by the present inventor is mainly applied to a parallel input type DA converter which is an application field as a background has been described, but the invention is not limited thereto. It can also be applied to DA converters.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, there is an effect that both low noise and high speed of the DA converter can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an outline of a DA converter to which the technology according to the present invention is applied, and FIGS. 2 (a), (b) and (c) are latches used in the DA converter shown in FIG. FIGS. 3 (a) and 3 (b) show an example of a specific circuit configuration of an inverter constituting the latch circuit. FIG. 3 shows a constant current circuit and a current switching circuit. Constituting MOS
FIG. 5 is a diagram showing an example of a layout configuration of a transistor. FIG.
FIG. 6 is a view showing an example of a desirable layout configuration of a transistor. FIG. 6 is a cross-sectional view showing an example of an element structure of a MOS transistor constituting a constant current circuit. FIG. 7 is an example of a desirable element structure of a MOS transistor constituting a constant current circuit. FIG. 8 is a circuit diagram showing an outline of a DA converter studied prior to the present invention; FIG. 9 is a graph showing an example of conversion characteristics of the DA converter shown in FIG. FIGS. 10 (a), (b) and (c) are diagrams showing the circuit configuration of the latch circuit used in the DA converter shown in FIG. Reference current source, 2-0 to 2-4 Constant current circuit, 3
-0 to 3-4,3-x ... current switching circuit, 4-0 to 4-4,4
-X: latch circuit, 5: decode circuit, RL: load resistance, Din: digital signal, Aout: analog signal.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-256228 (JP, A) JP-A-62-155622 (JP, A) JP-A-60-75121 (JP, A) JP-A-62 117410 (JP, A) JP-A-58-142622 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03M 1/00-1/88 H03K 3/02

Claims (2)

(57) [Claims] 1. A reference current source for supplying a predetermined reference current, a plurality of constant current circuits for supplying constant currents each having a predetermined magnitude relational weight according to the reference current of the reference current source; A multi-bit digital signal is input, and in response to a common clock signal, a positive-phase digital output signal in phase with the input digital signal and a negative-phase digital output signal in phase opposite to the input digital signal. A plurality of master-slave type latch circuits that output from a positive-phase digital output terminal and a negative-phase digital output terminal; and a constant current from the plurality of constant current circuits is supplied to a current input terminal. Is switched by the positive-phase digital output signal and the negative-phase digital output signal, so that the constant current supplied to the current input terminal is output to either the output side or the non-output side. On the other hand and a plurality of current switching circuit comprising a pair of current switch to be supplied to, 10 MHz
A DA converter that converts an input digital signal into an analog signal in a conversion cycle of z or more, wherein the plurality of latch circuits have a pair of slave latches respectively receiving a positive-phase output and a negative-phase output on the master side. The number of stages of the logic circuit interposed between the input terminal to which the digital signal is input and the positive-phase digital output terminal, and the logic circuit interposed between the input terminal and the negative-phase digital output terminal The number of stages is made substantially equal, so that the current switching timing of the pair of current switches of the plurality of current switching circuits is made substantially equal, and the noise due to the deviation of the current switching timing is reduced. . 2. A plurality of high-order bits of an input digital signal of a plurality of bits are decoded by a decoding circuit, and a decoding output of the decoding circuit is connected to a constant current circuit flowing a heavy weighted constant current among the plurality of constant current circuits. A plurality of lower bits of the input digital signal of the plurality of bits are supplied to a latch circuit connected to a constant current circuit that passes a lighter weighted constant current among the plurality of constant currents without passing through the decode circuit. The DA converter according to claim 1, wherein the DA converter is configured to be input.