JP2798188B2 - Semiconductor device test equipment - Google Patents

Semiconductor device test equipment

Info

Publication number
JP2798188B2
JP2798188B2 JP3009654A JP965491A JP2798188B2 JP 2798188 B2 JP2798188 B2 JP 2798188B2 JP 3009654 A JP3009654 A JP 3009654A JP 965491 A JP965491 A JP 965491A JP 2798188 B2 JP2798188 B2 JP 2798188B2
Authority
JP
Japan
Prior art keywords
semiconductor element
circuit board
semiconductor device
electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3009654A
Other languages
Japanese (ja)
Other versions
JPH04254346A (en
Inventor
美信 國友
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP3009654A priority Critical patent/JP2798188B2/en
Publication of JPH04254346A publication Critical patent/JPH04254346A/en
Application granted granted Critical
Publication of JP2798188B2 publication Critical patent/JP2798188B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は突起電極を有する半導体
素子を実装用基板にフリップチップ実装する前に半導体
素子を試験するための半導体素子の試験装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test apparatus for testing a semiconductor device having a bump electrode before flip-chip mounting the semiconductor device on a mounting substrate.

【0002】[0002]

【従来の技術】一般に半導体素子は初期不良を見いだす
ために高温で電圧印加試験を行っている。この半導体装
置は半導体素子を収納容器にパッケージしたものであ
る。しかしながら、近年高密度実装のために行われてい
るフリップチップ法に代表される半導体素子の直接実装
では上記の高温での電圧印加試験が行われないか、また
は半田等の接合材料で半導体素子の電極と試験装置を接
続して試験を行っていた。そのため試験後に試験装置か
ら半導体素子を取り出す際に再加熱しなければならず、
突起電極を形成する金属の半田への溶出、または突起電
極への半田の残留現象が発生し、実装後の信頼性を低下
させていた。この問題を解決するために半田による接続
ではなく、半導体素子を回路基板へ圧着する方法が検討
されている。
2. Description of the Related Art In general, a semiconductor element is subjected to a voltage application test at a high temperature in order to find an initial failure. In this semiconductor device, a semiconductor element is packaged in a storage container. However, in the direct mounting of a semiconductor element typified by a flip chip method which has been performed for high-density mounting in recent years, the above-described voltage application test at a high temperature is not performed, or the semiconductor element is bonded with a bonding material such as solder. The test was performed by connecting the electrodes and a test device. Therefore, when removing the semiconductor device from the test equipment after the test, it must be reheated,
Elution of the metal that forms the protruding electrode into the solder, or the phenomenon of the solder remaining on the protruding electrode occurs, reducing the reliability after mounting. In order to solve this problem, a method of crimping a semiconductor element onto a circuit board instead of connecting with solder has been studied.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記の従
来の構成では、半導体素子の試験装置に用いられている
回路基板はガラス繊維入りエポキシ等の樹脂材料または
アルミナ等の絶縁基体であり、半導体素子を構成するシ
リコンの熱膨張係数と比較して大きな熱膨張係数を有し
ている。そのためこれら絶縁基体からなる回路基板を半
導体素子の試験装置に使用し、半導体素子を圧着方法に
て搭載した場合、搭載時と試験時の加熱による温度差に
よる半導体素子および回路基板の相対的位置ずれに起因
する半導体素子と回路基板の電気的接続不良や突起電極
の変形が発生するという課題を有していた。
However, in the above-mentioned conventional configuration, the circuit board used in the semiconductor device test apparatus is a resin material such as epoxy containing glass fiber or an insulating base such as alumina. It has a large coefficient of thermal expansion as compared to the coefficient of thermal expansion of the constituent silicon. Therefore, when a circuit board made of these insulating bases is used in a semiconductor device test apparatus and the semiconductor device is mounted by a crimping method, the relative displacement of the semiconductor device and the circuit board due to a temperature difference due to heating during mounting and testing. Therefore, there is a problem that electrical connection failure between the semiconductor element and the circuit board and deformation of the protruding electrode occur due to the above.

【0004】本発明は上記従来の課題を解決するもの
で、半導体素子の上に設けられた突起電極に変形や損傷
を起こすことなく半導体素子の初期不良を見いだすこと
のできる半導体素子の試験装置を提供することを目的と
する。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. An object of the present invention is to provide a semiconductor device test apparatus capable of finding an initial defect of a semiconductor device without causing deformation or damage to a protruding electrode provided on the semiconductor device. The purpose is to provide.

【0005】[0005]

【課題を解決するための手段】この目的を達成するため
に本発明の半導体素子の試験装置は、突起電極を有する
半導体素子と電気的接続を行うための電極端子が形成さ
れた回路基板と、回路基板の上に設置された半導体素子
をその上方から押圧する圧着手段とを有し、回路基板が
ムライト質焼結体または窒化アルミニウム焼結体等の低
熱膨張セラミック基板であり、かつ電極端子には半導体
素子の突起電極を収納するための凹部を設けた構成を有
している。
In order to achieve the above object, a semiconductor device test apparatus according to the present invention comprises a circuit board having an electrode terminal for electrically connecting a semiconductor element having a protruding electrode; Pressure bonding means for pressing the semiconductor element mounted on the circuit board from above, the circuit board is a low thermal expansion ceramic substrate such as a mullite sintered body or an aluminum nitride sintered body, and the electrode terminals Has a configuration in which a concave portion for accommodating a projecting electrode of a semiconductor element is provided.

【0006】[0006]

【作用】この構成によって、温度変化による試験用の回
路基板と半導体素子の相対的位置ずれの発生に起因する
電気的接続不良や半導体素子の上に設けられた突起電極
の変形や損傷を起こすことなく半導体素子の初期不良を
見いだすことができる。
With this configuration, electrical connection failure due to the relative displacement between the test circuit board and the semiconductor element due to temperature change, and deformation or damage of the protruding electrode provided on the semiconductor element are caused. And the initial failure of the semiconductor element can be found without any problem.

【0007】[0007]

【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。
An embodiment of the present invention will be described below with reference to the drawings.

【0008】図1は本発明の一実施例における半導体素
子の試験装置の断面正面図である。図1において、1は
低熱膨張係数のセラミック焼結体からなる絶縁基体、2
は半導体素子、3は高融点金属からなる導体層、4は半
導体素子2の突起電極、5は基板電極の凹部、6は金め
っきを施した電極端子、7は圧着手段である。絶縁基体
1の主面には半導体素子2の突起電極4に対応した位置
に突起電極4の高さより10μm〜30μm浅い深さ
で、突起電極4より大きい内径を有する凹部5が設けら
れている。また凹部5の底面には突起電極4との良好な
電気的接続を得るために2μm以上の厚さの金めっき層
が施され、電極端子6を構成している。この電極端子6
は導体層3を通じて絶縁基体1の端部に電気的に引き出
されている。
FIG. 1 is a sectional front view of a semiconductor device test apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an insulating base made of a ceramic sintered body having a low coefficient of thermal expansion;
Is a semiconductor element, 3 is a conductor layer made of a high melting point metal, 4 is a protruding electrode of the semiconductor element 2, 5 is a concave portion of a substrate electrode, 6 is a gold-plated electrode terminal, and 7 is a crimping means. On the main surface of the insulating base 1, a recess 5 having a depth smaller than the height of the projecting electrode 4 by 10 μm to 30 μm and having an inner diameter larger than that of the projecting electrode 4 is provided at a position corresponding to the projecting electrode 4 of the semiconductor element 2. In addition, a gold plating layer having a thickness of 2 μm or more is applied to the bottom surface of the concave portion 5 in order to obtain good electrical connection with the protruding electrode 4, thereby forming an electrode terminal 6. This electrode terminal 6
Are electrically drawn to the end of the insulating base 1 through the conductor layer 3.

【0009】絶縁基体1は、ムライト(Al23・2S
i02)粉末に焼結助剤(Si02,Mg0,Ca0)を
添加し、さらにポリマーを添加混合してシート状に形成
した上に高融点金属粉末からなる導電性ペーストをスク
リーン印刷し、加圧積層後に約1500〜1700℃の
還元雰囲気中で焼成することにより形成される。基板電
極の凹部5はシート成形時にプレス金型で最上層のシー
トに孔を打ち抜いておくことにより形成される。
The insulating substrate 1 is made of mullite (Al 2 O 3 .2S).
i0 2) powder was added sintering aid (Si0 2, Mg0, Ca0) , a conductive paste made of a refractory metal powder by screen printing on the formed into a sheet by mixing further adding a polymer, pressurized It is formed by firing in a reducing atmosphere at about 1500 to 1700 ° C. after the pressure lamination. The concave portion 5 of the substrate electrode is formed by punching a hole in the uppermost layer sheet with a press die during sheet molding.

【0010】以上のような半導体素子の試験装置を用い
て、1MbitのDRAMを高温電圧印加試験を行った例に
ついて説明する。DRAMはそのチップサイズが4.3
8mm×11.63mmで厚さが0.4mmで、電極数は20
のものである。この電極の上にAuワイヤ(直径30μ
m)を用いたボールボンディング法により突起電極4を
形成する。このような半導体素子2を絶縁基体1に設置
する。この時、突起電極4を絶縁基体1の凹部5に一致
させ、圧着手段7としてクリップを使用して半導体素子
2を圧着する。半導体素子2の突起電極4は絶縁基体1
の外辺に設けられたタブを介して外部電源に接続され
る。このようにして、半導体素子2は2.5Vの電圧が
印加された状態で125℃に保持された電気オーブン中
に48時間放置される。その後、クリップをはずして半
導体素子2を絶縁基体1より取り外し、電気的特性を測
定した後不良の半導体素子2を除去する。良品の半導体
素子2は実装基板へ半田付けなどにより実装される。半
導体素子2を実装した実装基板について電気的検査を行
い、さらに高温での電圧印加試験を行う。
An example in which a 1 Mbit DRAM is subjected to a high-temperature voltage application test using the above-described semiconductor device test apparatus will be described. DRAM has a chip size of 4.3
8mm x 11.63mm, 0.4mm thick, 20 electrodes
belongs to. An Au wire (30 μm in diameter) is placed on this electrode.
The bump electrode 4 is formed by the ball bonding method using the method m). Such a semiconductor element 2 is placed on the insulating base 1. At this time, the semiconductor element 2 is crimped by using a clip as the crimping means 7 with the protruding electrode 4 aligned with the concave portion 5 of the insulating base 1. The protruding electrode 4 of the semiconductor element 2 is
Is connected to an external power supply via a tab provided on the outer side of. Thus, the semiconductor element 2 is left for 48 hours in an electric oven maintained at 125 ° C. while a voltage of 2.5 V is applied. After that, the clip is detached, the semiconductor element 2 is removed from the insulating base 1, the electrical characteristics are measured, and the defective semiconductor element 2 is removed. A good semiconductor element 2 is mounted on a mounting board by soldering or the like. An electrical test is performed on the mounting board on which the semiconductor element 2 is mounted, and a voltage application test is performed at a high temperature.

【0011】(表1)に半導体素子の試験装置に用いた
基板の種類と半導体素子の接合法に対して、半導体素子
の段階での試験結果(表1では1次と記す)、実装基板
への半田付け後の不良内容、実装基板としての試験結果
(表1では2次と記す)を示した。
Table 1 shows the test results at the stage of the semiconductor device (shown as primary in Table 1) for the type of substrate used in the semiconductor device test apparatus and the bonding method of the semiconductor device. Of the semiconductor device after soldering, and the test results as a mounting board (in Table 1, denoted as secondary).

【0012】[0012]

【表1】 [Table 1]

【0013】[0013]

【表2】 [Table 2]

【0014】(表1)に示す絶縁基体1としてはムライ
ト焼結体,窒化アルミニウム焼結体および比較としてア
ルミナ焼結体、ガラス繊維入りエポキシ基板を用い、半
導体素子2の状態での試験時の接続方法としてはクリッ
プによる圧着と半田による接続を用いた。(表1)およ
び(表2)に示すように、アルミナ焼結体またはガラス
繊維入りエポキシの基板に圧着法により半導体素子2を
搭載して高温電圧印加試験(1次)を行った場合、試験
後の半導体素子2の不良の発生率は低いが、実装基板へ
の実装後または実装基板での高温電圧印加試験(2次)
の実施後の半導体素子2の不良率は極めて高い。このこ
とは1次の高温電圧印加試験中に半導体素子2に電圧が
十分に印加されなかったこと、すなわち突起電極4と電
極端子6との接続が十分でなかったことを示している。
As an insulating substrate 1 shown in Table 1, a mullite sintered body, an aluminum nitride sintered body, an alumina sintered body as a comparison, and an epoxy substrate containing glass fiber were used. As a connection method, crimping by a clip and connection by soldering were used. As shown in (Table 1) and (Table 2), when the semiconductor element 2 was mounted on an alumina sintered body or an epoxy substrate containing glass fiber by a crimping method and a high-temperature voltage application test (primary) was performed, the test was performed. Although the rate of occurrence of defects in the semiconductor element 2 is low, a high-temperature voltage application test after or after mounting on the mounting board (secondary)
The defect rate of the semiconductor element 2 after the implementation is extremely high. This indicates that the voltage was not sufficiently applied to the semiconductor element 2 during the primary high-temperature voltage application test, that is, the connection between the protruding electrode 4 and the electrode terminal 6 was not sufficient.

【0015】[0015]

【発明の効果】以上のように本発明は、突起電極を有す
る半導体素子と電気的接続を行うための電極端子が形成
された回路基板と、回路基板の上に設置された半導体素
子をその上方から押圧する圧着手段とを有し、回路基板
がムライト質焼結体または窒化アルミニウム焼結体等の
低熱膨張セラミック基板であり、かつ電極端子には半導
体素子の突起電極を収納するための凹部を設けた構成と
することにより、半導体素子の上に設けられた突起電極
に変形や損傷を起こすことなく半導体素子の初期不良を
見いだすことのできる優れた半導体素子の試験装置を実
現できるものである。
As described above, according to the present invention, a circuit board on which an electrode terminal for making electrical connection with a semiconductor element having a protruding electrode is formed, and a semiconductor element mounted on the circuit board is placed above the circuit board. A circuit board is a low thermal expansion ceramic substrate such as a mullite sintered body or an aluminum nitride sintered body, and the electrode terminal has a recess for accommodating a projecting electrode of a semiconductor element. With such a configuration, it is possible to realize an excellent semiconductor device test apparatus capable of finding an initial failure of the semiconductor device without causing deformation or damage to the protruding electrode provided on the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における半導体素子の試験装
置の断面正面図
FIG. 1 is a sectional front view of a semiconductor device test apparatus according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁基体(回路基板) 2 半導体素子 4 突起電極 5 凹部 6 電極端子 7 圧着手段 DESCRIPTION OF SYMBOLS 1 Insulating base (circuit board) 2 Semiconductor element 4 Projection electrode 5 Depression 6 Electrode terminal 7 Crimping means

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 突起電極を有する半導体素子と電気的接
続を行うための電極端子が形成された回路基板と、前記
回路基板の上に設置された半導体素子をその上方から押
して前記半導体素子の突起電極と前記回路基板の電極
端子とを接続するクリップによる圧着手段とを有し、前
記回路基板がムライト質焼結体よりなる低熱膨張セラミ
ック基板であり、かつ前記電極端子には前記半導体素子
の突起電極を収納するための凹部を設けた半導体素子の
試験装置。
1. A circuit board on which an electrode terminal for making an electrical connection with a semiconductor element having a protruding electrode is formed, and a semiconductor element mounted on the circuit board is pressed from above to form the semiconductor element. Protruding electrodes and electrodes of the circuit board
A crimping means using a clip for connecting a terminal , the circuit board is a low thermal expansion ceramic substrate made of a mullite sintered body, and the electrode terminal has a recess for accommodating a projecting electrode of the semiconductor element. Tester for semiconductor devices provided with.
【請求項2】 回路基板が窒化アルミニウム焼結体より2. The circuit board is made of an aluminum nitride sintered body.
なる低熱膨張セラミック基板であることを特徴とする請A low thermal expansion ceramic substrate
求項1に記載の半導体素子の試験装置。The test device for a semiconductor device according to claim 1.
JP3009654A 1991-01-30 1991-01-30 Semiconductor device test equipment Expired - Fee Related JP2798188B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3009654A JP2798188B2 (en) 1991-01-30 1991-01-30 Semiconductor device test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3009654A JP2798188B2 (en) 1991-01-30 1991-01-30 Semiconductor device test equipment

Publications (2)

Publication Number Publication Date
JPH04254346A JPH04254346A (en) 1992-09-09
JP2798188B2 true JP2798188B2 (en) 1998-09-17

Family

ID=11726206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3009654A Expired - Fee Related JP2798188B2 (en) 1991-01-30 1991-01-30 Semiconductor device test equipment

Country Status (1)

Country Link
JP (1) JP2798188B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975079A (en) * 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing

Also Published As

Publication number Publication date
JPH04254346A (en) 1992-09-09

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