JP2792333B2 - Bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and, more particularly, to a technique for miniaturizing an ultra-high speed and highly integrated bipolar integrated circuit.

[0002]

2. Description of the Related Art In a conventional bipolar transistor, a contact portion is formed on a collector extraction portion of an emitter region and a collector region having a high impurity concentration due to low resistance, and electrodes are provided on each of the contact portions. .

FIG. 3 is a sectional view of a conventional bipolar transistor. An N ^-- type epitaxial silicon layer 1 is formed on a P-type silicon substrate (not shown) via an N ⁺ -type buried collector layer 4, and a field silicon oxide film 5 is selectively formed on the surface thereof. . The N ⁻ -type epitaxial silicon layer 1 becomes an active collector region, in which a P-type base region 6 is formed, in which an N ⁺ -type emitter region 7 is formed, while an N ⁻ -type remote from the base and emitter regions. High impurity concentration N ⁺ diffused N-type impurity into the portion of the epitaxial silicon layer 1 to reduce the resistance.
The collector extraction portion 2 of the mold is formed to reach the N ⁺ -type buried collector layer 4. An N-type polycrystalline silicon film 12 is in contact with the surface of collector take-out portion 2 and its end extends over field silicon oxide film 5. Also,
A P-type polycrystalline silicon film 16 extends on field silicon oxide film 5 in contact with base region 6. Further, on the periphery of the emitter region 7, a sidewall 11 made of a silicon oxide film is formed on the side wall of the P-type polycrystalline silicon film 16 and the side wall of the interlayer insulating film 8, through which an N-type polycrystalline silicon film 17 is formed. The end of the region 7 is in contact with the surface and extends over the interlayer insulating film 8. A thick insulating film 9 is formed on the entire surface, and a collector contact hole 22 is formed in a portion of the insulating films 9 and 8 immediately above the collector take-out portion 2, and an aluminum collector electrode 52 is formed on the collector of the N-type polycrystalline silicon film 12. A base contact hole 26 is formed on the field silicon oxide film 5 at the portions of the insulating films 9 and 8 on which the aluminum base electrode 56 is formed to connect to the base of the P-type polycrystalline silicon film 16. An emitter contact hole 27 is formed in a portion of the insulating film 9 formed directly above the emitter region 7 and connected to the contact portion B.
Is formed, and an aluminum emitter electrode 57 is formed so as to be connected to the emitter contact portion E of the N-type polycrystalline silicon film 17.

Here, consider the case where the electrode wiring of the semiconductor device has a wiring pitch rule of 4 μm. All wiring is 4μm
Are formed on a grid delimited by, and at the same time, the transistors are also arranged to be on the grid. That is, each electrode pitch between the emitter electrode 57 and the collector electrode 52 and between the emitter electrode 57 and the base electrode 56 is also formed at 4 μm. FIG. 3 shows the electrode arrangement of the transistor under such a design rule. Here, the emitter contact portion E and the collector contact portion C
(The distance between the centers of both) P ₃ is 4 μm,
The shortest distance between the low resistance high impurity concentration N ⁺ type collector extraction portion 2 and the emitter region 7 (the shortest distance between the peripheral ends thereof) is about 3 μm.

[0005]

One of the major factors that determine the yield of the bipolar transistor is the distance between the collector extraction portion and the emitter region formed by diffusing phosphorus at a high concentration in order to reduce the collector resistance. There is.

In the present specification, the distance between the collector take-out portion and the emitter region is the shortest distance between the peripheral ends of the collector take-out portion and the peripheral end of the collector take-out portion. (Ie, no horizontal diffusion is considered). Referring to FIG. 3 and FIG. 1, which will be described later, the position of the peripheral end of a portion of the N ⁻ type epitaxial silicon layer 1 which is diffused by phosphorus to form the collector extraction portion 2 and which is partitioned by the field silicon oxide film 5 And The periphery of the emitter region is a PN junction with the base region.

That is, the yield sharply drops when the distance between the collector extraction portion and the emitter region falls below 2 μm, and the electrode pitch will be reduced in accordance with the miniaturization and high integration of transistor electrode wiring in the future. It has become a big problem when going. In particular, in a region where the electrode pitch is less than 3 μm, the distance between the collector extraction portion and the emitter region corresponds to about 2 μm, and it is difficult to achieve the above-mentioned electrode pitch of 3 μm or less due to a reduction in yield.

On the other hand, in order to minimize this reduction in yield, the phosphorus concentration in the low-resistance collector extraction portion is set to 10 ¹⁹ c
A method of ^{reducing the value} to m ⁻³ or less is also conceivable. However, in this method, the collector resistance becomes high, and it is difficult to obtain a high-performance bipolar transistor.

[0009]

A feature of the present invention is that a collector region of one conductivity type formed on a semiconductor substrate, a base region of an opposite conductivity type formed in the collector region, and a collector region formed in the base region. An emitter region of one conductivity type formed;
A collector extraction portion having a high impurity concentration formed by diffusing an impurity of one conductivity type in a part of the collector region, and a collector contact hole formed in an insulating layer on the semiconductor substrate; In a bipolar transistor having a collector electrode formed thereon, the collector contact hole is located closer to the emitter region than immediately above the collector extraction portion, is connected to a surface of the collector extraction portion, and extends below the insulating layer in the emitter direction. In a bipolar transistor, a collector contact portion is formed below the collector contact hole by a conductor film and the collector electrode is connected to the collector contact portion.

Here, the one conductivity type collector region in which the base region is formed is an N ⁻ type epitaxial layer, and the collector take-out portion is formed by adding an N type impurity, preferably phosphorus, to the N ⁻ type epitaxial layer. It may be an N ⁺ type diffusion layer formed by diffusion. The conductor film is made of N
It is preferably a polycrystalline silicon film or a metal silicide film.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG.
FIG. 2 is a sectional view showing a semiconductor chip according to one embodiment of the present invention, and FIG. 2 is a plan view schematically showing the semiconductor chip.

An N ^-- type epitaxial silicon layer 1 is formed on a surface of a P-type silicon substrate (not shown) via an N ⁺ -type buried collector layer 4, and a field silicon oxide film is selectively formed on the surface. 5 are formed to partition the transistor formation region. The N ⁻ type epitaxial silicon layer 1 serves as an active collector region, in which a P type base region 6 is formed, in which an N ⁺ type emitter region 7 is formed.
Are formed.

On the other hand, phosphorus, which is an N-type impurity, is diffused into a portion of the N ⁻ -type epitaxial silicon layer 1 away from the base and emitter regions via the portion 5 ′ of the field silicon oxide film 5 to reduce the resistance to a high impurity. An N ⁺ -type collector extraction portion 2 having a concentration reaches the N ⁺ -type buried collector layer 4.

A phosphorus-containing N-type polycrystalline silicon film or metal silicide film 32 having a quadrangular planar shape (indicated by a dotted line in FIG. 2) is in contact with the surface of collector take-out portion 2 and its end is formed of field silicon. A portion 5 ′ of oxide film 5 extends in the direction of emitter region 7 and collector contact portion C is located there.

A boron-containing P-type polycrystalline silicon film or metal silicide film 16 having a quadrangular planar shape (indicated by a dotted line in FIG. 2) is in contact with base region 6 to cover field silicon oxide film 5. The base contact portion B extends toward the outside of the transistor formation region and is located there.

A sidewall 11 made of a silicon oxide film is formed on the side wall of the P-type polycrystalline silicon film 16 and the interlayer insulating film 8 on the periphery of the emitter region 7, and the planar shape is a quadrangle (see FIG. 1). 2 (indicated by a dotted line), an N-type polycrystalline silicon film or metal silicide film 17 containing phosphorus is in contact with the surface of the emitter region 7 and its end extends over the interlayer insulating film 8. The emitter contact portion E is located at

Then, a thick insulating film 9 is formed on the entire surface,
Insulating films 9 and 8 in portion 5 'of field silicon oxide film 5
A collector contact hole 42 having a square planar shape is formed at the portion indicated by.
It is formed so as to be connected to the collector contact portion C of the polycrystalline silicon film 32 of the mold.

A base contact hole 26 having a square planar shape is formed in the insulating films 9 and 8 on the field silicon oxide film 5, and an aluminum base electrode 5 is formed there.
6 is formed so as to be connected to the base contact portion B of the P-type polycrystalline silicon film 16, and an emitter contact hole 27 having a square planar shape is formed in a portion of the insulating film 9 immediately above the emitter region 7. The emitter electrode 57 is formed of an N-type polycrystalline silicon film 17 having an emitter contact portion E.
Is formed by being connected to.

In FIG. 2, the center of each of the contact portions C, E, and B, that is, each of the collector contact holes 42, 27, and 26 is indicated by +, between the collector electrode 62 and the emitter electrode 57 and between the collector electrode 62 and the emitter electrode 57. electrode pitch between the base electrode 56 is P _1, a wiring pitch rule 2 [mu] m in this embodiment, the electrode pitch P ₁ is 2 [mu] m. Therefore, it becomes an electrode wiring of a miniaturized and highly integrated transistor.

On the other hand, the shortest distance (the shortest distance between the both peripheral ends) between the low-resistance, high-impurity-concentration N ⁺ -type collector extraction portion 2 and the emitter region 7 is referred to the data shown in FIG. Thus, the transistor yield is increased so as to have a desired value. In this embodiment, the thickness is 3 μm.

[0021]

As described above, the present invention relates to miniaturization of electrode wiring of a high performance bipolar transistor.
The shortest distance between the N ⁺ -type collector extraction portion 2 and the emitter region 7 of the collector region where phosphorus is diffused at a high concentration in order to reduce the resistance (the shortest distance between both peripheral ends) is set to the N ⁺ -type collector extraction. In order to prevent the yield from lowering due to the dislocation generated from the portion 2, the yield is secured so as not to lower, and the collector contact is provided by drawing out to the emitter region using a polycrystalline silicon film or a metal silicide film. Therefore, it is possible to reduce the electrode pitch without lowering the yield, and there is an effect that the pitch of 3 μm in the prior art can be reduced to 2 μm or less.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a bipolar transistor according to one embodiment of the present invention.

FIG. 2 is a plan view schematically showing a plane of the bipolar transistor of FIG. 1;

FIG. 3 is a sectional view showing a conventional bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N ^- type epitaxial silicon layer 2 N ⁺ type collector extraction part 4 N ⁺ type buried collector layer 5 Field silicon oxide film 5 'Field silicon oxide film 5 part 6 Base region 7 Emitter region 8 Interlayer insulating film 9 Insulation Film 11 Side wall 12, 17 N-type polycrystalline silicon film 16 P-type polycrystalline silicon film 22, 42 Collector contact hole 26 Base contact hole 27 Emitter contact hole 52, 62 Collector electrode 56 Base electrode 57 Emitter electrode 32 N-type polycrystalline silicon film or metal silicide film C collector contact portion B base contact portion E emitter contact unit P _1, P ₃ electrode pitch of

Claims (4)

(57) [Claims] A first conductivity type collector region formed in a semiconductor substrate; a reverse conductivity type base region formed in the collector region; and a one conductivity type emitter region formed in the base region. A high impurity concentration collector extraction portion formed by diffusing an impurity of one conductivity type in a part of the collector region, wherein the collector region is formed in a collector contact hole formed in an insulating layer on the semiconductor substrate. The collector contact hole is located closer to the emitter region than directly above the collector extraction portion, is connected to the surface of the collector extraction portion, and extends below the insulating layer in the emitter direction. A collector contact portion below the collector contact hole is formed by the conductive film to be formed, and the collector A bipolar transistor to which a data electrode is connected. 2. The one conductivity type collector region in which the base region is formed is an N ⁻ type epitaxial layer,
2. The bipolar transistor according to claim 1, wherein the collector extraction portion is an N ⁺ -type diffusion layer formed by diffusing an N-type impurity into the N ⁻ -type epitaxial layer. 3. The bipolar transistor according to claim 1, wherein the conductive film is an N-type polycrystalline silicon film. 4. The bipolar transistor according to claim 1, wherein the conductor film is a metal silicide film.