JP2792222B2 - Successive approximation type A / D converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a successive approximation type A / D converter.

[Conventional technology]

For a head that reads / writes data from a hard disk or a floppy disk, it is usually necessary to perform servo control of the head position in order to follow tracks on the disk. This servo control detects the current head position by sampling a servo pattern recorded in advance between the data area on the track in synchronization with the end of the data area, and detects the difference from the target track. Judge and perform servo control.

FIG. 7 is a schematic diagram illustrating an example of the servo control. Data tracks 81 to 84, 9 on which data is recorded
1 to 94 are concentrically written on the disk in advance. The servo patterns 85 to 88 are recorded at a predetermined interval from the data area. The head position is determined by the read signal 8 from the head at the timings T1, T2, T3, T4 in the figure.
5 to 88 can be obtained by A / D conversion. For example, if the head is located at the position 90 in FIG. 7 and moves on the broken line, the servo pattern is not recorded at the timings T ₁ , T ₂ , and T ₄ , and the A / D conversion result is 0 V and T 3 Since the servo pattern is recorded at the timing, the conversion result is 5V. This indicates that the head is located on the tracks 83 and 93. Also,
Even if the head is located between tracks,
The position can be determined by checking the A / D conversion result.

[Problems to be solved by the invention]

This servo area is in the range of several 100 μS, and the width of the servo pattern read signals 85 to 88 is about 100 μS. However, the servo area tends to be shorter in order to improve the recording density. Therefore, even if there is no problem in the feedback control of the actual conversion result with time delay, the analog voltage changes in a short time, so that a very high-speed A / D converter (for example, a flash A / D converter) Converter), and it was not possible to use an inexpensive successive approximation type A / D converter.

This flash-type A / D converter is susceptible to transformation by the normal first timing, for example, in the case of 8-bit resolution, and requires 2 ⁸ comparators, generally very becomes large expensive chip size, single-chip It is difficult to build in a microcomputer or the like. Therefore, a dedicated high-speed A / D converter is arranged outside the microcomputer, and its output is received and controlled by an input port or the like. For this reason, the substrate area, the wiring cost on the substrate are increased, the reliability is reduced, and unnecessary ports are consumed, and the cost performance of the applied system is reduced. Further, when a plurality of analog inputs are converted at the same timing, it is necessary to arrange a plurality of A / D converters in parallel and perform a fluctuating operation in parallel, which further increases the cost.

It is an object of the present invention to provide an A / D converter capable of solving such a problem and inexpensively and quickly converting an analog voltage to be converted in a short time.

[Means for solving the problem]

According to the configuration of the present invention, the input analog voltage is sequentially sampled by a plurality of n sample-and-hold circuits that sample and hold at a predetermined sampling period, and sequentially converts the upper bits sequentially, and then sequentially converts the upper bits. Pipeline operation by transferring the contents of the comparison register to the successive approximation register for lower bit conversion and performing successive conversion of the lower bits while the next input signal is performing successive conversion of the upper bits Successive approximation type
In the A / D converter, a timing control means for respectively generating a sampling timing signal for designating a sampling timing of each of the sample and hold circuits and synchronizing with the sampling timing signal to output each control timing; N for each sampling period according to the synchronous output of the control means.
Reference voltage generating means for sequentially generating a plurality of successive comparison reference voltages having different resolutions in accordance with the control timings; i-th sampling cycle of the successive comparison reference voltage (i is an integer smaller than n); A plurality of n comparing means for respectively comparing the i-th analog voltage held by the sample-and-hold circuit, each comparison result being input, held as a plurality of n bits, and output as the control output; Multiple meters with different widths
(M is an integer smaller than n) stages of successive approximation registers; and transfer means for transferring data between the successive approximation registers. The conversion result is stored in all bits of the m-th successive approximation register. When this is done, this is (m + 1)
Of the (m + 1) -th successive approximation register and using the m-th successive approximation register.
It is characterized in that the hold output is converted.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a successive approximation type A / D converter having 4-bit resolution according to the present invention. This A / D converter has analog input terminals 10 to 13,
Converters 20 to 23 with built-in sample and hold circuits and comparators for sampling and holding analog inputs from analog input terminals 10 to 13;
A reference voltage generator 15 for sequentially supplying reference voltages 50 to 53 to comparators in 20 to 23; selectors 31 and 32 for selecting one of four output signals of converters 20 to 23;
A register (hereinafter referred to as SAR) 17 which controls the reference voltage by data stored in the register as a 2-bit register to which the output of 1 is input. A 4-bit register (hereinafter referred to as SA) that controls the reference voltage by the data stored in the register that inputs the output to the lower 2 bits.
R) 18, a timing control unit 16 for controlling the timing of the entire A / D converter, and a conversion result register (hereinafter referred to as ADCR) 25a to 25d for storing the 4-bit output of the SAR 18.
And a bus 26 for transmitting the outputs of the ADCRs 25a to 25d.

FIG. 2 is a detailed view of the converter 20 shown in FIG. 1, and includes a switch S ₁ for sampling the analog input 10 with a sampling signal 40, a capacitor C ₁ for holding the sampled voltage, and a reference voltage generator 15. the reference voltage 50 and hold compared to the comparison result and the analog voltage which is composed of Kopareta a ₁ for outputting a logical output. Since the other converters 21 to 23 have the same configuration, the description is omitted here.

The timing control unit 16 includes sampling signals 40 to 43 based on the internal operation clock and a selection signal 5 for selecting which converter to apply the voltage generated in the reference voltage generation unit 15 to.
4.Selection signals 57 and 58 for selecting which of the outputs of the converters 20 to 23 are to be input to the SAR, and control signals 59 and 6 for specifying in which bits the input data of the SARs 17 and 18 are stored.
It outputs 0, a conversion end signal 61, and an interrupt request 63.

FIG. 3 is a block diagram showing the inside of the reference voltage generator 15. Reference numeral 70 denotes an output selector, SARs 17 and 18 each having 2-bit and 4-bit register outputs 55 and 56, first bit and O-th bit data 71 and 72 of register output 55, and register output 56.
Are the data 73 to 76 of the third bit, the second bit, the first bit, and the Oth bit. 77 and 78 are reference voltages. In the selector 70, the reference voltages 77 and 78 selectively output according to the levels of the selection signals 71 to 76 are changed to the reference voltages 50 to 5 by the selection signal 54.
Connect to any of 3 and output. That is, the reference voltage generator 15 divides the reference input voltage 14 applied to the reference input into 16 parts by an R string composed of a resistor R and a transfer gate, and n / 16 (n =
0-15) can be output. For the reference voltages 50 to 53, two kinds of reference voltages can be simultaneously output from one R string by the register data 55 and 56 of the SARs 17 and 18, and the reference voltage 77 is 1/4 of the reference input voltage 14, The 1/2, 3/4, and reference voltage 78 can output a voltage of 0/16 to 15/16 of the reference input voltage 14.

For example, when the selection signals 71 to 76 are "101011", the reference voltage 77 generates 1/4 of the reference voltage 14, and the reference voltage 78 generates 1/8 of the reference voltage 14. The selector 70 is a switch circuit as shown in FIG. 4, and the selection signal 54 causes the reference voltage 50 to 53 to be equal to the reference voltage 77 or the reference voltage 77.
Selectively outputs 78 levels. Here, the reference voltages 50 to 53 are reference voltages for the converters 20 to 23.

Hereinafter, the operation of the present embodiment will be described. here,
It is assumed that the analog voltage applied to the analog input terminals 10 to 13 is converted in a state where the analog voltage is not sampled and held in all the converters 20 to 23. Analog voltage sampling signal 40 to 43, holds the voltage on capacitor C ₁ by closing the switch S ₁ when the logical value 1. Reference voltage generating unit to one terminal of a comparator A ₁
A reference voltage 50 to 53 input from 15 is applied, and a sampled and held analog voltage is applied to the other input. When the analog voltage is higher than the reference voltage, the comparator A ₁ outputs a logical value 1 Is output.

The output of the comparator A ₁ is inputted to the selector 31 or the selector 32, and stores the SAR17 or SAR18 store the converted results in 1-bit units. In selectors 31 and 32, converters 20 to 23
Which of the converters is used as the input of SAR17 and SAR18 is selected and output by selector signals 57 and 58.

The operation when the analog input is continuously converted will be described with reference to the timing chart of FIG.

The sampling signals 40 to 43 generate timing for sampling the analog input, and are output here by the timing control unit 16. When the sampling signals 40 to 43 have a logical value of 1, the converters 20 to 23 sample the analog values of the analog inputs 10 to 13.

First, an operation for an analog voltage applied to the analog input terminal 10 will be described. In the figure, the conversion operation of the data stored in the converter 20 at the timing T50 is started using the SAR 17, and the voltage of 1/2 of the reference input 14 input from the reference input terminal is used as the initial value as the reference voltage 50.
Is applied. In the figure, performs a comparison operation between the analog voltage sampled by the comparator A ₁ in the reference voltage 50 and the sampling signal 40 for a period of time T50～T501, the comparison result is transferred to the bit 1 of SAR17 via the selector 31 You. Next, at timings T50 to T501, the converter 20 determines the SAR determined at the previous timings T50 to T501.
If bit 1 is a logical value 0 according to the data of bit 1 of 17, the reference voltage generator 15 generates 1/4 of the reference input 14,
If the logical value is 1, compare operation is performed at 3/4 voltage and the result is SAR
Transfer to bit 0 of 17

When the data is transferred to bits 1 and 0 of SAR 17, at timing T51, SAR 17 synchronizes the data of bits 1 and 0 with bits 3 and 2 of SAR 18, respectively, in synchronization with timing control signal 60 indicating that the 2-bit conversion has been completed. At the same time as transferring to 2, the SAR 17 is set with an initial value for the conversion operation for the analog voltage applied to the analog input terminal 11.

Next, according to the data of bits 3 and 2 of the SAR 18, the reference voltage generator 15 outputs 1/8 or 3/8 or 5/8 of the reference input 14.
Alternatively, a voltage of 7/8 is generated as a reference voltage 50, and a voltage of 1/2 of the reference input is generated as a reference voltage 51.
The comparison operation is performed at 0 and 21, and the result is transferred to bit 1 of SAR18 and bit 1 of SAR17, respectively. That is, at timings T51 to T52, the conversion operation is performed on the analog input 10 and the analog input 11 in parallel. By repeating this operation for bit 0, the conversion result of 4-bit resolution is
In the SAR 17, data of 2-bit resolution can be stored. When the 4-bit data is stored in the SAR 18, the timing controller 16 outputs a conversion end signal 61 indicating that the conversion operation has been completed, and outputs the 4-bit data of the SAR 18 to the ADCR2.
At the same time as transferring to 5a, the data of SAR17 is transferred to SAR18 and the above operation is repeated.

In the above operation, the order conversion operation is performed in the same manner for the analog values of the analog input terminals 12 and 13, and the data is stored in the ADCRs 25a to 25d, respectively. Therefore, the timing
At T51 to T52, timings T52 to T53, and timings T53 to T54, conversion of the analog values of the analog input 10 and the analog input 11, the analog input 11 and the analog input 12, and the analog input 12 and the analog input 13 are performed in parallel.

With the above operation, the analog values 10 to 13 are sequentially converted, and when the data is stored in the ADCRs 25a to 25d, the timing control unit 16 outputs the interrupt request 63 and the A / D
Stop the conversion operation.

In this embodiment, since two SARs, SAR17 and SAR18, are provided and a circuit for simultaneously generating a two-level reference voltage is provided, two analog values can be simultaneously converted. Can be implemented, and the conversion time can be reduced to about 1/2 compared with the ordinary successive approximation method.

In addition, the A / D converter of the present invention is configured such that, when the input cycle of the sampling signal is longer than the conversion time, the A / D converter stops conversion and enters a standby state when the input signal is longer than the conversion time, and the input cycle is short. In this case, the sampled and held analog voltage is continuously converted, and when the conversion is completed for all inputs, the conversion operation is stopped.

FIG. 6 is a block diagram of a second embodiment of the present invention.
In this embodiment, analog voltages from the same input terminal 80 are sampled in time series in place of the input terminals 10 to 13 of the first embodiment. I do. In this case, the number of input terminals can be reduced, which is effective when a small package or the like is employed.

In this embodiment, the number of sample and hold circuits is four, and
Although the number of SARs is set to two, the number can be further increased, the number of analog input terminals and the number of parallel conversions executed can be increased, and the conversion can be performed at higher speed. The interrupt request is generated when the conversion of all inputs is completed, but may be performed for each conversion. In this embodiment, the sampling timing signal is generated by the timing control unit. However, the sampling timing signal can be input from the outside, and the A / D conversion operation can be performed by sampling and converting at an arbitrary timing or repeatedly outputting the sampling signal. Can be easily continued without terminating.

〔The invention's effect〕

As described above, according to the present invention, the conversion time can be significantly reduced as compared with the ordinary successive approximation method, and an analog input for converting in a short time or a plurality of analog inputs at the same timing can be inexpensively and quickly operated. There is an effect that A / D conversion can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of the converter 20 of FIG. 1, FIG. 3 is a detailed circuit diagram of the reference voltage generator 15 of FIG. FIG. 4 shows the selector section 70 of FIG.
5 is a timing chart for explaining the operation of the embodiment of FIG. 1, FIG. 6 is a block diagram of a second embodiment of the present invention, and FIG. 7 is a diagram for explaining a conventional example. It is a schematic diagram. 10 to 13,80 ... analog input terminal, 14 ... reference input, 15 ... reference voltage generator, 16 ... timing control unit, 17, 18 ... control register, 20 to 23 ... converter, 25 ...
... Conversion result register, 26 ... bus, 31, 32, 70 ... selector, 40-43 ... sampling signal, 50-53, 77, 78 ... reference voltage, 54, 57, 58, 71-76 ... Selection signal, 55, 56 ... Register output, 59, 60 ... control signal, 61 ... conversion end signal, 6
3 ...... interrupt request signal, 81～84,91～94 ...... data tracks 85 to 88 ...... Sabopatan read signal, 90 ...... head position, A ₁ ...... comparator, C ₁ ...... capacitor, S ₁ ... …switch.

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/00-1/88

Claims (3)

(57) [Claims] An input analog voltage is sequentially sampled by a plurality of n sample-and-hold circuits for sampling and holding at a predetermined sampling period, successively converting upper bits sequentially, and then successively comparing the upper bits. The pipeline operation is performed by transferring the contents of the register to the successive approximation register for lower bit conversion and performing successive conversion of the lower bits while the next input signal is performing successive conversion of the upper bits. In the successive approximation type A / D converter to be performed, a timing control means for generating a sampling timing signal for designating the sampling timing of each of the sample and hold circuits and synchronizing with the sampling timing signal to output each control timing. And according to the synchronous output of this timing control means A reference voltage generating means for sequentially generating sequential comparison reference voltage different in a plurality of resolution according to n control timing of each sampling period, the i-th of the sampling period of said sequential comparison reference voltage (i is n
A plurality of n comparing means for respectively comparing the i-th analog voltage held by the sample-and-hold circuit with the analog voltage held by the sample-and-hold circuit, and inputting and holding each comparison result of these comparing means as a plurality of n bits A plurality of m (m is an integer smaller than n) stages of successive approximation registers which are output as the control outputs and have different bit widths; and transfer means for transferring data between the successive approximation registers; When the conversion result is stored in all the bits of the successive approximation register, the result of the conversion is transferred to the (m + 1) th successive approximation register, and the (m + 1) th sample and A successive approximation type A /, characterized in that the hold output is converted.
D conversion device. 2. The successive approximation type A / D converter according to claim 1, wherein n input analog voltages are inputted to each sample and hold circuit. 3. The successive approximation A / D converter according to claim 1, wherein one input analog voltage is input in common and input in a time division manner by each sample-and-hold circuit.