JP2784357B2 - Overcurrent protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overcurrent protection circuit for protecting a load circuit from overcurrent.

[0002]

2. Description of the Related Art Fuses, breakers, and the like are used as devices connected in series to a load to protect the load from overcurrent.

[0003]

The fuse must be replaced each time it blows when an overcurrent flows. The breaker cannot be used for a circuit that requires a high speed due to a low breaking speed. The present invention can be easily connected in series to the load where necessary, such as a fuse or breaker, and does not need to be replaced every time an overcurrent flows. Also,
N-type / P-type depletion type M that can be used as a delay type
It is an object to provide an overcurrent protection circuit using an OS field effect semiconductor.

[0004]

According to the present invention, a source of an N-type depletion type MOS semiconductor (hereinafter abbreviated as N-type DMOS) and a P-type depletion type MOS semiconductor (hereinafter referred to as a P-type depletion type MOS semiconductor) are provided.
N-type DMOS)
Is connected to the drain of a P-type DMOS through a resistor or the like, and the gate of the P-type DMOS is connected to the N-type DM
This is an overcurrent protection circuit connected to the drain of the OS, where the drain of the N-type DMOS is plus and the drain of the P-type DMOS is minus.

[0005]

The overcurrent protection circuit configured as described above,
When an overcurrent flows through the drain of the N-type DMOS plus and the drain of the P-type DMOS negative , the potential difference in the P-type DMOS becomes the gate voltage of the N-type DMOS,
Since the potential difference in the MOS becomes the gate voltage of the P-type DMOS, an overcurrent flows and the N-type DMOS and the P-type DMO
When the potential difference at S increases, the P-type DM
When the gate voltages of the OS and N-type DMOSs increase and the gate voltages of the P-type and N-type DMOSs increase, the potential difference between the P-type and N-type DMOSs also increases. Cut off.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the overcurrent protection circuit according to the present invention will be described with reference to FIG. N-type DMOS1 source and P-type DMOS
2, the gate of the N-type DMOS 1 is connected to the drain of the P-type DMOS 3, the source of the P-type DMOS 3 is connected to the drain of the P-type DMOS 4,
4 is connected to the source of the N-type DMOS 5, and the N-type
The drain of the MOS 5 is connected to the drain of the P-type DMOS 2 through the resistor 6. The gate of P-type DMOS2 is N-type D
The source of the N-type DMOS 10 is connected to the drain of the N-type DMOS 9.
Is connected to the source of the P-type DMOS 8 and the P-type
The drain of the OS 8 is connected to the drain of the N-type DMOS 1 through the resistor 7. The gate of P-type DMOS3 is N-type DM
Connected to the drain of OS1, the gate of P-type DMOS4 is connected to the drain of P-type DMOS2, and the gate of N-type DMOS5 is connected to the drain of P-type DMOS3 (gate of N-type DMOS1). The gate of the N-type DMOS 10 is a P-type D
The gate of the N-type DMOS 9 is connected to the drain of the N-type DMOS 1 and the P-type DMOS 8
Is the drain of N-type DMOS 10 (P-type DMOS 2
Gate). This is an overcurrent protection circuit in which the drain of the N-type DMOS 1 is a positive terminal A to the outside and the drain of the P-type DMOS 2 is a negative terminal B to the outside.

With this connection, the terminal A is positive and the terminal B
Is applied with a negative voltage V _AB , the potential difference in the P-type DMOS 2 becomes the gate voltage of the N-type DMOS 1
The potential difference in the type DMOS1 becomes the gate voltage of the P-type DMOS2. For this reason, when the voltage V _AB gradually increases, the current I flowing through the N-type DMOS 1 and the P-type DMOS 2
_AB gradually increases, however, when the potential difference in the N-type DMOS 1 increases, the gate voltage of the P-type DMOS 2 increases. Similarly, when the potential difference in the P-type DMOS 2 increases, the gate voltage of the N-type DMOS 1 increases. When the voltage V _AB increases, the potential difference between the N-type DMOS1 and the P-type DMOS2 increases, and until the gate voltage of the N-type DMOS1 and the P-type DMOS2 becomes a certain level. Current I _AB
Increases, the voltage V _AB further increases, the potential difference between the N-type DMOS 1 and the P-type DMOS 2 further increases, and when the gate voltage of the N-type DMOS 1 and the P-type DMOS 2 becomes a certain level, the N-type DMOS 1 And P
Type DMOS2 moderates from current I _AB increases. When the voltage V _AB becomes larger, the N-type DMOS1
And the P-type DMOS2 gate voltage becomes larger,
The type DMOS1 and the P-type DMOS2 reduce the current I _AB , and thereafter, the N-type DMOS1 and the P-type DMOS2 reach a pinch-off state and cut off the current I _AB . As described above, the current I _AB flows to a certain extent, but if a large overcurrent flows to a certain extent or more, the potential difference between each of the N-type DMOS 1 and the P-type DMOS 2 increases, whereby the N-type DMOS 1 and the P-type DMOS 2 Of each of the gates increases. When the gate voltage increases, the potential difference also increases, and
The N-type DMOS1 and the P-type DMOS2 act on each other repeatedly to increase the gate voltage, and the current I _AB
Shuts off and works for overcurrent protection. FIG. 3 shows the static characteristics of the interruption of the overcurrent protection circuit.

Next, the operation of the P-type DMOSs 3 and 4 and the N-type DMOS 5 connected to the gate of the N-type DMOS 1 will be described. Terminal A is positive between terminals AB, terminal B
Assume that a negative pulse-shaped voltage V _AB is applied and a periodic current I _AB flows. The order of magnitude of the rated current value
When the normal current I _AB flows, the N-type DMOS 1 and P
Since the potential difference in the DMOS 2 is small,
The gate voltage of S3 is small, and the potential difference in the P-type DMOS 3 is very small. When the overcurrent I _AB flows, the N-type DMOS1 and the P-type DMOS2 act on each other to
When the current I _AB is cut off, the N-type DMOS1 and the P-type DMOS
Since the power supply voltage is applied to both ends of the gate 2, the gate voltages of the N-type DMOS 1 and the P-type DMOS 2 increase. And P
Drain type DMOS3 is connected to the gate of the N-type DMOS1, for the gate of the P-type DMOS3 is connected to the drain of the N-type DMOS1, the gate of the P-type DMOS3
The voltage increases, and the potential difference in the P-type DMOS 3 is
It becomes a certain size. The drain of the P-type DMOS 4 is connected to the source of the P-type DMOS 3,
The source of S4 is connected to the source of N-type DMOS 5, and the drain of N-type DMOS 5 is connected to P-type DMOS 2 through resistor 6.
And the gate of the P-type DMOS 4 is connected to the P-type
The gate of the N-type DMOS 5 is connected to the drain of the P-type DMOS 3 (the gate of the N-type DMOS 1).
For the current flowing to the MOS5, the P-type DMOS4 and N
Although the DMOS 5 enters a low resistance state, the current flowing from the N-type DMOS 5 to the P-type DMOS 4
The potential difference at S3 and S4 becomes the gate voltage of N-type DMOS 5, and the potential difference at N-type DMOS 5
4 and a P-type DMOS 4 and an N-type D
MOS 5 enters a high resistance state or a cutoff state. Therefore, the pulse-like voltage VAB is changed from the period in which the voltage is applied to
When the voltage falls and the voltage reaches the OV cycle, the voltage is increased.
In the cycle, the charged gate voltage of the N-type DMOS 1 is discharged, so that the gate current in the opposite direction becomes the N-type DMOS.
But it tends to flow to the P-type DMOS4 from 5, when the cut-off, Oh
The potential difference of the P-type DMOS 3 which has become
It becomes the gate voltage of the mold DMOS5, the potential difference in the N-type DMOS5 large ing. And the N-type DMOS 5
The gate voltage of the P-type DMOS4 is increased by a large potential difference, P-type DMOS4 and N-type DMOS5 goes high-resistance state or blocking state, the gate voltage of the N-type DMOS1 is held without being discharged Runode, N-type DMOS1 Is kept off.

Similarly, the P-type DMOS 8 and the N-type DMOSs 9 and 10 connected to the gate of the P-type DMOS 2
P flowing from P-type DMOS 8 to N-type DMOS 9
A low-resistance state is established for the charging current of the gate of the D-type DMOS 2 and a charging current flows. However, a high-resistance state is set for the discharging current of the gate of the P-type DMOS 2 flowing from the N-type DMOS 9 to the P-type DMOS 8. In this state, the discharge current is cut off, the gate voltage of the P-type DMOS 2 is maintained, and the cut-off state of the P-type DMOS 2 is maintained. As a result, the cutoff state of the overcurrent protection circuit is maintained until the next cycle in which a voltage is applied, so that a peak-like rush current does not flow in each pulse cycle, and the pulse-like overcurrent can be cut off. it can. In addition, when the resistance value of the resistor 6 connected to the gate of the N-type DMOS 1 and the resistance value of the resistor 7 connected to the gate of the P-type DMOS 2 are reduced, the cutoff time can be shortened. Can be. P-type DMO connected to the gate of N-type DMOS1
S3 or N-type D connected to the gate of P-type DMOS2
One of the MOSs 10 may be removed to form an overcurrent protection circuit.

Another embodiment will be described with reference to FIG. FIG.
In the embodiment, the gate of the P-type DMOS 3 is an N-type DMOS
1, the gate of the P-type DMOS 4 is connected to the drain of the P-type DMOS 2, the gate of the N-type DMOS 9 is connected to the drain of the N-type DMOS 1, and the N-type DMOS
Although the gate of the P-type DMOS 3 is connected to the drain of the P-type DMOS 2 in the embodiment of FIG.
The gate of the P-type DMOS 4 is connected to the drain of the N-type DMOS 1,
The gate of S9 is connected to the drain of P-type DMOS2,
The gate of the type DMOS 10 is connected to the drain of the N-type DMOS 1. Otherwise, the embodiment of FIG. 2 is the same as the embodiment of FIG. In the embodiment of FIG. 2 , overcurrent can be cut off as in the embodiment of FIG. The overcurrent protection circuit described above is a DC-type overcurrent protection circuit in which the terminal A is positive and the terminal B is negative, but two DC-type overcurrent protection circuits are connected in series in the reverse direction. Accordingly, an AC overcurrent protection circuit can be obtained.

[0011]

Since the present invention is configured as described above, it exhibits the following effects. Since this overcurrent protection circuit is composed of a depletion type MOS semiconductor, if the circuit is composed of a depletion type MOS semiconductor having a small threshold voltage,
The voltage drop in the overcurrent protection circuit when a normal current flows can be reduced, and the normal current of the load circuit does not cross one PN junction in the overcurrent protection circuit. You can stand up smoothly.

The gates of the N-type DMOS1 and the P-type DMOS2, through which the load circuit current flows, have a low resistance state with respect to the charging current of the gate and a cutoff state with respect to the discharging current of the gate. Since the pair of the type DMOS and the N-type DMOS is connected, the gate voltage at the time of shutting down is maintained even when the temperature used is high or low, and the overcurrent protection circuit holds the shutoff state. The overcurrent protection circuit can cut off the pulse-like overcurrent without causing the peak-like rush current to flow at each pulse period.

A resistor 6 connected to the gate of the N-type DMOS 1 and a resistor 7 connected to the gate of the P-type DMOS 2
If the resistance value is small, the cutoff time can be shortened, and if it is increased, the cutoff time can be reduced. Therefore, the overcurrent protection circuit can be either a fast-acting type or a delay type according to the load. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an overcurrent protection circuit of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the overcurrent protection circuit of the present invention.

FIG. 3 is a diagram showing static characteristics of cutoff of the overcurrent protection circuit of the present invention.

[Explanation of symbols]

 1,5,9,10 N-type depletion type MOS semiconductor 2,3,4,8 P-type depletion type MOS semiconductor 6,7 Resistance

Claims (2)

(57) [Claims] 1. A source of an N-type depletion type MOS semiconductor (1) is connected to a source of a P-type depletion type MOS semiconductor (2), and the gate of the N-type depletion type MOS semiconductor (1) has a P-type depletion type MOS semiconductor. P-type depletion type MOS semiconductor (3) connected to the drain of semiconductor (3)
Is a P-type depletion type MOS semiconductor (4)
The source of the P-type depletion type MOS semiconductor (4) is connected to the source of the N-type depletion type MOS semiconductor (5), and the drain of the N-type depletion type MOS semiconductor (5) is connected through the resistor (6). P
The gate of the P-type depletion type MOS semiconductor (2) is connected to the drain of the N-type depletion type MOS semiconductor (10), and the N-type depletion type MOS semiconductor (10) is connected to the drain of the N-type depletion type MOS semiconductor (10).
Is N-type depletion type MOS semiconductor (9)
And the source of the N-type depletion type MOS semiconductor (9) is connected to the source of the P-type depletion type MOS semiconductor (8), and the drain of the P-type depletion type MOS semiconductor (8) is connected through a resistor (7). N
The gate of the P-type depletion type MOS semiconductor (3) is connected to the drain of the N-type depletion type MOS semiconductor (1), and the P-type depletion type MOS semiconductor (4) is connected to the drain of the N-type depletion type MOS semiconductor (1).
Is a P-type depletion type MOS semiconductor (2)
The gate of the N-type depletion type MOS semiconductor (3) is connected to the drain of the P-type depletion type MOS semiconductor (3). The gate of the N-type depletion type MOS semiconductor (10) is connected to the P-type depletion type MOS semiconductor. N-type depletion type MOS semiconductor (9) connected to the drain of semiconductor (2)
Gate is N-type depletion type MOS semiconductor (1)
The gate of the P-type depletion type MOS semiconductor (8) is connected to the drain of the N-type depletion type MOS semiconductor (10); the drain of the N-type depletion type MOS semiconductor (1) is used as a positive terminal; An overcurrent protection circuit in which the drain of the P-type depletion type MOS semiconductor (2) has a negative terminal. 2. The source of an N-type depletion type MOS semiconductor (1) is connected to the source of a P-type depletion type MOS semiconductor (2), and the gate of the N-type depletion type MOS semiconductor (1) has a P-type depletion type MOS semiconductor. P-type depletion type MOS semiconductor (3) connected to the drain of semiconductor (3)
Is a P-type depletion type MOS semiconductor (4)
The source of the P-type depletion type MOS semiconductor (4) is connected to the source of the N-type depletion type MOS semiconductor (5), and the drain of the N-type depletion type MOS semiconductor (5) is connected through the resistor (6). P
The gate of the P-type depletion type MOS semiconductor (2) is connected to the drain of the N-type depletion type MOS semiconductor (10), and the N-type depletion type MOS semiconductor (10) is connected to the drain of the N-type depletion type MOS semiconductor (10).
Is N-type depletion type MOS semiconductor (9)
And the source of the N-type depletion type MOS semiconductor (9) is connected to the source of the P-type depletion type MOS semiconductor (8), and the drain of the P-type depletion type MOS semiconductor (8) is connected through a resistor (7). N
The gate of the P-type depletion type MOS semiconductor (3) is connected to the drain of the P-type depletion type MOS semiconductor (2), and the P-type depletion type MOS semiconductor (4) is connected to the drain of the P-type depletion type MOS semiconductor (2).
Gate is N-type depletion type MOS semiconductor (1)
And the gate of the N-type depletion type MOS semiconductor (5) is connected to the drain of the P-type depletion type MOS semiconductor (3). The gate of the N-type depletion type MOS semiconductor (10) is N-type depletion type MOS. N-type depletion type MOS semiconductor (9) connected to the drain of semiconductor (1)
Is a P-type depletion type MOS semiconductor (2)
The gate of the P-type depletion type MOS semiconductor (8) is connected to the drain of the N-type depletion type MOS semiconductor (10); the drain of the N-type depletion type MOS semiconductor (1) is used as a positive terminal; An overcurrent protection circuit in which the drain of the P-type depletion type MOS semiconductor (2) has a negative terminal.