JP2782748B2 - Oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION At one end of a parallel resonance circuit, a positive feedback circuit including a base of a transistor of an emitter follower and a current mirror circuit for positively feeding back an output current of the transistor is connected.
The other end is connected to a level shift circuit composed of a diode function element, which generates a bias voltage when a DC bias current is applied. As a result, even if the level shift circuit is manufactured in the bipolar IC, it is possible to prevent the oscillation amplitude from being clamped by the parasitic diode and the parasitic capacitor and the adverse effects of the phase delay.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit, for example, to a high-frequency oscillation circuit provided in a high-frequency oscillation type proximity switch for detecting an object or the like.

2. Description of the Related Art Oscillation circuits of this kind include an emitter-follower connected transistor, a current mirror circuit for feeding back the output current of the transistor, and a detection coil to which a feedback current is supplied by the current mirror circuit. And a capacitor, a parallel resonance circuit, a DC bias application circuit for generating a DC bias current, and a level shift circuit for obtaining a bias voltage by applying the bias current. In such an oscillating circuit, as shown in FIG. 3, a case is considered in which the level shift circuit is configured by a bipolar IC.

In this figure, a positive feedback circuit (indicated by a chain line in FIG. 3) for returning an output current of the transistor 1 to a parallel resonance circuit (tank circuit) 8 is formed at the collector of the transistor 1 of the emitter follower. Current mirror circuit 4 is connected. The current mirror circuit 4 includes a transistor 2 and a transistor 3 having a base and a collector connected in common. The resonance circuit 8 includes a capacitor 6 and a coil 7 connected in parallel. In the positive feedback circuit, a bias voltage is obtained by a DC bias current from a DC bias circuit (current source) 10 to obtain a transistor 1.
Is provided with a level shift circuit 9 for applying a bias voltage to the base. The level shift circuit 9 is composed of a transistor for making the oscillation circuit an IC, and the base and the collector of the transistor are commonly connected (diode-connected transistor). The emitter of the transistor 1 is grounded via the output resistor 5. An oscillation output is obtained from the resistor 5.

When such an oscillation circuit fabricated in Morinoshikku IC on the devices structures, as indicated by broken lines, the parasitic capacitor C _CS and the parasitic diode D _CS is generated in the diode-connected transistor 9 constituting the level shift circuit.
When such a parasitic diode _DCS and a parasitic capacitor _CCS occur in the level shift circuit in a high-frequency oscillation state, the following problem occurs.

As shown in FIG. 4 (A), when the oscillation amplitude (V _PP : voltage from peak to peak) does not exceed 2V _BE (V _BE is the base-emitter voltage of transistor 1), the level shift circuit By the original level shift function, the LC terminal voltage of the parallel resonance circuit 8 is level-shifted to the bias point A by the voltage _VA as shown in FIG.

On the other hand, if the oscillation amplitude as FIG. 5 (A) is to exceeding 2V _BE, charging voltage V _F of the parasitic diode D _CS (Fifth
(In the case of FIG. 5, V _F = V _A ), the negative peak portion is clamped as shown by the hatched portion a in FIG. 5B, and the oscillation amplitude itself is eventually limited.

In the circuit shown in FIG. 3, the level shift circuit 9 is operated by the bias current I _BIAS from the DC bias circuit 10. That is, in the steady state as shown in FIG. 7, it is obtained a V _A becomes the voltage by the bias current I _BIAS = I _0. Here, in an ideal state without the parasitic capacitor _CCS , this oscillation circuit oscillates with an amplitude corresponding to the conductance of the parallel circuit 8, and the voltage of the LC terminal of the parallel resonance circuit 8 is level-shifted by the voltage _VA. Appears at point A on the base of transistor 1.

However, due to the effect of the parasitic capacitor C _CS , the rise of the LC terminal voltage (waveform W _{B in} FIG. 6) of the parallel resonance circuit 8
When the potential at point A is about to rise, the parasitic capacitor C
Since the charging current to the _CS DC bias current I _BIAS to flow (the current and I _CS), the current flowing through the level shift circuit 9 is I ₁ = I _BIAS -I _CS becomes parasitic capacitor C _CS
As shown in FIG. 7, the parallel resonance circuit 8
Voltage of the LC terminal becomes smaller voltages V ₁ than the voltage V _A of the steady.

Conversely, when the LC terminal voltage of the parallel resonance circuit 8 decreases, the discharge current I _CS from the parasitic capacitor C _CS flows through the level shift circuit 9, so that the current flowing through the level shift circuit is I ₂ = I _BIAS + _ICS as shown in FIG.
The voltage V ₂ becomes larger than V _A. Therefore, the shaded area b in FIG.
As shown in (c) and (c), the phase lag occurs and the original oscillation amplitude
The waveform W _A is different from W _B.

Actually, the effect of charging the parasitic capacitor C _CS is particularly large. To avoid this effect, the DC bias current I _{BIAS is set} to a sufficiently large value to _{speed up} the charging of the parasitic capacitor C _CS . However, in this method, the current consumption of the oscillation circuit increases, and a low current consumption type oscillation circuit cannot be realized. In the positive feedback circuit of the oscillation circuit, feedback with a delayed phase is applied, and the oscillation circuit operates with poor feedback efficiency. Therefore, a change in the oscillation amplitude is hardly obtained with respect to a slight change in the conductance of the parallel resonance circuit ₈ , and only the proximity switch having low detection sensitivity can be provided even if the oscillation circuit is applied to the proximity switch. This is a problem especially when a very small current flows with a high-frequency signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide an oscillation circuit that does not cause amplitude clamp and phase delay due to a parasitic diode and a parasitic capacitor that are generated when an IC is formed.

Oscillation circuit according to the present invention includes an oscillation transistor connected in an emitter-follower connection, a DC bias circuit for supplying a DC bias current, and a diode function element for generating a bias voltage by the DC bias current supplied from the DC bias circuit. , A parallel resonance circuit including a coil and a capacitor, and a current mirror circuit for positively feeding back the output current of the oscillation transistor to the parallel resonance circuit. One end of the parallel resonance circuit includes the oscillation circuit. A positive feedback circuit including a base of a transistor and the current mirror circuit is connected, and the level shift circuit is connected to the other end of the parallel resonance circuit.

According to the present invention, since the level shift circuit is provided outside the positive feedback circuit, the oscillation amplitude is limited only by the power supply voltage.
The oscillation amplitude is not clamped by the parasitic diode. Also, since there is no influence of the charge and discharge delay of the parasitic capacitor, the phase delay of feedback is eliminated.

In addition, the oscillation amplitude of the resonance circuit can be widened to the range of the power supply voltage, and the sensitivity of the resonance circuit directly appears as a change in the amplitude of the oscillation circuit. When applied to such applications, the sensitivity is high. Furthermore, since the DC bias current can be reduced, the current consumption of the oscillation circuit can be reduced.

FIG. 1 is a circuit diagram showing an embodiment of an oscillation circuit according to the present invention. In this figure, the same components as those shown in FIG.

In the oscillation circuit shown in FIG. 1, one end of a parallel resonance circuit 8 is connected to a positive feedback circuit (shown by a chain line) composed of a transistor ₁ connected in an emitter-follower manner and a current mirror circuit 4, and The other end is connected to the base and collector of a diode-connected NPN transistor as the level shift circuit 9, and the emitter of this transistor is connected to ground. With this configuration, the level shift circuit 9 is connected outside the positive feedback circuit. Then, so that the parasitic diode D _CS and the parasitic capacitor C _CS caused by constructing the level shift circuit 9 in bipolar IC is connected to the outside of the positive feedback circuit.

Therefore, the oscillation amplitude of this oscillation circuit is
Since not limited by D _CS within the power supply voltage, it is possible to obtain the oscillation amplitude. It becomes independent of the further influence of the phase delay of the conventional kind of parasitic capacitor C _CS by the level shift.

FIG. 2 is a circuit showing another embodiment. The same parts as those in the circuit shown in FIG. The circuit shown in FIG. 2 is different from the circuit shown in FIG. 1 in that the level shift circuit is composed of a diode-connected NPN transistor 9 and a capacitor 11 connected in parallel thereto. The capacitor is for keeping the level shift amount constant.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing another embodiment. FIG. 3 shows an example of a conventional oscillation circuit. FIGS. 4 (A) and (B) and FIGS. 5 (A) and (B) show the amplitude of the parallel resonance circuit and the output waveform of the oscillation circuit. FIGS. 4 (A) and (B) show V _Shows when _PP ≤ 2V _BE ,
5A shows the output amplitude of the parallel resonance circuit, FIG. 5B shows the output waveform of the oscillation circuit, and FIGS.
Indicates when the _PP> 2V _BE, shows (A) is the output amplitude of the parallel resonant circuit, (B) is the output waveform of the oscillator circuit, respectively. FIG. 6 is a waveform diagram showing the amplitude of the parallel resonance circuit and the output amplitude of the oscillation circuit, and showing a state in which a phase delay has occurred in the output amplitude due to a parasitic capacitor. FIG. 7 is a graph showing characteristics of a current supplied to the level shift circuit and a voltage obtained from the level shift circuit. 1 oscillation transistor, 4 current mirror circuit, 8 parallel resonance circuit, 9 level shift circuit, 10 DC bias circuit, C _CS parasitic capacitor, D _CS parasitic diode.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hirofumi Endo 10th Hanazono Todocho, Ukyo-ku, Kyoto-shi, Kyoto Prefecture Inside Tateishi Electric Co., Ltd. Co., Ltd. (72) Inventor Satoshi Motoshi Tateishi Electric Co., Ltd., 10-10 Hanazono Todocho, Ukyo-ku, Kyoto-shi, Kyoto Prefecture (56) References JP-A-1-226217 (JP, A) JP, A) JP-A-57-131128 (JP, A) JP-A-55-39109 (JP, A)

Claims (1)

(57) [Claims] 1. A level shift circuit comprising: an emitter-follower connected oscillation transistor; a DC bias circuit for supplying a DC bias current; and a diode function element for generating a bias voltage by the DC bias current supplied from the DC bias circuit. , A parallel resonance circuit comprising a coil and a capacitor, and a current mirror circuit for positively feeding back the output current of the oscillation transistor to the parallel resonance circuit. One end of the parallel resonance circuit has a base of the oscillation transistor and the current mirror. An oscillation circuit, wherein a positive feedback circuit comprising a circuit and the level shift circuit is connected to the other end of the parallel resonance circuit.