JP2765367B2 - Mask pattern design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of designing a mask pattern, and more particularly to a method of designing a mask pattern for arranging and wiring circuit elements in a semiconductor circuit.

[0002]

2. Description of the Related Art A conventional mask pattern designing method is shown in FIG.
As shown in FIG. 1, first, the circuit element blocks 11 to 15 are arranged, and then the circuit element blocks 11 to 15 are held while the arrangement positions of the circuit element blocks 11 to 15 are relatively held.
The wirings 21 to 25, 31 and the like between 15 are performed. Here, the wiring of the first wiring layer is indicated by a solid line, the wiring of the second wiring layer is indicated by a dotted line, and the through holes are indicated by white circles.

FIG. 2 shows a circuit diagram of a multiplexer circuit as an example of this type of mask pattern design. FIG.
As shown in the figure, switches M1 to M
4 are circuit element blocks 11 to 14 in FIG.
The inverter IN1 corresponds to the circuit element block 15, respectively. In addition, the node N1 input to the output inverter IN1 has a regular configuration in which outputs of the same logic circuit including the switches M1 to M4 are connected in parallel.

In the case of a circuit having such a regular configuration, designing a mask pattern centering on the node N1, which is a main cause of regularity, is more compact overall and improves circuit characteristics. It is thought that.

[0005]

In the above-described conventional mask pattern designing method, first, circuit element blocks are arranged, and then wiring between the circuit elements is performed. Even in the case of (1), an optimal mask pattern cannot be designed around a node or the like which is a main cause of regularity, and there is a disadvantage that a circuit area increases and circuit characteristics deteriorate.

[0006]

A mask pattern designing method according to the present invention comprises a plurality of circuit element blocks and a plurality of wirings connecting the circuit element blocks, and has a regular circuit configuration with respect to predetermined nodes. In the mask pattern designing method for the first circuit including the second circuit, the node which is a determining factor of the regularity of the second circuit is extracted, a wiring path of the node is determined, and the wiring path is adapted. The circuit element blocks are arranged so that

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a mask pattern diagram showing an embodiment of a mask pattern designing method according to the present invention.

The mask pattern diagram of this embodiment is an example in which the same mask pattern of the circuit of FIG. 2 as that of the conventional example is realized. As shown in FIG.
And wirings 24 and 25 for power supply VC and ground G, and node N
1 as a wiring 41. The wiring of the first wiring layer is indicated by a solid line, the wiring of the second wiring layer is indicated by a dotted line, and the through holes are indicated by white circles.

Next, the operation of this embodiment will be described.

FIG. 2 is a circuit diagram of a multiplexer circuit similar to the conventional example. Switches M1 to M4 are connected to circuit element blocks 11 to 14 in FIG.
1 corresponds to each of the circuit element blocks 15. Also,
The node N1 input to the output inverter IN1 has a regular configuration in which outputs of the same logic circuit including the switches M1 to M4 are connected in parallel.

First, in the multiplexer circuit shown in FIG. 2, attention is paid to a node N1 at which outputs of the switches M1 to M4 are wired-logic. The wiring path of the wiring 41 forming the node N1 is determined in the lateral direction of the mask pattern as shown in FIG.

The wirings 51-54 on the output side of the four switches M1-M4 connected to the node N1, ie, the wiring 41
And the wiring 55 on the input side of the inverter IN1 are arranged so as to be as straight as possible without bending.

Switches M1 to M4 and inverter IN
The inside of each of the circuit element blocks 11 to 15 is completed by a diffusion layer, a polysilicon layer, and a first wiring layer. Therefore, if the second wiring layer is used as a part of the wiring 41 at the node N1, the wiring portions of the circuit elements blocks 11 to 15 can be passed, and the wiring paths of the wirings 51 to 55 connected to the wiring 41 are almost broken. Can be arranged without bending.

Finally, the input lines I of the switches M11 to M14
1 to I4 wirings 61 to 64 and enable lines E1A, B1 to
The wirings 71 to 74 of E4A and B are arranged orthogonally to the wirings 41 and 51 to 55, and the wiring 24 of the power supply VC and the wiring 2 of the ground G are arranged.
5 is arranged in parallel with the wirings 41, 51 to 55 to complete the process.

As an example, the mask pattern according to the method of this embodiment has a circuit area of about 4% and a node N1 as compared with the conventional example.
Can be reduced by about 30%.

[0017]

As described above, in the mask pattern designing method of the present invention, the circuit element block is arranged after determining the wiring route of the node which causes the regularity of the circuit. There is an effect that the entire mask pattern can be designed compactly and the circuit characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a mask pattern diagram showing an embodiment of a mask pattern designing method according to the present invention.

FIG. 2 is a circuit diagram of a multiplexer circuit showing an example of a target circuit of the present embodiment and a conventional mask pattern designing method.

FIG. 3 is a mask pattern diagram showing an example of a conventional mask pattern designing method.

[Explanation of symbols]

11 to 15 circuit element blocks 21 to 25, 31, 41, 51 to 55, 61 to 64, 7
1-74 Wiring M1-M4 Switch IN1 Inverter

Claims (1)

(57) [Claims] 1. A mask pattern of a first circuit including a second circuit having a plurality of circuit element blocks and a plurality of wirings interconnecting the circuit element blocks and having a regular circuit configuration with respect to predetermined nodes. In the design method, the node which is a determinant of the regularity of the second circuit is extracted, a wiring path of the node is determined, and the circuit element block is arranged so as to conform to the wiring path. Mask pattern design method.