JP2760821B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an external connection electrode.

(Prior art)

It is known to use a metal projection electrode as an external connection electrode of a semiconductor integrated circuit, and a lift-off method is used as a method for forming the metal projection electrode. In this lift-off method, after forming a base electrode at a desired position on an insulating film, a release layer is deposited on the insulating film, and then the release layer on the projection electrode formation region is removed to expose the base electrode. Let
A metal layer is deposited on the release layer, and the release layer is decomposed and dissolved in a release liquid to selectively remove the metal layer on the release layer to form an electrode-forming metal layer at a desired position. Is the way. Conventionally, two layers of tin (Sn) and lead (Pb) are used as the above-mentioned metal layer, and after forming a metal layer for forming an electrode, it is heated and melted to form a spherical solder bump electrode. Since the protruding electrode is spherical, the base electrode is also formed in a circular shape. Such a base electrode is formed by using BLM (Ball Limiting Metalizatio).
n) Also called an electrode.

Conventionally, the release layer is composed of a non-photosensitive resist film deposited thinly and a photosensitive negative resist film deposited thickly thereon, and selectively exposes the negative resist film on a region where the electrode is not formed. After immersion, it is immersed in a developer. At this time, the non-exposed, that is, the negative resist film on the electrode forming region is removed to form a circular second opening, and the lower non-photosensitive resist film is also dissolved by the developer to form a circular second resist. One opening is formed. An opening is formed on the electrode forming region by the first opening and the second opening. Since the side wall of the first opening is also dissolved by the developer, the first opening is formed larger than the second opening. The opening has a so-called overhang section. After the opening is formed, (Sn) to be lead (Pb) is sequentially deposited on the upper surface of the peeling layer and the base electrode in the opening, but intentionally by forming an overhang in the opening. Since the step coverage is reduced, the upper surface of the release layer and the metal layer deposited on the base electrode are separated from each other. At this time, the side surface of the metal layer is slightly inclined with respect to the substrate with respect to the vertical direction, and has a gentle shape.

In addition, as an example described about the lift-off process,
There is Japanese Patent Application No. 61-225981.

[Problems to be solved by the invention]

A semiconductor integrated circuit device having a solder bump electrode is electrically connected to and fixed to a wiring board via the electrode. When the substrate of the semiconductor integrated circuit device and the wiring substrate have different coefficients of thermal expansion, a large stress is applied to the protruding electrodes due to high heat generated during operation of the semiconductor integrated circuit device.

As the size of the circuit device increases, the strain generated in the circuit device also increases, and accordingly, the stress applied to the bump electrode also increases. In order to improve the mechanical strength of the solder bump electrode in response to this stress, it is necessary to increase the bump electrode dimension. However, in order to increase the bump electrode, the electrode forming metal layer must be deposited high. . However, when the metal layer for forming an electrode is deposited high, the angle of the side surface of the metal layer having the shape of a truncated cone gradually approaches vertical, and the second layer of the peeling layer becomes second.
The distance between the opening and the metal layer becomes narrower, so that even when trying to decompose and dissolve the release layer in the release liquid, the inflow of the solvent is hindered and it is difficult to flow into the contact portion between the release layer and the insulating film. . In addition, since the release layer expands due to the flow of the release liquid, the metal layer for electrode formation and the release layer come into contact with each other at the end, and the release liquid does not flow any more. For this reason, the height from the bottom surface to the overhanging portion is increased while the bite size of the lower resist film in the opening having the overhanging cross-sectional shape remains the same as in the conventional case, and the truncated cone-shaped metal layer and the second opening are formed. It is necessary to secure the path of the stripping liquid by widening the interval between the two. In order to increase the height to the overhang, the lower resist film may be thickened.However, in the conventional method of dissolving a non-photosensitive resist film with a developing solution, the horizontal resist film is dissolved while dissolving the thick resist film. Dissolution also proceeds in the direction, and the diameter of the first opening becomes undesirably large. If the distance between the adjacent first openings is small, the first openings may be undesirably enlarged, but the connection may occur. In this case, the electrode forming metal layers formed in a later process may be short-circuited. Therefore, there is a problem that the interval between the metal protruding electrodes arranged on the substrate cannot be reduced to a certain value or less.
Further, when the metal layer is deposited in a state where the first opening is undesirably large, the metal layer undesirably spreads in the first opening, a metal layer is formed on the side of the first opening, and the peeling layer is removed. It remains afterwards. There is a problem that the remaining metal layer peels off with the passage of time and becomes a foreign substance, contacts an adjacent electrode or the like, and causes a short circuit failure.

In the method of dissolving the lower resist film with a developing solution, the side surface of the first opening may not be perpendicular to the substrate, and the upper and lower ends of the side surface may be arcuate. For this reason, there is a problem that a metal layer is also formed on the side surface and remains as a foreign substance even after the release layer is removed, which causes a short circuit failure.

In addition, the release layer is decomposed in the conventionally used release liquid.
In the method of dissolving, the release liquid enters only from the edge of the opening of the release layer to decompose and dissolve the release layer. For this reason, in a region where the openings are densely located, the peeling liquid easily penetrates through the openings and the peeling can be performed satisfactorily. It takes a long time until the process is completed, or peeling failure easily occurs. Particularly, a semiconductor integrated circuit device having a built-in DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) has a problem that α generated from radioactive elements (U and Th) contained in a trace amount of solder. In order to prevent the occurrence of soft errors in the lines, the protruding electrodes are not provided in the memory cell array that occupies the majority of the integrated circuit device, and there is a problem that the processing time is long in this region or peeling failure is likely to occur. Found by the inventor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a lift-off type semiconductor integrated circuit device capable of forming a metal projection electrode larger than a conventional one.

It is another object of the present invention to provide a method of manufacturing a lift-off type semiconductor integrated circuit device which can reduce the distance between metal electrodes.

Another object of the present invention is to provide a method of manufacturing a lift-off type semiconductor integrated circuit device which does not generate foreign matter when a metal layer for forming an electrode is formed.

Still another object of the present invention is to provide a method of manufacturing a lift-off type semiconductor integrated circuit device, which can shorten the processing time and prevent the occurrence of peeling failure.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a first release layer is formed on an insulating film provided on a semiconductor substrate, a first opening is formed in the first release layer on a region where a pattern is to be formed, and then a second release film is formed. A second release layer is formed on the first opening and a second opening smaller than the first opening is formed. At this time, a third opening independent of the first opening is formed in a required portion of the first layer release layer on a region where the first opening is not formed, and a third opening is formed on the second layer release layer on the third opening. Four openings are formed.

(Operation)

According to the above-described means, since the first opening is formed by exposing and developing the first release layer, the first opening is formed in the horizontal direction as in the conventional method of dissolving a non-photosensitive resist film with a developing solution. Undesired progress of dissolution does not occur, and the size of the first opening can be accurately determined regardless of the thickness of the first release layer.
Since the second opening formed in the upper layer is also formed by exposure and development, the size can be accurately determined. In other words, the amount of overhang on the first opening where the second opening is formed in the opening having the overhang-shaped cross section can be accurately determined. Further, by changing the thickness of the lower first release layer, the height from the overhang portion to the bottom surface of the opening can be changed as appropriate.

Further, since the adjacent first openings are not connected with each other due to the progress of the melting, the interval between the pattern forming regions can be further reduced.

Further, since the side wall of the opening is formed perpendicular to the substrate, it is possible to prevent the conductor from depositing on the side wall of the opening when depositing the conductor.

Further, since a third opening is formed in a required portion of the first release layer, and a film-like second release layer is adhered on the third opening to form a cavity, the third opening enters only through the opening. The time required for the release liquid to completely decompose and dissolve the first release layer is reduced, and the occurrence of defective peeling can be prevented. In particular, the effect is remarkable in a portion where the opening is sparsely formed.

Furthermore, since the fourth opening is formed in the film-like second release layer on the third opening, when the semiconductor integrated circuit device is exposed to vacuum in the metal layer deposition step,
It is possible to prevent the air in the cavity from expanding and forming the film-like second release layer.

[Embodiment 1] FIG. 1 shows a memory LSI composed of bipolar transistors.
A vertical sectional view near the metal bump electrode is shown.

FIG. 2 is a plan view of the memory LSI shown in FIG. Although not shown in FIG. 2, the memory LSI is mounted on a wiring board via bump electrodes made of, for example, solder. The memory LSI is constituted by an SRAM, and a memory cell array MARY is arranged at a central portion. In the memory cell array MARY, a plurality of memory cells are arranged in a matrix.

As shown in FIG. 2, peripheral circuits including an input circuit Din, an output circuit Dout, a power supply circuit VC, an address buffer circuit AB, an X decoder circuit XD, a Y decoder circuit YD, and the like are arranged in a peripheral portion of the memory LSI. ing. The semiconductor elements constituting each circuit of the peripheral circuit are not particularly limited,
It is a bipolar transistor. The memory LSI has a two-layer wiring structure. Although not shown in FIG. 2, the external terminal BP is formed on each circuit of the peripheral circuit, although not particularly limited. The external terminal BP is not formed on the memory cell array MARY in order to reduce a soft error due to α rays generated from a trace amount of radioactive elements (U and Th) contained in the solder metal bump electrode 4. A memory cell composed of a bipolar transistor is more resistant to α-ray soft errors than a memory cell composed of MISFETs, but the external terminal BP is not formed on the memory cell MARY in order to improve the margin for soft errors.

The bipolar transistor shown in FIG. 1 is formed on a main surface of a semiconductor substrate 2A in which a P-type impurity is diffused at a low concentration. The bipolar transistor is electrically isolated from other regions by an isolation region including the semiconductor substrate 2A, the P ⁺ type semiconductor region 2D, and the element isolation insulating film 2E.
The semiconductor region 2D is composed of a semiconductor substrate 2A and N ⁻ grown thereon.
It is formed between the type epitaxial layer 2B. That is, the semiconductor region 2D is a buried semiconductor region. The element isolation insulating film 2E is formed on the main surface of the epitaxial layer 2B so as to reach the semiconductor region 2D. The element isolation insulating film 2E is formed of a silicon oxide film obtained by oxidizing the main surface of the epitaxial layer 2B. The bipolar transistor is of an NPN type including an N-type collector region C, a P-type base region B, and an N-type emitter region E.

The collector region C is composed of an N ⁺ type semiconductor region 2C, an epitaxial layer 2B, and a potential raising N ⁺ type semiconductor region 2F. The semiconductor region 2C is, like the semiconductor region 2D, a semiconductor substrate.
This is a buried semiconductor region provided between 2A and the epitaxial layer 2B. The semiconductor region 2F is provided on the main surface of the epitaxial layer 2B so as to reach the semiconductor region 2C. The first layer wiring 2N is connected to the semiconductor region 2F of the collector region C through a connection hole 2M formed in the interlayer insulating film 2L. The wiring 2N is formed of an aluminum film or an aluminum film to which Cu or Si is added.

Cu reduces stress migration, and Si reduces the occurrence of alloy spikes.

The base region B is composed of a P-type semiconductor region 2G provided on the main surface of the epitaxial layer 2B constituting the collector region C. The wiring 2N is connected to the semiconductor region 2G that is the base region B.

The emitter region E is composed of an N ⁺ type semiconductor region 2H provided on the main surface of the semiconductor region 2G constituting the base region B. An emitter electrode 2K is connected to the semiconductor region 2H, which is the emitter region E, through a connection hole 2J formed in the insulating film 2I. The emitter electrode 2K is an N-type impurity (P or
(As) is formed of polycrystalline silicon. The semiconductor region 2H is formed by diffusing the N-type impurity introduced into the emitter electrode 2K into the semiconductor region 2G. Although not shown, the polycrystalline silicon forming the emitter electrode 2K constitutes a wiring, a resistance element, and the like in other regions. Similarly, a wiring 2N is connected to the emitter electrode 2K.

A second layer wiring 2Q is provided above the first layer wiring 2N with an interlayer insulating film 20 interposed therebetween. As described above, the memory LSI has a two-layer wiring structure. Wiring 2
N and the wiring 2Q are connected through a connection hole 2P formed in the interlayer insulating film 2O. Each of the interlayer insulating films 2L and 2O is formed mainly of a silicon oxide film.

A surface protection film 41 is provided on the second layer wiring 2Q. The surface protection film 41 is formed of, for example, a nitride film deposited by plasma CVD.

The second layer wiring 2Q forms an external terminal BP on each of the peripheral circuits. An opening 2V is formed in the surface protection film 41 on the wiring 2Q to be the external terminal BP. The BLM electrode 50 is provided on the wiring 2Q, which is the external terminal BP, through the opening 2V. The BIM electrode 50 is composed of a composite film in which Cr, Cu, and Au are sequentially laminated. For wiring 2Q, which is the external terminal BP,
One end of the metal bump electrode 4 made of, for example, solder is connected with the BLM electrode 50 interposed therebetween.

Next, a manufacturing process of the metal bump electrode shown in FIG. 1 will be described with reference to FIGS. 3 (a) to 3 (e).

As shown in FIG. 3 (a), the solder bump electrode base electrode 50 is formed at a required position on the surface protection film 41 on the semiconductor substrate 2A through a predetermined process, and the BLM electrode 50 is placed from above. A
It has a three-layer structure of l, Cu, and Cr. A liquid negative resist film 51 is applied on the surface protective film 41 so as to flatten the unevenness of the protective film, for example, about 10 to 15 [μm]. Next, although not shown, a mask formed in a required pattern is placed on the liquid negative resist film 51, and ultraviolet light is irradiated through the mask to expose a resist other than a region where a metal bump electrode is to be formed. After that, the resist in the electrode formation region is removed by development. Thus, the above BLM electrode 50
An opening 51a is formed at a required position above.

As the mask, a positive resist film and chromium oxide are deposited on quartz glass, patterned with an electron beam, and then developed to form a required pattern. Since the opening 51 is formed by the above method,
The size of a is accurately determined, and even if the distance between the BLM electrodes 50 is small, the openings are not connected as in the conventional case.

In the conventional method using a non-photosensitive resist film for a lower release layer, etching proceeds while the non-photosensitive resist film is immersed in a developer for forming an opening, and the side wall of the opening becomes semi-dissolved. Although the semi-dissolved resist film was not completely removed even after washing after the etching, there was a possibility that the BLM electrode might be contaminated.According to the present embodiment, portions other than the openings were exposed in advance. Therefore, the side wall of the opening after the etching is not semi-dissolved and the BLM electrode is not contaminated.

At this time, an opening 51b independent of the opening 51a is simultaneously formed at a required position in a region where the opening 51a is not formed.
The opening 51b is for forming a cavity by attaching a film-like resist material to the upper layer, shortening the processing time when peeling in a peeling solution, and preventing peeling failure.

In FIG. 2, circuit elements, wirings, and the like formed below the surface protective film 41 are omitted.

Next, as shown in FIG. 3 (b), a methacrylic film-like negative resist film is formed on the liquid negative resist film 51.
52 (approximately 40 [μm] thick) is attached. A release layer formed by the liquid negative resist film 51 and the film negative resist film 52.
53 are configured. At this time, the hollow portion 61 is formed by the opening 51b.
Is formed.

Next, the opening 51 of the film-like negative resist film 52 is formed.
An opening 52a having a smaller diameter than the opening 51a is formed on a, and an opening 52b having a small diameter is formed on the opening 51b.
Similarly to the lower liquid negative resist film 51, a quartz glass mask is placed on the film negative resist film 52, and ultraviolet light is irradiated through the mask to form the openings 52a and 52b.
The film negative resist film 52 other than the region where the
To expose. Next, development is performed to form the openings 52a and 52b. By the opening 51a and the opening 52a,
An opening 55 having an overhanging cross-sectional shape is formed. Since the dimensions of the opening 51a and the opening 52a are accurately determined, the bite size of the lower resist film in the opening 55 is also accurately determined. Also, by changing the thickness of the lower resist film, the dimension from the overhang to the bottom surface in the opening 55 can be appropriately changed.

Therefore, the height of the electrode forming metal layer can be increased, and the solder bump electrode can be formed larger than before.
In the step of depositing a conductive layer on the release layer 53 in a vacuum, the opening 52b expands the air in the cavity 61,
This is to prevent the film-shaped negative resist film 52 from being deformed.

Next, as shown in FIG. 3 (c), Pb and Sn are sequentially deposited on the entire surface so that the thickness ratio becomes, for example, 92: 8. Since the opening 55 has an overhanging cross-sectional shape and has a shape that intentionally deteriorates step coverage, the coating layer 56 deposited on the release layer 53 and the BLM
The electrode forming metal layer 57 deposited on the electrode 50 is separated from each other.

A small amount of metal is also deposited in the cavity 61 through the opening 52b.

Next, as shown in FIG. 3 (d), the entire circuit device is immersed in a stripping solution 59 such as acetone, for example.
The release layer 53 is decomposed by the release liquid that has entered from the edge of
Dissolve and peel. Conventionally, in the region where the openings 55 are sparsely formed, it takes time to completely invade the stripping solution to decompose and dissolve the stripping layer, but in the present embodiment, the cavity 61 is formed in the lower resist film. Since it is provided, the processing time can be shortened and peeling failure can be prevented. Thus, only the electrode forming metal layer 57 deposited on the BLM electrode 50 can be left on the substrate surface.

Subsequently, as shown in FIG. 3 (e), the Pb and Sn of the electrode forming metal layer 57 are heat-treated at, for example, about 350 ° C.
Is dissolved to form a spherical solder bump electrode 4. At this time
The Au layer on the surface of the BLM electrode 50 is absorbed by Pb and diffused.

The lower Cu layer reacts with Sn to form an intermetallic compound, and the lowermost layer of Cr forms a barrier metal that prevents the solder forming the solder bump electrode and the aluminum forming the wiring layer from reacting and diffusing. Work as In addition, a small amount of metal deposited in the cavity becomes a solder ball having a very small diameter by the heat treatment, and can be removed in the cleaning step.

According to the above embodiment, the following effects can be obtained.

(1) In forming the opening 55, in order to form the opening 51a in the lower liquid negative resist film 51, a mask is placed on the liquid negative resist film 51, and the opening 51a is irradiated with ultraviolet light through the mask. Since the development is carried out after selectively exposing the liquid negative resist film 51 on the region where no is formed, the size of the opening 51a can be accurately determined.
Since the upper opening 51b is also formed in the same step, the size can be determined accurately. In other words, it is possible to accurately determine the bite size of the lower resist film in the opening 55 having the overhang-shaped cross section. By changing the thickness of the lower liquid negative resist film 51, the height from the overhang of the opening to the bottom surface can be changed as appropriate. For this reason, the height of the electrode forming metal layer can be increased, and a solder bump electrode larger than before can be formed.

(2) In order to form the opening 51a in the liquid negative resist film 51, the liquid negative resist film 51 in a region where the opening 51a is not formed is selectively exposed to light and then developed. Is undesirably greatly dissolved, and adjacent openings are not connected to each other. For this reason, the dimension between the adjacent openings 51a can be formed shorter than before, and the interval between the metal protruding electrodes can be shorter than before.

(3) Since the exposure and development are used to form the openings 51a in the liquid negative resist film 51, the side walls of the openings 51a are perpendicular to the substrate. For this reason, a conductor layer is not formed on the side surface portion, and short circuit failure due to foreign matter can be prevented.

(4) Since the cavity 61 is formed in the liquid negative resist film 51, the time required for the peeling process in the region where the opening 55 is sparsely formed is reduced, and peeling failure can be prevented.

Embodiment 2 FIGS. 4 (a) to 4 (c) are longitudinal sectional views showing the steps of manufacturing a solder bump electrode according to another embodiment of the present invention.
The difference between this embodiment and the first embodiment shown in FIGS. 1 and 2 is that only one development step is required. The processing time cannot be reduced. Note that the same members as those in the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 4 (a), a BLM electrode 50 is formed at a required position on the surface protection film 41 on the semiconductor substrate 2A through a predetermined process, and the BLM electrode 50 is formed on the surface protection film 41. For example, an isoprene rubber-based liquid negative resist film 61 is formed so as to flatten the unevenness, and the resist film 61 is selectively exposed to light except for the resist film 61b immediately above the BLM electrode 50.

Next, as shown in FIG. 4B, for example, the same isoprene rubber-based film-like negative resist film 62 is attached to the upper layer of the liquid negative resist film 61, leaving the resist film 62b immediately above the BLM electrode 50. The resist film 61 is selectively exposed.

The light source for exposing the film-like negative resist film 62 is a lower liquid negative resist film 61 already exposed.
Have an energy of such an intensity that the photosensitive member is not exposed to light. At this time, the unexposed area 61b in the liquid negative resist film 61 is formed to be smaller than the unexposed area 62b in the film negative resist film 62.

Next, as shown in FIG. 4C, an unexposed area 61b in the liquid negative resist film 61 and an unexposed area 62b in the film negative resist film 62 due to development.
Is removed to form openings 61a and 62a. Openings 62a and 6 above
An opening 65 is formed by 1a, but since the opening 62a is smaller than the opening 61a, the cross-sectional shape of the opening 65 is an overhang shape.

 The following steps are the same as in the first embodiment.

According to the above-described embodiment, similarly to the first embodiment, it is possible to form a solder bump electrode larger than before, to prevent short-circuit failure due to foreign matter, and to shorten the interval between solder bump electrodes as compared with the conventional technique. It is possible to obtain the effect of being able to do so.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the gist of the invention.

For example, in the present embodiment, the present invention is applied to a DRAM provided with a bipolar transistor. However, the present invention is not limited to this, and a DRAM provided with a MISFET, an SRAM (static random access memory), Logical LSI
Etc. can be widely applied to semiconductor integrated circuit devices.

In the first embodiment, a film-like resist film is used as the upper resist film. However, the present invention is not limited to this, and a liquid resist film can be appropriately used.

Further, in Example 2, in order to expose only the upper film negative resist film without exposing the lower liquid negative resist film already exposed, light is attenuated in the film resist film while the lower liquid negative resist film is exposed. The light source energy is set to an appropriate intensity so that the resist film does not expose the resist film when it reaches the liquid resist film. However, the method is not necessarily limited to this method. Alternatively, a method may be employed in which the amount of the reaction initiator contained in the upper resist film is larger than the amount of the reaction initiator contained in the lower resist film. Further, the same effect can be obtained by changing the reaction wavelength of the upper resist film and the reaction wavelength of the lower resist film and using a light source corresponding to each reaction wavelength.

Further, in the present embodiment, as a method of removing the release layer, a method of decomposing and dissolving the release layer in a release liquid is adopted, but the method is not necessarily limited to this method, and the release layer may be mechanically removed. May be peeled off. In this case, it is necessary to weaken the bonding force between the release layer and the surface protective film in advance.

Further, in this embodiment, a negative resist is used as the peeling layer. However, the present invention is not limited to this, and a positive resist film may be used.

When the above positive resist film is employed in the second embodiment, it is not necessary to prevent the lower resist film from being exposed when exposing the upper resist film.

Further, in this embodiment, Pb and Sn were used as the metal layer, and the thickness ratio when the metal layer was deposited was set to 92: 8.However, the ratio is not necessarily limited to this ratio, and other ratios are appropriately used. can do.

In the above description, the case where the invention made by the present inventor is mainly applied to a solder bump electrode of a semiconductor integrated circuit device, which is a field of application as a background, has been described, but the present invention is not limited thereto. For example, it can be widely used for forming a wiring board on which electronic components are mounted. The present invention is applicable to at least a condition for forming a pattern made of a conductor on an insulator.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

That is, the first release layer is deposited on the surface of the semiconductor substrate,
A mask is placed on the first release layer and selectively exposed through the mask so as to form a first opening on the pattern formation region. Undesired dissolution such as the dissolution method does not proceed, and the first opening having a desired size can be formed.

Since the second opening in the upper layer is also formed in the same process, the amount of overhang on the first opening where the second opening is formed can be accurately determined in the opening having an overhanging cross-sectional shape. Also, depending on the thickness of the first release layer,
The height from the bottom surface of the opening to the overhang portion can be appropriately determined. For this reason, the height of the pattern forming metal layer can be increased, and there is an effect that a solder bump electrode larger than before can be formed.

Further, unlike the conventional case, the first openings are not connected with each other due to the progress of dissolution of the first release layer, and the short circuit between the patterns does not occur. Therefore, the interval between the openings can be reduced and the degree of integration can be increased.

Further, since the side wall of the opening is formed perpendicular to the substrate, the conductor is not deposited on the side wall of the opening when depositing the conductor, so that there is an effect that generation of foreign matter during deposition of the pattern forming metal layer can be prevented. .

Further, a third opening independent of the first opening is formed in the first release layer, and a film-like second release layer is attached on the third opening to form a cavity, Second
The release liquid that has entered through the opening decomposes the first release layer.
This has the effect of shortening the time required for dissolution. Especially the second
The effect is remarkable in a region where the openings are sparsely formed.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing the vicinity of a solder bump electrode obtained by applying an embodiment of the present invention to a memory LSI, FIG. 2 is a plan view of the memory LSI shown in FIG. 1, and FIGS. e) is a longitudinal sectional view sequentially showing an example of the manufacturing process of the solder bump electrode shown in FIG. 1, and FIGS. 4 (a) to 4 (c) show another example of the manufacturing process of the solder bump electrode shown in FIG. FIG. 2A: Semiconductor substrate, 4: Solder bump electrode, 41: Surface protective film, 50: BLM electrode, 51: Liquid negative resist film, 51a
… Opening, 51b …… Opening, 52 …… Film negative resist film, 52a …… Opening, 52b… Opening, 53 …… Release layer, 55…
... Opening, 56 ... Coating layer, 57 ... Electrode forming metal layer, 59 ...
... stripper, 61 ... cavity.

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Ikuo Yoshida 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (56) References JP-A-56-55950 (JP, A) JP-A-58 -125825 (JP, A) JP-A-61-245531 (JP, A) JP-A-57-192027 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/60, 21/30

Claims (3)

(57) [Claims] 1. A method for manufacturing a semiconductor integrated circuit device, comprising forming a pattern by depositing a conductor on an insulating film provided on a semiconductor substrate, the method comprising: forming a photosensitive first layer on the surface of the insulating film. A second step of exposing and developing the first release layer to form a first opening at a position corresponding to a region where the pattern is to be formed; and After the opening is formed, a third film-like release layer having photosensitivity is attached onto the first layer release layer.
And exposing and developing the second release layer to form a second opening smaller than the first opening over the first opening and to form a fourth opening at a position different from the second opening. A fourth step of forming a pattern by depositing a conductor on an insulating film through the first and second openings that are formed by overlapping. A method for manufacturing a semiconductor integrated circuit device. 2. The second step further comprises: exposing and developing the first release layer to a third layer larger than the fourth opening.
2. The method according to claim 1, further comprising a step of forming an opening, wherein the fourth step includes forming the fourth opening so as to overlap the third opening. 3. A method of manufacturing a semiconductor integrated circuit device, wherein a pattern is formed by depositing a conductor on an insulating film provided on a semiconductor substrate, wherein a photosensitive first layer negative resist is formed on the surface of the insulating film. A first step of forming a film; a second step of exposing and developing the first-layer negative resist film to form a first opening at a position corresponding to a region where the pattern is to be formed; After forming the first opening, a third step of attaching a photosensitive film-shaped second layer negative resist film on the first layer negative resist film; and forming the second layer negative resist film on the first layer. A fourth step of exposing and developing to form a second opening smaller than the first opening over the first opening and to form a fourth opening at a position different from the second opening; Conductive on the insulating film through the first and second openings formed The deposited manufacturing method of a semiconductor integrated circuit device which comprises a fifth step of forming the pattern.