JP2788639B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an external connection electrode.

(Prior art)

It is known to use a metal projection electrode as an external connection electrode of a semiconductor integrated circuit, and a lift-off method is used as a method for forming the metal projection electrode. This lift-off method forms a release layer such as a resist on an insulating film,
By a well-known exposure technique, a release layer in a conductive pattern forming region of, for example, aluminum is removed to form a conductive pattern on the entire surface.

Thereafter, the conductive layer on the release layer is selectively removed by removing the release layer in an organic solvent to form a desired conductor pattern.

There is also a method of removing the above-mentioned peeling layer by oxygen plasma etching instead of performing the operation in an organic solvent liquid.

In addition, as an example described about the lift-off process,
There is Japanese Patent Application No. 61-225981.

[Problems to be solved by the invention]

Separation of release layer in conventionally used organic solvent liquid
In the method of dissolving, the organic solvent penetrates only from the peripheral portion of the release layer, that is, the edge of the desired pattern, and decomposes and dissolves the release layer. Takes a long time, and consequently it takes a long time to complete the process. In particular, when the release layer surrounded by the desired pattern is large, it becomes extremely remarkable.

Even in the method of decomposing and dissolving the release layer using oxygen plasma etching, it is not possible to raise the processing temperature above the melting point of the conductor formed on the entire surface or the melting point of the base electrode metal of the metal bump electrode. No, as a result it still takes a long time.

In the step of decomposing and dissolving the release layer using an organic solvent, there is a method of applying vibration by ultrasonic waves in order to shorten the working time, but the device is liable to be damaged such as cracks.

Also, small pieces of the peeling layer or the coating layer peeled in the organic solvent liquid adhere as foreign matter to the gaps between the patterns formed on the insulating film, and easily remain after the cleaning step. In particular, the remaining metal foreign matter causes a short circuit failure between the conductor patterns.

Furthermore, the present inventor has found that the treatment using an organic solvent has a problem that equipment for improving a working environment such as exhaust / drainage treatment is required.

An object of the present invention is to provide a method of manufacturing a lift-off type semiconductor integrated circuit device which can shorten the processing time.

Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device that can prevent short circuit failure due to remaining foreign matter.

It is still another object of the present invention to provide a method for forming a metal bump electrode in a short time without using an organic solvent, and a method for manufacturing a semiconductor integrated circuit device having a metal bump electrode.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a release layer is formed in a region on an insulating film other than a region where a pattern is to be formed, a conductor is deposited on the release layer, and a coating layer is formed on the release layer, and the release layer does not exist. When the pattern is formed in the region, and then the peeling layer and the coating layer are peeled off from the insulating film to leave a required pattern on the insulating film, the peeling layer is formed on the surface of the insulating film. Forming a first photosensitive film for forming a layer; and exposing the first photosensitive film to form a first opening at a position corresponding to a region where the pattern is to be formed. , On the first photosensitive film,
Forming a second photosensitive film for forming a release layer; and exposing the second photosensitive film to form a second opening smaller than the first opening over the first opening. And the step of performing

Further, the means focused on the separation of the release layer and the coating layer, after the first opening and the second opening are formed, depositing a conductive layer from above, a coating layer on the release layer, A desired pattern is formed in a region where the release layer does not exist, and if necessary, after weakening the bonding force between the release layer and the insulating film, the release layer and the coating layer are mechanically formed. The desired pattern is peeled off from the insulating film and remains on the surface of the insulating film. In the above means, a film-shaped photosensitive film is used as the second photosensitive film for forming the release layer.

The step of weakening the bonding force between the release layer and the insulating film includes ultraviolet irradiation, exposure to air or a humidified atmosphere,
Cooling with a low-temperature liquid or the like can be employed.

[Action]

According to the above-mentioned means, the second opening smaller than the first opening.
The opening portion of the release layer formed by overlapping the openings is in an overhang state, whereby the conductive coating layer deposited on the release layer and the conductive layer deposited on the insulating film are formed. Patterns are separated from each other.

Further, regarding the peeling of the release layer and the coating layer, unlike the conventional method of decomposing and dissolving the release layer in an organic solvent solution to release the coating layer, the bonding force between the release layer and the insulating film is reduced. By mechanically peeling the two off to a certain extent, the time required for the method of manufacturing a semiconductor integrated circuit device of the lift-off type is reduced. Furthermore, since the peeling layer is removed without using an organic solvent, there is little possibility that foreign matter remains, and the occurrence of device cracks due to strong vibration is suppressed.

〔Example〕

FIG. 1 shows a bipolar transistor according to the present invention.
FIG. 1 is a longitudinal sectional view of an embodiment applied to a metal protruding electrode in a semiconductor integrated circuit incorporating a CMOS (mutual MOS) mixed type circuit.

In the bipolar transistor section of the present embodiment, for example, an N ⁺ -type buried layer 21 is provided on the surface of a P-type semiconductor substrate 20, and an epitaxial layer 22 of, for example, N-type silicon is provided on the buried layer 21. This epitaxial layer
A field insulating film 23 such as a silicon oxide film is provided on a required portion of the element 22, thereby performing isolation between elements and isolation within the element. This field insulating film 23
Below this, for example, a P ⁺ type channel stopper region 24 is provided. In the epitaxial layer 22 in a portion surrounded by the field insulating film 23, for example, a P-type intrinsic base region 25 and, for example, a P ⁺ -type graft base region 26 are provided. In the intrinsic base region 25, for example, An N ⁺ -type emitter region 27 is provided. Then, the emitter region 27, the intrinsic base region 25, the epitaxial layer 22 and the buried layer below the intrinsic base region 25 are formed.
The NPN type bipolar transistor is constituted by the collector region composed of 21. The NPN bipolar transistor is, for example, an ECL OR gate using a plurality of sets of resistors together with resistors (not shown).

Reference numeral 28 denotes an N-type collector extraction region connected to the buried layer 21, for example. Reference numeral 29 denotes an insulating film such as a silicon oxide film provided so as to be continuous with the field insulating film 23. The insulating film 29 includes the graft base region 26, the emitter region 27, and the collector extraction region. Contact holes corresponding to 28 respectively
29a to 29c are provided. A base extraction electrode 30 made of a polycrystalline silicon film is connected to the graft base region 26 through the contact hole 29a, and a polycrystalline silicon emitter electrode 31 is provided on the emitter region 27 through the contact hole 29b. I have. Here, 32 and 33 are insulating films such as silicon oxide films.

34a to 34b are first-layer wirings made of, for example, an aluminum film. Among them, the wiring 34a is connected to the base lead electrode 30 through a contact hole 33a provided in the insulating film 33.
The wiring 34b is connected to the polycrystalline silicon emitter electrode 31 through the contact hole 33b, and the wiring 34c is connected to the collector extraction region 28 through the contact hole 33c and the contact hole 29c. Reference numeral 35 denotes an interlayer insulating film including, for example, a nitride film, a spin-on-glass (SOG) film formed by plasma CVD, and a silicon oxide film formed by plasma CVD.

On the interlayer insulating film 35, second-layer wirings 36a and 36b made of, for example, an aluminum film are provided.
6a is a through hole provided in the interlayer insulating film 35.
It is connected to the wiring 34a through 35a. Reference numeral 37 denotes an interlayer insulating film similar to the interlayer insulating film 35. This interlayer insulating film
On the 37, third-layer wirings 38a to 38f made of, for example, an aluminum film are provided, among which the wiring 38a is connected to the wiring 36a through a through hole 37a provided in the interlayer insulating film 37, The wiring 38e is connected to the wiring 36b through the through hole 37b. Reference numeral 39 denotes an interlayer insulating film similar to the above-mentioned interlayer insulating films 35 and 37. On this interlayer insulating film 39, a fourth-layer wiring 40 made of, for example, an aluminum film is provided. The wiring 40 is configured to have a larger width and thickness than the lower wiring so that a large current can flow. 41 is, for example, a plasma CV
Plasma CVD as well as nitride film formed by D
Is a surface protection film made of silicon oxide formed by the method described above. The surface protection film 41 is provided with a through hole 41a, and a chromium (Cr) film 42 is provided on the wiring 40 through the through hole 41a. And this Cr
A projection electrode (bump) 4 made of, for example, lead (Pb) / tin (Sn) alloy-based solder is provided on the film 42 via, for example, a copper (Cu) / tin (Sn) -based intermetallic compound layer 43. I have.

Next, a manufacturing process of the metal bump electrode shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 2 (d).

As shown in FIG. 2A, a solder bump electrode base electrode 50 is formed at a required position on a surface protection film 41 on a semiconductor substrate 20 through a predetermined process.
M [Ball Limiting Metalization] electrode) has a three-layer structure of Au, Cu, and Cr from above. A methacrylic liquid resist film 51 of about 10 to 20 [μm] is applied on the surface protective film 41 so as to flatten the unevenness of the protective film. Remove with. Thus, an opening 51a is formed at a required position on the BLM electrode 50. Next, the liquid resist film 51
A methacrylic film-like resist film 52 (thickness 40
[Approximately [μm]), cured by heat or ultraviolet light, and then formed at an appropriate position on the BLM electrode 50 with an opening 52a having a smaller diameter than the opening 51a by using a well-known photosensitive technique. To the 50 side.

The opening 55 is formed by the opening 51a and the opening 52a. The liquid resist film 51 and the film-like resist film 52 constitute a release layer 53.

In FIG. 2, circuit elements, wirings, and the like formed below the surface protective film 41 are omitted.

Next, as shown in FIG. 2 (b), lead (P
b) and tin (Sn) are sequentially deposited so that the thickness ratio becomes, for example, 92: 8. However, since the diameter of the surface opening 52a of the peeling layer 53 is smaller than the diameter of the bottom opening 51a, the above-mentioned opening is formed. A so-called overhang such as an overhang is formed on the inner peripheral edge of 55, and is intentionally shaped to deteriorate step coverage. Thus, the coating layer 56 deposited on the release layer 53 and the bump metal layer 57 deposited on the BLM electrode 50
Are separated from each other.

Further, by irradiating the entire surface with ultraviolet rays, the bonding force between the release layer 53 and the surface protective film 41 is weakened. At this time, if the area 60 where the covering layer 56 does not exist is formed in a required portion on the release layer 53, the bonding force can be weakened more effectively.

Next, after fixing the substrate, an adhesive tape 58 is attached to the entire surface as shown in FIG.
Only the covering layer 56 on 53 adheres to the tape. By pulling the pressure-sensitive adhesive tape 58 in a direction away from the substrate surface, the release layer 53 and the coating layer 56 can be simultaneously released from the surface protective film. In this case, the adhesive strength between the release layer 53, the coating layer 56, and the surface protective film needs to be smaller than the adhesive strength between the adhesive tape 58 and the coating layer 56.

Thus, only the bump metal layer 57 deposited on the BLM electrode 50 can be left on the surface.

Subsequently, as shown in FIG. 2 (d), Pb and Sn of the bump metal layer 57 are melted by a heat treatment at, for example, about 350 ° C. to form a spherical solder bump electrode 4. At this time, the above BLM
The Au layer on the surface of the electrode 50 is absorbed by Pb and diffused.
The lower Cu layer reacts with Sn to form an intermetallic compound, and the lowermost layer of Cr forms a barrier metal that prevents the solder forming the solder bump electrode and the aluminum forming the wiring layer from reacting and diffusing. Work as

According to the above embodiment, the following effects can be obtained.

(1) After a release layer 53 made of a resist material is deposited on the surface protective film 41 in a region other than the BLM electrode formation region, a solder layer serving as a coating layer 56 is formed on the release layer 53, and the release layer In a region where no bump metal layer 57 is present, a solder layer for forming the bump metal layer 57 is deposited so as to be separated from each other, and after the bonding force between the peeling layer 53 and the surface protective film 41 is weakened by ultraviolet irradiation, the peeling layer 53 is formed. In order to mechanically peel off the coating layer 56 from the surface protective film 41 and leave the solder layer forming the bump electrode 4, the coating layer is decomposed and dissolved in a conventional organic solvent liquid to dissolve the coating layer. As compared with the method of peeling off, the working time is remarkably reduced, and adhesion of foreign matter from the peeling layer can be prevented.

(2) Unlike the conventional method, the present embodiment does not use an organic solvent liquid, so that the adverse effect on the working environment is reduced and the ultrasonic vibration required for increasing the reaction speed in the solution is required. And cracks in the device can be prevented.

[Embodiment 2] FIG. 3 is a vertical cross-sectional view showing a manufacturing process of a metal bump electrode according to another embodiment of the present invention, and shows the difference between this embodiment and the embodiment shown in FIG. The difference is that after forming the release layer, BLM
That is, to form electrodes.

Note that the same members as those in the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 3, through holes are opened at required positions on the wiring layer located below the surface protection film 41, and a methacrylic liquid resist film 51 is coated on the surface protection film 41 by 10 to 20.
[Μm] is applied, and the resist in a region where the metal bump electrode is to be formed is removed by using a known photosensitive technique. Thus, an opening 51a is formed at a required position on the through hole.
Next, a methacrylic film-like resist film 52 (about 40 [μm] in thickness) is adhered on the liquid resist film 51 and cured by heat or ultraviolet light. An opening 52a having a smaller diameter than the opening 51a is formed by using a photosensitive technique, and an inner peripheral edge of the opening 52a protrudes toward the 50 side. The opening 55 is formed by the opening 51a and the opening 52a. The liquid resist film 51 and a film-like resist film
52 constitutes the release layer 53. Next, C over the entire pellet surface
r, Cu, and Au are sequentially deposited to form the BLM electrode 50 in the opening 55.
The Au layer 61 is formed. Further, Pb and Sn are changed to a thickness ratio of 9
Deposit sequentially to make 2: 8. The following steps are performed in Example 1.
Is the same as

 It should be noted that wirings and through holes are omitted in this drawing.

According to the above embodiment, in addition to the effects of the first embodiment, a release layer
Since the 53 also serves as a mask for forming the BLM electrode 50 and the bump metal layer 57, the process can be shortened, and further, the BLM electrode 50 and the bump metal layer 57 can be formed without displacement.

Embodiment 3 FIG. 4 is a longitudinal sectional view showing a manufacturing process of a metal bump electrode according to another embodiment of the present invention, which is shown in FIG. 2 and FIG. 3 and FIG. The difference from the embodiment is the step of removing the release layer. Note that the same members as those in the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

After completion of the step shown in FIG. 2 (b), the whole is immersed in an ultra-low temperature liquid 70 such as liquid nitrogen, and the release layer is naturally released from the surface protective film.

This utilizes the property that the adhesive strength between the release layer and the surface protective film becomes extremely weak when the temperature is lowered.

According to the above embodiment, the following operation and effect can be obtained as in the first and second embodiments.

(1) Since the step of weakening the adhesive strength between the peeling layer and the surface protective film and the step of peeling both are the same, the working time is further reduced.

(2) The adverse effect on the working environment due to the organic solvent is reduced, and the need for ultrasonic vibration is eliminated, so that the occurrence of cracks in the device can be prevented. The invention made by the present inventors has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, in this embodiment, the material of the release layer is a combination of a liquid resist and a film-like resist film. However, the material is not limited to this. Only the liquid resist film, only the film-like resist film, or another resist film is used. Can be appropriately adopted.

Further, in the first embodiment, ultraviolet irradiation is performed as a method of weakening the bonding force between the peeling layer and the surface protective film. However, the method is not limited to this. Alternatively, a method of cooling in a liquid, a method of decomposing and dissolving the release layer with a chemical solution, and then performing the above treatment, or the like can be appropriately adopted.

Further, in Example 1, an adhesive tape was used to mechanically peel the release layer from the surface protective film. However, the present invention is not limited to this, and a force is applied to the release layer such as an adhesive roller or a vacuum chuck. Other methods for obtaining can be appropriately adopted.

Further, in the first embodiment, the thickness ratio of Pb and Sn forming the bump metal layer is set to 92: 8. However, the present invention is not necessarily limited to this, and other ratios can be appropriately used.

In the above description, the case where the invention made by the present inventor is mainly applied to the metal projecting electrode of the semiconductor integrated circuit which is the background of the application has been described, but the present invention is not limited thereto. For example, it can be widely used for forming various patterns such as other electrodes and wiring layers. The present invention is applicable to at least a condition for forming a pattern made of a conductor on an insulator.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

That is, the opening portion of the release layer formed by stacking the second openings smaller than the first opening is in an overhang state, whereby the conductive coating layer deposited on the release layer and The conductive pattern deposited on the insulating film can be separated from each other.

Regarding the peeling of the release layer and the coating layer, a release layer is deposited in a region other than the pattern formation region on the insulator, and then a conductive layer is deposited thereon, and the coating layer is formed on the release layer. And, in a region where the release layer does not exist, a desired pattern is formed respectively, and after the bonding force between the release layer and the insulating film is weakened, the release layer and the coating layer are mechanically removed from the insulating film. Since the desired pattern is left on the surface of the insulator by peeling, the working time is remarkably shortened as compared with the conventional method of decomposing and dissolving the peeling layer in an organic solvent solution, and the effect of preventing foreign matter from remaining can be prevented. There is.

In addition, since no organic solvent liquid is used, the adverse effect on the working environment is reduced, and the need for ultrasonic vibration required to increase the reaction speed in the solution is eliminated,
This has the effect of preventing the occurrence of cracks in the device.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing the vicinity of a metal bump electrode formed by applying an embodiment of the present invention in a semiconductor integrated circuit. FIGS. 2 (a) to 2 (d) show an example of a manufacturing process of the above metal bump electrode. 3 is a longitudinal sectional view showing a manufacturing process of another embodiment of the present invention, and FIG. 4 is a longitudinal sectional view showing a manufacturing process of another embodiment of the present invention. . 4 ... solder bump electrode, 41 ... surface protective film, 42 ... Cr film,
43 ... Cu, Sn based intermetallic compound, 50 ... BLM electrode, 51 ... Liquid resist film, 51a ... Opening, 52 ... Film resist film, 52a ... Opening, 53 ... Release layer, 55 ... … Opening, 56
… Coating layer, 57… Bump metal layer, 58… Adhesive tape.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tetsuya Hayashida 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (56) References JP-A-56-55950 (JP, A) JP-A-58 JP-A-125825 (JP, A) JP-A-53-47773 (JP, A) JP-A-55-59718 (JP, A) JP-A-58-31528 (JP, A) (58) Fields investigated (Int. . ^6, DB name) H01L 21/60 H01L 21/027 - 21/033 H01L 21/30

Claims (7)

(57) [Claims] 1. A method for manufacturing a semiconductor integrated circuit device, comprising forming a pattern by depositing a conductor on an insulating film provided on a semiconductor substrate, wherein a first photosensitive film is formed on the surface of the insulating film. A first step, a second step of exposing the first photosensitive film to form a first opening at a position corresponding to a region where the pattern is to be formed; A third step of attaching a film-shaped second photosensitive film thereon, exposing the second photosensitive film, and overlaying a second opening smaller than the first opening on the first opening. A fourth step of forming, and a fifth step of forming the pattern by depositing the conductor on an insulating film through the first and second openings that are formed in an overlapping manner.
And a method for manufacturing a semiconductor integrated circuit device. 2. A method of manufacturing a semiconductor integrated circuit device, wherein a pattern is formed by depositing a conductor on an insulating film provided on a semiconductor substrate, wherein a release layer is formed in a region other than a region where the pattern is to be formed. A first step of forming, and a second step of depositing a conductor on the release layer after the formation of the release layer, forming a coating layer on the release layer, and forming the pattern in a region where the release layer does not exist. And a third step of separating the release layer and the coating layer from the insulating film to leave the pattern on the insulating film. The first step includes forming a release layer on the surface of the insulating film. Forming a first photosensitive film, exposing the first photosensitive film to form a first opening at a position corresponding to a region where the pattern is to be formed, A filter for forming a release layer on the photosensitive film Lum-shaped second
Bonding the second photosensitive film to the first photosensitive film and exposing the second photosensitive film to a second opening smaller than the first opening.
Forming a semiconductor integrated circuit device over the opening. 3. The semiconductor according to claim 2, wherein the third step is a step of applying a pulling force to the coating layer via an adhesive to remove the release layer and the coating layer. A method for manufacturing an integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said third step is a step of mechanically separating said release layer together with said coating layer from said insulating film. 5. The semiconductor integrated circuit according to claim 4, wherein in the third step, a tensile force greater than a bonding force between the insulating film and the release layer acts on the coating layer via the adhesive. A method for manufacturing a circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said third step includes a step of weakening a bonding force between said peeling layer and said insulating film. 7. The step of weakening the bonding force includes the steps of:
7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the method is one step selected from exposure to the air or a humidified atmosphere, and cooling in a low-temperature atmosphere or a low-temperature liquid.