JP2760602B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2760602B2 JP2760602B2 JP1269474A JP26947489A JP2760602B2 JP 2760602 B2 JP2760602 B2 JP 2760602B2 JP 1269474 A JP1269474 A JP 1269474A JP 26947489 A JP26947489 A JP 26947489A JP 2760602 B2 JP2760602 B2 JP 2760602B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- type
- semiconductor
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は結晶系半導体による背面電界型光電変換素子
等の半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device such as a back surface photoelectric conversion element using a crystalline semiconductor.
（ロ）従来の技術 従来の単結晶または多結晶シリコン等を基体とする背
面電界（BSF）型光電変換素子の製造方法につき簡単に
説明する。例えば、n+p-p+構造の場合、p-型の単結晶シ
リコンウエハからなる基体に拡散またはイオン注入等に
よりn+層を形成する。そして、イオン注入による場合、
ｎ型ドーパントを基体にイオン注入し、800℃〜1000℃
の熱アニール工程で、pn接合を形成する。(B) Conventional technology A brief description will be given of a conventional method for manufacturing a back surface electric field (BSF) type photoelectric conversion element using single crystal or polycrystalline silicon as a base. For example, in the case of an n + p - p + structure, an n + layer is formed on a base made of a p - type single crystal silicon wafer by diffusion or ion implantation. And in the case of ion implantation,
Ion implantation of an n-type dopant into the substrate, 800 ° C to 1000 ° C
A pn junction is formed in the thermal annealing step.
また、拡散法では、基体を拡散炉内で1000℃程度の高
温に加熱した状態に保持し、拡散炉内へ所望の気体ドー
パントを導入し、基体表面よりドーパントを拡散し、基
体両面にn+層が形成される。その後、n+層の片側をエッ
チングにより除去し、n+p-接合が形成される。Further, in the diffusion method, the substrate is kept heated at a high temperature of about 1000 ° C. in a diffusion furnace, a desired gaseous dopant is introduced into the diffusion furnace, the dopant is diffused from the substrate surface, and n + A layer is formed. Thereafter, one side of the n + layer is removed by etching, forming an n + p - junction.
続いて、裏面側のp+層として、Al蒸着し、熱処理を行
いAlをp-層の裏面側より拡散させ、p+層を形成するかま
たはイオン注入によりｐ型ドーパントを注入後、前述と
同様の工程を行なってp+層を形成するか、あるいは、液
相成長法により形成する。液相成長法は、あらかじめ、
ｐ型ドーパントを高濃度に含んだシリコン材料を溶解し
た金属融液中よりp+シリコン層を基体p-層裏面にエピタ
キシャル成長させる。このような手法によってn+p-p+構
造のBSF型光電変換素子が形成されていた。Subsequently, as a p + layer on the back side, Al is vapor-deposited, heat treatment is performed to diffuse Al from the back side of the p − layer, and ap + layer is formed or a p-type dopant is implanted by ion implantation. A p + layer is formed by performing a similar process, or is formed by a liquid phase growth method. In the liquid phase growth method,
A p + silicon layer is epitaxially grown on the back surface of the base p − layer from a metal melt in which a silicon material containing a high concentration of a p-type dopant is dissolved. A BSF-type photoelectric conversion element having an n + p - p + structure was formed by such a method.
（ハ）発明が解決しようとする課題 前述した製造方法において、イオン注入を用いる場
合、n+層形成においては、イオン注入後、更に高温熱処
理を必要として、工程が煩雑で製造コストが高くなる。
しかも、イオン注入のための装置を必要とするが、斯か
る装置は高価である等の難点がある。(C) Problems to be Solved by the Invention In the above-described manufacturing method, when ion implantation is used, in the formation of the n + layer, a high-temperature heat treatment is required after the ion implantation, which complicates the process and increases the manufacturing cost.
In addition, a device for ion implantation is required, but such a device has disadvantages such as being expensive.
一方、拡散によるものは、熱拡散後、裏面エッチング
が必要であると共に、高温熱処理過程におけるオートド
ーピングの問題があった。更に、前述した如く、n+層を
形成後、改めてp+層を形成する工程を必要とするなど、
その製造工程が煩雑であり、製造コストが高くなること
は否めない。On the other hand, the diffusion method requires etching of the back surface after thermal diffusion, and also has a problem of autodoping in a high-temperature heat treatment process. Further, as described above, after the formation of the n + layer, a step of forming the p + layer again is required,
It is undeniable that the manufacturing process is complicated and the manufacturing cost increases.
本発明は上述した問題点を解消すべくなされたものに
して、製造工程を省略し、製造コストを大幅に低減でき
る製造方法を提供することをその課題とする。An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a manufacturing method which can omit a manufacturing process and greatly reduce a manufacturing cost.
（ニ）課題を解決するための手段 本発明の製造方法はn+p-p+又はp+n-n+接合を形成する
際、一導電型の前記半導体基体の一面上に、逆導電型の
非晶質半導体層を形成した後、前記半導体基体の他面上
に液相成長により前記基体と同一導電型で且つ高濃度に
ドープされた結晶半導体層をエピタキシャル成長により
形成するとともに、前記非晶質半導体層を固相成長によ
り結晶化させることを特徴とする。(D) Means for Solving the Problems In the production method of the present invention, when an n + p - p + or p + n - n + junction is formed, a reverse conductivity type is formed on one surface of the semiconductor substrate of one conductivity type. After the amorphous semiconductor layer is formed, a crystalline semiconductor layer of the same conductivity type as that of the substrate and highly doped is formed on the other surface of the semiconductor substrate by liquid phase epitaxy, and the amorphous The crystalline semiconductor layer is crystallized by solid phase growth.
（ホ）作用 本発明法によれば、高濃度半導体層の形成と同時に非
晶質半導体層の結晶化を行なうことができ、接合形成
と、高濃度半導体層の形成が同一プロセスで行なえる。
従って、高熱処理工程を減らすプロセスが低温化する。
また、任意の深さの接合が得ることができる。(E) Function According to the method of the present invention, the amorphous semiconductor layer can be crystallized simultaneously with the formation of the high-concentration semiconductor layer, and the formation of the junction and the formation of the high-concentration semiconductor layer can be performed in the same process.
Therefore, the temperature of the process for reducing the number of the high heat treatment steps is reduced.
Further, a junction having an arbitrary depth can be obtained.
（ヘ）実施例 以下、本発明の一実施例を図面に従い説明する。(F) Embodiment One embodiment of the present invention will be described below with reference to the drawings.
第１図（イ）は一導電型の半導体基体上に逆導電型の
非晶質半導体層を形成した状態を示す断面図、第１図
（ロ）は本発明により形成されたBSF型光電変換素子を
示す断面図である。FIG. 1 (a) is a cross-sectional view showing a state in which an amorphous semiconductor layer of the opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and FIG. 1 (b) is a BSF type photoelectric conversion formed according to the present invention. It is sectional drawing which shows an element.
まず、第１図（イ）に示すように、半導体基体（１）
としてp-型シリコン（Si）ウエハを用い第１表に示す形
成条件で、基体（１）の一面上に膜厚１μｍのn+型非晶
質シリコン層（２）を形成する。First, as shown in FIG. 1 (a), a semiconductor substrate (1)
A p - type silicon (Si) wafer is used as an example and under the formation conditions shown in Table 1, an n + type amorphous silicon layer (2) having a thickness of 1 μm is formed on one surface of the base (1).
尚、基体（１）の比抵抗は10Ωcm、厚みは200μであ
る。The substrate (1) has a specific resistance of 10 Ωcm and a thickness of 200 μm.
続いて、非晶質シリコン層（２）が形成された基体
（１）の一面とは反対側の基体（１）の他面上に第２表
に示す条件で基体（１）と同導電型のp+型シリコン層
（３）を液層成長させる。この液相成長と同時にn+型非
晶質シリコン層（２）を固相結晶化させn+型結晶または
多結晶半導体薄膜からなる結晶系シリコン層（２′）を
成長させる。Subsequently, on the other surface of the substrate (1) opposite to the one surface of the substrate (1) on which the amorphous silicon layer (2) is formed, the same conductivity type as that of the substrate (1) is applied under the conditions shown in Table 2. The p + type silicon layer (3) is grown in a liquid layer. Simultaneously with the liquid phase growth, the n + -type amorphous silicon layer (2) is solid-phase crystallized to grow a crystalline silicon layer (2 ′) composed of an n + -type crystal or a polycrystalline semiconductor thin film.
すなわち、第２表で示すように、この時のプロセスの
条件（温度、雰囲気、ガス、圧力時間）を、非晶質シリ
コン層（２）の固相成長の最適条件に設定することで、
液相成長プロセス中に非晶質シリコン層（２）を結晶ま
たは多結晶半導体薄膜に成長させることができ、任意の
深さのPN接合が同時に形成される。That is, as shown in Table 2, by setting the process conditions (temperature, atmosphere, gas, pressure time) at this time to the optimum conditions for the solid phase growth of the amorphous silicon layer (2),
During the liquid phase growth process, the amorphous silicon layer (2) can be grown on a crystalline or polycrystalline semiconductor thin film, and a PN junction of any depth is formed simultaneously.
尚、固相結晶化のシリコン層（２′）及びp+型シリコ
ン層（３）の不純物濃度は１×1017cm-3以上とした。The impurity concentration of the solid-phase crystallized silicon layer (2 ') and the p + -type silicon layer (3) was set to 1 × 10 17 cm −3 or more.
このように、n+p-p+構造を形成した後、AuGaからなる
裏面電極（４）およびAlからなる表面串型電極（５）を
形成し、ARコーティング（６）を行なって、BSF型光電
変換素子が形成される。 After forming the n + p - p + structure in this way, a back electrode (4) made of AuGa and a surface skewer electrode (5) made of Al are formed, and AR coating (6) is performed to form a BSF-type electrode. A photoelectric conversion element is formed.
従来のイオン注入などでは１μｍ程度までの浅い接合
しかできず、光電変換素子の特性に制限を加えていたが
本発明法により形成された光電変換素子は、任意の深さ
の接合形成ができるため、良好な特性が得られる。Conventional ion implantation and the like can form only a shallow junction of about 1 μm, which limits the characteristics of the photoelectric conversion element. However, the photoelectric conversion element formed by the method of the present invention can form a junction of an arbitrary depth. And good characteristics can be obtained.
次に、比較のため上述した本発明により製造したBSF
型光電変換素子と従来法によりn+p-p+構造のBSF型光電
変換素子を形成し（第２図参照）、両者の特性を比較し
た結果を第４表に示す。Next, the BSF produced according to the present invention described above for comparison.
A BSF type photoelectric conversion element having an n + p - p + structure was formed by a conventional method and an N + p - p + structure according to a conventional method (see FIG. 2).
尚、従来法はn+型シリコン層として第３表に示す条件
により拡散法により形成したｎ型拡散シリコン層（2
1）、p+型シリコン層（３）は本実施例と同様に第２表
に示す条件で液相成長法により形成した。Incidentally, the conventional method is n-type diffusion silicon layer formed by the diffusion method by the conditions shown in Table 3 as the n + type silicon layer (2
1) The p + type silicon layer (3) was formed by the liquid phase growth method under the conditions shown in Table 2 in the same manner as in the present example.
尚使用した基体（１）はp-型シリコンウエハで比抵抗
10Ωcm、厚みは200μｍである。The substrate (1) used was a p - type silicon wafer with specific resistance
The thickness is 10 Ωcm and the thickness is 200 μm.
第４表から明らかな如く、本発明法による光電変換素
子が各特性において従来のものに比べて向上しているこ
とが判かる。 As is clear from Table 4, the photoelectric conversion element according to the method of the present invention is improved in each characteristic as compared with the conventional one.
尚、本実施例においては、基体（１）としてシリコン
ウエハを用いたが、これ以外にゲルマニウム（Ge）、シ
リコンゲルマニウム（SiGe）等を用いても良い。In this embodiment, a silicon wafer is used as the substrate (1), but germanium (Ge), silicon germanium (SiGe), or the like may be used instead.
また、本実施例における結晶化n+型シリコン層
（２′）をn+SiGe、n+SiCで構成しても良い。Further, the crystallized n + -type silicon layer (2 ′) in this embodiment may be made of n + SiGe or n + SiC.
更に、本実施例ではn+p-p+構造について説明したが同
時にp+n-n+構造についても適用できる。Further, in this embodiment, the n + p - p + structure has been described, but the present invention can be applied to the p + n - n + structure.
（ト）発明の効果 以上説明したように、本発明法によれば、高濃度半導
体層の形成と接合形成とを、非晶質半導体層形成後の高
濃度半導体層の固相形成で同時に行なえるため、高温処
理工程を減らし、プロセスの低温化が図れ、製造が容易
になる。更に任意の深さの接合を得ることができるの
で、半導体装置の特性の向上が図れる。(G) Effects of the Invention As described above, according to the method of the present invention, the formation of the high-concentration semiconductor layer and the formation of the junction can be performed simultaneously by the solid-phase formation of the high-concentration semiconductor layer after the formation of the amorphous semiconductor layer. Therefore, the number of high-temperature processing steps can be reduced, the temperature of the process can be reduced, and the production becomes easy. Further, since a junction having an arbitrary depth can be obtained, the characteristics of the semiconductor device can be improved.
第１図は本発明法を適用するBSF型光電変換素子を示
し、第１図（イ）は基体上に非晶質半導体層を形成した
状態を示す断面図、第１図（ロ）は本発明法により形成
されたBSF型光電変換素子を示す断面図である。 第２図は従来法により形成されたBSF型光電変換素子を
示す断面図である。FIG. 1 shows a BSF type photoelectric conversion element to which the method of the present invention is applied, FIG. 1 (a) is a cross-sectional view showing a state in which an amorphous semiconductor layer is formed on a substrate, and FIG. It is sectional drawing which shows the BSF type photoelectric conversion element formed by the invention method. FIG. 2 is a sectional view showing a BSF type photoelectric conversion element formed by a conventional method.
フロントページの続き (56)参考文献 特開 昭64−89568（ＪＰ，Ａ) 特開 昭63−196082（ＪＰ，Ａ) 特開 昭63−152177（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 31/04 - 31/078Continuation of front page (56) References JP-A-64-89568 (JP, A) JP-A-63-196082 (JP, A) JP-A-63-152177 (JP, A) (58) Fields investigated (Int) .Cl. 6 , DB name) H01L 31/04-31/078
Claims (1)
いた半導体装置の製造方法であって、n+p-p+又はp+n-n+
接合を形成する際、一導電型の前記半導体基体の一面上
に、逆導電型の非晶質半導体層を形成した後、前記半導
体基体の他面上に液相成長法により前記基体と同一導電
型で且つ高濃度にドープされた結晶半導体層をエピタキ
シャル成長により形成すると共に、前記非晶質半導体層
を固相成長により結晶化させることを特徴とする半導体
装置の製造方法。1. A method for manufacturing a semiconductor device using a single-crystal semiconductor or a polycrystalline semiconductor substrate, comprising: n + p - p + or p + n - n +
When forming a junction, after forming an amorphous semiconductor layer of the opposite conductivity type on one surface of the semiconductor substrate of one conductivity type, the same conductivity as the substrate is formed on the other surface of the semiconductor substrate by a liquid phase growth method. A method for manufacturing a semiconductor device, comprising: forming a crystalline semiconductor layer doped with high concentration at a high concentration by epitaxial growth; and crystallizing the amorphous semiconductor layer by solid phase growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1269474A JP2760602B2 (en) | 1989-10-17 | 1989-10-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1269474A JP2760602B2 (en) | 1989-10-17 | 1989-10-17 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03131070A JPH03131070A (en) | 1991-06-04 |
| JP2760602B2 true JP2760602B2 (en) | 1998-06-04 |
Family
ID=17472946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1269474A Expired - Fee Related JP2760602B2 (en) | 1989-10-17 | 1989-10-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2760602B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2109147A1 (en) * | 2008-04-08 | 2009-10-14 | FOM Institute for Atomic and Molueculair Physics | Photovoltaic cell with surface plasmon resonance generating nano-structures |
| JP2014056677A (en) * | 2012-09-11 | 2014-03-27 | Panasonic Corp | Manufacturing method of electron source |
| KR101674523B1 (en) * | 2015-03-20 | 2016-11-09 | 주식회사 케이티앤지 | Beam irradiation type lighter |
-
1989
- 1989-10-17 JP JP1269474A patent/JP2760602B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03131070A (en) | 1991-06-04 |
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