JP2755063B2 - Transmission error detection system for digital information - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data transmission error detection system.

[0002]

2. Description of the Related Art A conventional example will be described with reference to the drawings.

Referring to FIG. 3 showing a conventional example, this digital information transmission error detecting system includes a transmitting unit 10b for transmitting input digital information, a receiving unit 20b for receiving a signal transmitted by the transmitting unit 10b, and a transmitting unit. 10b and a transmission path 30b connecting the receiving unit 20b. Transmission unit 10
b denotes a parity generation circuit 2 for generating parity bits for error checking from the input digital information, and a transmission buffer 21 for temporarily storing the difference between the processing speed of the parity bits from the parity generation circuit 2 and the processing speed of the input digital information. And The receiving unit 20b temporarily stores the parity bit and the input digital information transmitted from the transmitting unit 10b through the transmission path 30b to compensate for the difference in transmission speed between the parity bit and the input digital information. And a parity error detection circuit 3 that outputs a parity error detection signal 12 when detecting an error. When the logical value of the information is “0”, the signal level of the transmission line is “L” (low potential)
And the signal level is “H” when the logical value is “1”.
(High potential). The parity is odd, and the signal level of the parity bit is set such that the sum of the number of bits of the signal level “H” for the 8 information bits and the parity bit is odd.

The 8-bit input digital information DIN0 to DIN7 input to the transmission unit 10b is transmitted as information bits to the reception unit 20b through the transmission buffer 21. At the same time, the input information DIN0 to DIN7 is input to the parity generation circuit 2. The parity generation circuit 2 generates an odd parity of these bits, and uses the parity as parity bits to transmit the odd parity through the transmission buffer 21 and the transmission path 30b.
0b.

[0005] The information bits input to the receiving section 20b through the transmission path 30b are output as output signals DOT0 to DOT7 through the receiving buffer 22 and input to the parity error check circuit 3. The parity bit input to the receiving unit 20 b is also input to the parity error check circuit 3 through the reception buffer 22. The parity error check circuit 3 compares the value of the odd parity based on the input information bits and the value of the input parity bits, and outputs a parity error detection signal 12 if they are different.

[0006]

As described above, in the conventional digital information transmission error detection system, when the same logical value (for example, "0") continues for a certain information bit, the signal level is kept at a constant value (for example, "0"). "L"). For this reason,
When an error occurs in which the signal level is forcibly fixed on the transmission line, the error cannot be detected if the fixed value is the same as the fixed value ("L").

[0007]

In the digital information transmission error detecting system according to the present invention, each of the digital information has a binary level, and the input digital information in units of a plurality of bits which are inputted in parallel is inverted at predetermined timing. A first means, a second means for transmitting a timing control signal for setting the predetermined timing, and a binary level in response to digital information of level inversion and level non-inversion from the first means A transmission means for transmitting the level-inverted and non-level-inverted digital information, the parity bits and the timing control signal to a transmission path in parallel; and Checking a parity error based on the digital information and the parity bit received through the transmission path;
And receiving means for restoring the digital information of the level inversion in response to the timing control signal received through the transmission line.

The transmitting means includes a sixth means for temporarily storing the digital information of the level inversion and the level non-inversion, the parity bit, and the timing control signal for temporarily compensating for a difference in processing speed. A seventh means is provided for temporarily storing the digital information of the level inversion and the level non-inversion transmitted from the transmission means, the parity bit, and the timing control signal to compensate for a difference in transmission speed.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, a transmitting unit 10a for transmitting input digital information, a receiving unit 20a for receiving a signal transmitted by the transmitting unit 10a, a transmitting unit 10a and a receiving unit 20a Transmission line 30a connecting
And The transmission unit 10a includes a signal level inverting circuit 1a for inverting the level of input digital information in units of a plurality of bits, each of which takes a binary level and is input in parallel at predetermined timings, and a timing control for setting predetermined timings A timing control circuit 6 for transmitting the signal 11, a parity generation circuit 2 for generating one of two levels of parity bits according to the digital information of the level inversion and the level non-inversion from the signal level inversion circuit 1a, A transmission buffer 4 for temporarily storing the difference between the processing speed of the bit, the input digital information and the timing control signal 11; The reception unit 20a temporarily stores the parity bit, the input digital information, and the transmission speed of the timing control signal 11 transmitted from the transmission unit 10a to compensate for the difference between the transmission speed and the digital information and parity bit from the reception buffer 5. A parity error check circuit 3 that outputs a parity error detection signal 12 when a parity error is detected based on a parity error based on the parity control signal and a timing control signal 11 that receives level-inverted digital information through a transmission path 30a and a reception buffer 5. And a signal level inverting circuit 1b for restoring in response to the The parity is an odd number, and the parity bit and the signal level are set so that the sum of the number of bits whose signal level is “H” (high potential) is odd for the information bit and the parity bit.

Next, the operation of the transmitting section 10a will be described. 8-bit input information DIN0 to DIN0 input to the transmission unit 10a
DIN7 is input to the signal level inverting circuit 1a. The signal level inverting circuit 1a switches the selector (not shown) according to the timing control signal 11 and switches the input information DIN.
Each time 0 to DIN7 is input, the input information DIN0 to DIN0
Inversion and non-inversion are alternately performed on DIN7 through an inverter (not shown) and transmitted as transmission signals DS0 to DS7. When the signal levels of the input information DIN0 to DIN7 are "L" (low potential), the output signal level of the signal level inversion circuit 1a is "L" when not inverted and "H" when inverted. When the signal levels of the input information DIN0 to DIN7 are "H", the output signal level of the signal level inversion circuit 1a is "H" when not inverted and "L" when inverted.

The transmission signal DS0 of the signal level inversion circuit 1a
DS7 are transmitted as information bits to the receiving unit 20a via the transmission buffer 4. At the same time, the output of the signal level inversion circuit 1a is input to the parity generation circuit 2. The parity generation circuit 2 creates an odd parity of these bits, and transmits the odd parity to the receiving unit 20a via the transmission buffer 4 as a parity bit transmission signal DSP. Further, the timing control circuit 6 transmits the timing control signal 11 to the receiving unit 20a via the transmission buffer 4.

Next, the operation of the receiving section 20a will be described. The transmission signal DS which is the information bit input to the receiving unit 20a
The signals 0 to DS7 are input to the signal level inversion circuit 1b and the parity error check circuit 3 via the reception buffer 5 as reception signals DR0 to DR7. Transmission signal DSP input simultaneously with transmission signals DS0 to DS7 as parity bits
Is input to the parity error check circuit 3 via the reception buffer 5 as a reception signal DRP. On the other hand, the timing control signal 11 is input to the signal level inversion circuit 1b via the reception buffer 5.

The signal level inverting circuit 1b of the transmitting section 10a responds to the input information bits DR0 to DR7 in accordance with the timing control signal 11.
The signal level is inverted / non-inverted in synchronization with a to obtain output information DOT0 to DOT7. In other words, the signal level inverting circuits 1a and 1b of the transmitting unit 10a and the receiving unit 20a are synchronously inverted / non-inverted, so that the signal levels are restored and the output information DOT0 to DOT7 are input information DOT.
It becomes the same as IN0 to DIN7. On the other hand, the parity error check circuit 3 outputs an odd parity based on the information bits of the input received signals DR0 to DR7 and the input received signal D
The parity bits of the RP are compared, and if they are different, a parity error detection signal 12 is output.

FIG. 2 shows a specific example of error detection. Section Ta
From 1 to Ta8, the input digital information logical value “00” (1
(In hexadecimal notation) input information DIN0 to DIN7 are input. In the sections Ta1, Ta3, Ta5 and Ta7, the signal level inversion circuit 1a is in a non-inversion state. Section Ta
2, Ta4, Ta6 and Ta8 are in an inverted state,
As a result, the signal levels of all bits of the transmission signals DS0 to DS7 and DSP are “H”. In the sections Ta5 to Ta8, an error occurs in which the signal level of the least significant bit is forcibly fixed to “L” on the transmission line 30a.
As a result, the signal level of the reception signal DR0 changes to “L”, and changes to the output digital information logical value “01” (hexadecimal notation). As a result, the receiving unit 20a detects a parity error at Ta6 and Ta8 at the time of inversion.

Next, in the section Tb1 to Tb2, the input information D of the input digital information logical value "FF" (hexadecimal notation)
IN0 to DIN7 are input. This time, section Tb5
From Tb8 to Tb8, an error occurs in which the signal level of the least significant bit is forcibly fixed to “H” on the transmission line 30a.
As a result, the signal level of the reception signal DR0 changes to “H” and changes to the output digital information logical value “FE” (hexadecimal notation). As a result, the receiver 20a detects a parity error at Tb6 and Tb8 at the time of inversion.

As described above, according to the present invention, a signal level inverting circuit for inverting input digital information in units of a plurality of bits, each of which takes a binary level and which is input in parallel, at predetermined timings, is provided. A timing control circuit for transmitting a timing control signal for setting a predetermined timing, and generating one of binary parity bits according to digital information of level inversion and level non-inversion from a signal level inversion circuit A parity generation circuit, a parity check circuit for checking a parity error based on digital information and parity bits received through the transmission path, and a timing control signal received through the transmission path for level-inverted digital information. Receiving means having a signal level inverting circuit for restoring in response to , It can detect the transmission error even when the error signal level is forced secured in the transmission path has occurred.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of error detection in the embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1a, 1b Signal level inversion circuit 2 Parity generation circuit 3 Parity error check circuit 4 Transmission buffer 5 Reception buffer 6 Timing control circuit 10a Transmission unit 11 Timing control signal 12 Parity error detection signal 20a Receiving unit 30a Transmission line DIN0 to DIN7 Input information DOT0 ~ DOT7 output information DS0 ~ DS7, DSP transmission signal DR0 ~ DR7, DRP reception signal

Claims (2)

(57) [Claims] 1. A first means for inverting the level of input digital information in units of a plurality of bits, each of which takes a binary level and is input in parallel, at predetermined timings, and a timing for setting the predetermined timings A second means for transmitting a control signal; and a third means for generating either a binary level parity bit in accordance with the level-inverted and level-inverted digital information from the first means. Transmitting means for transmitting the level-inverted and level-non-inverted digital information, the parity bit, and the timing control signal to a transmission path in parallel; and based on the digital information and the parity bit received through the transmission path. Fourth means for checking a parity error by using the digital information of the level inversion. Receiving means having a fifth means for restoring in response to an imaging control signal; and a transmission error detection system for digital information. 2. The transmitting means comprises sixth means for compensating for a difference in processing speed between the level-inverted and non-level-inverted digital information, the parity bit, and the timing control signal. 7. A transmission error of digital information, comprising: a seventh means for compensating a difference in transmission speed between the level-inverted and non-level-inverted digital information, the parity bit, and the timing control signal transmitted from the means. Detection system.