JP2752544B2 - Virtual memory address space access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual memory address space access control method for controlling access to a virtual memory address space in a multiple virtual memory system, and more particularly, to high-speed address conversion from a virtual address to a real address. The present invention relates to a virtual memory address space access control method which is enabled.

In a conventional multiple virtual memory system, only access to data in an address space specified by a control register is permitted. In order to refer to data in a plurality of address spaces, the data in the control register cannot be accessed. Although the contents had to be replaced, the contents of this control register were replaced under the control of the operating system, so that the user program could execute data processing that directly spans multiple address spaces. Did not.

[0003] Against this background, recently, a multiple virtual memory system of a new architecture has been put to practical use, which enables an access register to directly access data in an extremely large number of address spaces from a user program. ing. When implementing this multiple virtual storage system, the segment table required for address translation can be accessed at high speed,
It is necessary to take measures to enable high-speed address conversion processing from a virtual address to a real address.

[0004]

2. Description of the Related Art In a new multiple virtual storage system using an access register, as shown in FIG. 6, an access register number (correlated with a base register number).
Of the access register accessed by ALE (ALE
T), the corresponding data of the access list is specified, and the corresponding data of the specified access list is used in the segment table specifier (abbreviated as STD in the figure) managed by the ASN second table. One segment table specifier is specified, and the address conversion from the virtual address to the real address by the dynamic address conversion mechanism is performed by using the segment table specified by the specified segment table specifier. ing.

In this configuration, the user program is:
For example, by loading ALET for the entries of 16 access registers provided, it becomes possible to access an access list having a capacity of 1K or 4K, thereby selecting an extremely large number of segment table specifiers. This makes it possible to use a large-capacity multi-virtual storage that has never been available before. In addition, separately from this, the first control register (C
Two address spaces are prepared: a primary space specified by a segment table specifier managed by R1) and a secondary space specified by a segment table specifier managed by the seventh control register (CR7).

In this multiple virtual storage system, since a segment table specifier is obtained by sequentially accessing a plurality of tables, it takes time to obtain a segment table specifier. There is a problem. Therefore, by providing an access register conversion index buffer mechanism (referred to as an ALB) for executing the conversion from the ALET to the segment table specifier at a high speed, the required segment table specifier can be obtained at a high speed. The configuration is adopted.

However, in the access method using the ALB, first, an ALET is read from the access register according to a given access register number, and then a segment table specifier is read from the ALB according to the ALET. , It takes too much time to obtain the required segment table specifier. This problem is further exacerbated by the fact that it cannot be arranged in the main part of the CPU because the hardware amount of the ALB is large.

Accordingly, the present applicant has filed Japanese Patent Application No. Hei 1-192267 (JP-A-3-57046 / Title of Invention: Virtual memory address space access control system) filed on July 25, 1999.
A conversion index register (hereinafter, referred to as SA) for performing high-speed conversion from an access register number to a segment table designator
R: sometimes referred to as a shadow access register), so that a required segment table specifier can be obtained at high speed.

That is, a conversion index register for managing the correspondence between the access register number and the segment table specifier is prepared, and when the system is initialized or a purge command is issued, the conversion index register is associated with the management data. When a valid bit corresponding to the access register number indicates invalid data when an access register number is given by adopting a configuration in which the valid bit to be
If the segment table specifier obtained by indexing the LB does not hit the ALB, the segment table specifier obtained by the above-described access register → access list → ASN second table conversion route is registered and validated, and this segment The configuration is such that a table designator is provided to the dynamic address translation mechanism. When the valid bit corresponding to the access register number indicates valid data when the access register number is given, it is necessary to immediately provide the associated segment table specifier to the dynamic address translation mechanism. The invention disclosed is such that the segment table specifier to be obtained can be obtained at high speed.

Hereinafter, for convenience of explanation, the process of specifying a segment table specifier by a conversion route of ALET → access list → ASN second table will be referred to as an AR conversion process, and a mechanism for executing the AR conversion process will be referred to as an AR conversion mechanism. .

In a multiple virtual storage system having such a configuration, a CPYA (Copy Access) instruction is prepared as a data transfer instruction between entries of an access register. This CPYA instruction has the following format: CPYA x, y where x is the copy destination access register number and y is the copy source access register number, and is the ALE managed by the entry of the access register indicated by the copy source access register number.
This is an instruction requesting that T be copied to the entry of the access register indicated by the copy destination access register number.

Conventionally, when this CPYA instruction is issued, the ALET of the entry of the copy destination access register is different from the previous one, so the entry data of the conversion index register indicated by the copy destination access register number is used. It was processing to invalidate.

[0013]

SUMMARY OF THE INVENTION However, CPY
When the A instruction is issued, there is a high possibility that the entry data of the access register specified by the source operand as the copy source has recently been used, and the entry data of the access register specified by the target operand as the copy destination Is likely to be used soon.

However, as in the prior art, when the CPYA instruction is issued, the entry data of the conversion index register indicated by the base register number of the target operand is invalidated. When the entry data of the access register specified by the operand is used, no hit occurs in the conversion index register.
Since the execution of the R conversion is started, it takes time until the segment table specifier is obtained.

From now on, according to the prior art, CP
After the YA instruction is issued, there is a problem that the address conversion from the virtual address to the real address cannot be executed at high speed.

The present invention has been made in view of the above circumstances, and is directed to a data processing apparatus for performing access control of a virtual memory address space according to an AR conversion mechanism and a conversion index register, in which a CPYA instruction is issued. In some cases, it is an object of the present invention to provide a new virtual memory address space access control method that enables high-speed address conversion from a virtual address to a real address.

[0017]

FIG. 1 shows the principle configuration of the present invention. In the figure, reference numeral 1 denotes a data processing device equipped with the present invention, which includes an access register 10 and a conversion mechanism 11.
, Translation index register 12 and dynamic address translation mechanism 1
3; a CPYA instruction issuing unit 14; a SAR data registration unit 15; and an AR data copying unit 16.

The access register 10 manages the correspondence between the access register number and the ALET, and outputs the corresponding ALET when the access request source gives the access register number associated with the base register number. Works as follows. The conversion mechanism 11 uses the above-described AR
An ALE provided from the access register 10 which is constituted by a conversion mechanism alone or by adding the above-mentioned ALB to the conversion mechanism.
It operates to specify the segment table specifier specified by T. The conversion index register 12 stores the conversion mechanism 11
Manages the correspondence between the access register number and the segment table specifier specified by, and outputs the corresponding segment table specifier when the access register number is given from the access request source. When there is no valid segment table specifier in the conversion index register 12, the conversion mechanism 11 operates.

The dynamic address translation mechanism 13 operates to execute the address translation from the virtual address to the real address by using the translation look-up register 12 or the segment table specified by the segment table designator obtained by the translation mechanism 11. . The CPYA instruction issuing unit 14 operates to issue a CPYA instruction requesting execution of management data copying between entries of the access register 10.
The SAR data registration unit 15 operates to execute a process of registering management data in the conversion index register 12. When the CPYA instruction issuing unit 14 issues the CPYA instruction, the AR data copying unit 16 operates to copy the management data between the entries of the access register 10 specified by the CPYA instruction.

[0020]

According to the present invention, when the CPYA instruction issuing unit 14 specifies a source and destination access register number and issues a CPYA instruction requesting execution of management data copying between entries of the access register 10, The SAR data registration unit 15 stores the segment table specifier managed in the entry of the conversion index register 12 indicated by the copy source access register number of the CPYA instruction in the entry of the conversion index register 12 indicated by the copy destination access register number of the CPYA instruction. Process to copy to.

As described above, according to the present invention, when the management data (ALET) is copied between the entries of the access register 10 according to the issuance of the CPYA instruction,
Since the management data (segment table specifier) is configured to be copied between corresponding entries of the conversion index register 12, the CPYA instruction is issued after the CPYA instruction is issued. When the entry data of the access register specified by the target operand is used, the desired segment table specifier can be obtained immediately according to the conversion index register 12, and the address conversion from the virtual address to the real address can be executed at high speed. You can do it.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 2 shows a system configuration of a multiple virtual storage system to which the present invention is applied. In the figure, as described with reference to FIG. 1, reference numeral 10 denotes an access register, reference numeral 12 denotes a translation index register, and reference numeral 13 denotes a dynamic address translation mechanism. FIG.
However, as shown in this figure, the conversion index register 12 manages the valid / invalid of the registered segment table specifier according to the valid bit. Although not shown, a TLB is provided corresponding to the dynamic address translation mechanism 13. Reference numeral 11a denotes an AR conversion mechanism corresponding to the conversion mechanism 11 of FIG. The AR conversion mechanism 11a receives the ALET given from the access register 10, the ALDSO information for indirectly displaying the expanded area of the access list, and the domain ID information, and receives the ALET described in FIG.
By executing the conversion process of the conversion route of the ASN second table, processing is performed so as to specify the segment table specifier. Although not shown, this AR conversion mechanism 11
ALB will be provided corresponding to a.

FIG. 3 shows a signal relationship between the conversion index register 12 and the SAR data registration unit 15 described with reference to FIG. 1 for executing management data registration processing of the conversion index register 12.

As shown in FIG. 3, the conversion index register 12 manages a segment table specifier accessed by an access register number and a valid bit indicating validity / invalidity of the segment specifier. When the access register number of the read request is given from the request source, and the segment table specifier associated with the access register number is valid data, the segment table specifier is notified to the TLB so that the virtual address is obtained from the virtual address. It operates to realize high-speed address conversion to a real address.

The SAR data registration unit 15 executes a process of registering the management data of the conversion index register 12, and implements the access register 1 in order to realize the present invention.
C prepared as a data transfer instruction between 0 entries
When the PYA instruction is issued, it operates to execute the registration processing characteristic of the present invention. Next, the registration process executed by the SAR data registration unit 15 will be described in detail with reference to the explanatory diagram of the registration process of the SAR data registration unit 15 shown in FIG.

The SAR data registration unit 15 obtains the correspondence between the access register number and the segment table designator by executing the AR conversion by the AR conversion mechanism 11a. AR by CPYA = 0
, The segment table specifier “STD” obtained by the AR conversion mechanism 11a for the entry of the conversion index register 12 indicated by the access register number (represented by i = 1 in FIG. 4). _ART ", and the valid bit of the entry is set to" 1 "to register that the data is valid data. When the CPYA instruction is issued, “Set AR by CPYA = 1,
However, as shown in the column of “AR conversion = 0”, the CPYA instruction specifies an entry of the conversion index register 12 indicated by the copy destination access register number (indicated by i = 1 in FIG. 4) in the CPYA instruction. The segment table specifier "STD _SRC " managed in the entry of the conversion index register 12 indicated by the copy source access register number specified by the instruction is registered, and the valid bit of the entry is set to "1" to indicate valid data. Register that thing.

On the other hand, when the AR conversion mechanism 11a does not execute the AR conversion, the SAR data
When no instruction is issued, “AR conversion = 0,
SetAR by CPYA = 0 as shown in the column "no do not want to perform the registration processing for converting the index register 12.

In this way, as shown in FIG. 5, the SAR data registration unit 15 of the present invention, when the management data (ALET) is copied between the entries of the access register 10 according to the issuance of the CPYA instruction, Processing is performed so that the management data (segment table specifier) is copied between corresponding entries of the conversion index register 12.

[0029]

As described above, according to the present invention,
In connection with the issuance of the CPYA instruction,
When the entry data of the access register specified by the target operand of the instruction is used, a desired segment table specifier can be obtained immediately according to the conversion index register. As a result, even after the CPYA instruction is issued, the address conversion from the virtual address to the real address can be executed at high speed.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a system configuration diagram of a multiple virtual storage system to which the present invention is applied;

FIG. 3 is an explanatory diagram of a peripheral mechanism of a conversion index register.

FIG. 4 is an explanatory diagram of a registration process executed by a SAR data registration unit.

FIG. 5 is an explanatory diagram of the processing of the present invention.

FIG. 6 is an explanatory diagram of address control of a multiple virtual storage system to which the present invention is applied.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data processing device 10 access register 11 conversion mechanism 12 conversion index register 13 dynamic address conversion mechanism 14 CPYA instruction issuing section 15 SAR data registration section 16 AR data copying section

Claims (1)

(57) [Claims] 1. A and conversion mechanism code values or al segment table designator to specific that manages the access register accessed by the access register number, access register number and segment table designator specified by the conversion mechanism in the data processing device and a conversion index register to manage the correspondence between the instruction to copy the code values managed by the access registers
When a copy instruction to be issued is issued,
Access specified by the copy source access register number
The code value managed in the register entry is
-Indicates the copy destination access register number specified by the instruction
First copy for copying to the entry of the access register
And the first copying unit performs the copying process.
The above conversion index register indicated by the source access register number
The segment table specifier managed in the entry of
The conversion index record indicated by the copy destination access register number
A second copying unit for copying to the register entry.
And a virtual memory address space access control method.