JP2790556B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a data processing device for executing access control of the virtual memory address space in a multi-virtual storage system, in particular, data allowing perform address translation to a real address at high speed from the virtual address
The present invention relates to a processing device .

In a conventional multiple virtual memory system, only access to data in an address space specified by a control register is permitted. In order to refer to data in a plurality of address spaces, the data in the control register cannot be accessed. Although the contents had to be replaced, the contents of this control register were replaced under the control of the operating system, so that the user program could execute data processing that directly spans multiple address spaces. Did not.

[0003] Against this background, recently, a multiple virtual memory system of a new architecture has been put to practical use, which enables an access register to directly access data in an extremely large number of address spaces from a user program. ing. When implementing this multiple virtual storage system, the segment table required for address translation can be accessed at high speed,
It is necessary to take measures to enable high-speed address conversion processing from a virtual address to a real address.

[0004]

2. Description of the Related Art In a new multiple virtual storage system using an access register, as shown in FIG. 6, an access register number (correlated with a base register number).
Of the access register accessed by ALE (ALE
T), the corresponding data of the access list is specified, and the corresponding data of the specified access list is used in the segment table specifier (abbreviated as STD in the figure) managed by the ASN second table. One segment table specifier is specified, and the address conversion from the virtual address to the real address by the dynamic address conversion mechanism is performed by using the segment table specified by the specified segment table specifier. ing.

In this configuration, the user program is:
For example, by loading ALET for the entries of 16 access registers provided, it becomes possible to access an access list having a capacity of 1K or 4K, thereby selecting an extremely large number of segment table specifiers. This makes it possible to use a large-capacity multi-virtual storage that has never been available before. In addition, separately from this, the first control register (C
Two address spaces are prepared: a primary space specified by a segment table specifier managed by R1) and a secondary space specified by a segment table specifier managed by the seventh control register (CR7).

In this multiple virtual storage system, since a segment table specifier is obtained by sequentially accessing a plurality of tables, it takes time to obtain a segment table specifier. There is a problem. Therefore, by providing an access register conversion index buffer mechanism (referred to as an ALB) for executing the conversion from the ALET to the segment table specifier at a high speed, the required segment table specifier can be obtained at a high speed. The configuration is adopted.

However, in the access method using the ALB, first, an ALET is read from the access register according to a given access register number, and then a segment table specifier is read from the ALB according to the ALET. , It takes too much time to obtain the required segment table specifier. This problem is further exacerbated by the fact that it cannot be arranged in the main part of the CPU because the hardware amount of the ALB is large.

Accordingly, the present applicant has filed Japanese Patent Application No. Hei 1-192267 (JP-A-3-57046 / Title of Invention: Virtual memory address space access control system) filed on July 25, 1999.
A conversion index register (hereinafter, referred to as SA) for performing high-speed conversion from an access register number to a segment table designator
R: sometimes referred to as a shadow access register), so that a required segment table specifier can be obtained at high speed.

That is, a conversion index register for managing the correspondence between the access register number and the segment table specifier is prepared, and when the system is initialized or a purge command is issued, the conversion index register is associated with the management data. When a valid bit corresponding to the access register number indicates invalid data when an access register number is given by adopting a configuration in which the valid bit to be
If the segment table specifier obtained by indexing the LB does not hit the ALB, the segment table specifier obtained by the above-described access register → access list → ASN second table conversion route is registered and validated, and this segment The configuration is such that a table designator is provided to the dynamic address translation mechanism. When the valid bit corresponding to the access register number indicates valid data when the access register number is given, it is necessary to immediately provide the associated segment table specifier to the dynamic address translation mechanism. The invention disclosed is such that the segment table specifier to be obtained can be obtained at high speed.

Hereinafter, for convenience of explanation, the process of specifying a segment table specifier by a conversion route of ALET → access list → ASN second table will be referred to as an AR conversion process, and a mechanism for executing the AR conversion process will be referred to as an AR conversion mechanism. .

In the multiple virtual memory system having such a configuration, a SAR (Set AR) instruction, a LAM (Load Access Multiple) instruction, or the like is prepared as a load instruction for setting an ALET for an access register. ing. This LAM instruction is designated as a load destination by using a description format of LAM h, i, j (k) where h: load start access register number i: load end access register number j: offset value k: base register. The main memory data from the address position defined by the sum of the offset value j and the contents of the base register k is loaded into each entry of the access register indicated by the range of the access register numbers h to i. This is an instruction requesting that On the other hand, the SAR instruction is an instruction for requesting that an entry of an access register indicated by a specified access register number be loaded with data stored in a specified general-purpose register.

Conventionally, when a load instruction such as the SAR instruction or the LAM instruction requesting that an ALET be set for an access register is issued, the ALET of the entry of the access register to be loaded is set to the previous ALET. Therefore, the entry data in the conversion index register indicated by the access register number of the load destination is invalidated.

[0013]

However, when a load instruction requesting that an ALET be set for an access register is issued, the entry data of the access register at the load destination can be used immediately. The nature is also high.

However, as in the prior art, when such an instruction is issued, if the entry data of the conversion index register pointed to by the access register number of the load destination is invalidated, the processing becomes When the entry data of the access register specified by the access register number is used, a hit does not occur in the conversion index register, and the execution of the ALB index or the execution of the AR conversion results in the segment table specifier being obtained. It will take some time before it can be done.

Thus, according to the prior art, there is a problem that the address conversion from the virtual address to the real address cannot be executed at high speed after the issuance of the ALET setting request instruction to the access register.

The present invention was made in view of such circumstances, a configuration that perform access control of the virtual memory address space according to the conversion index register AR conversion mechanism
At the time of adoption, even when a load instruction requesting to set an ALET for an access register such as a SAR instruction or a LAM instruction is issued, the address conversion from the virtual address to the real address is performed. It is an object of the present invention to provide a new data processing device capable of executing at high speed.

[0017]

FIG. 1 shows the principle configuration of the present invention. In the figure, reference numeral 1 denotes a data processing device equipped with the present invention, which includes an access register 10 and a conversion mechanism 11.
, Translation index register 12 and dynamic address translation mechanism 1
3, an AR load instruction issuing unit 14, an SAR data registration unit 15, and an AR data registration unit 16.

The access register 10 manages the correspondence between the access register number and the ALET, and outputs the corresponding ALET when the access request source gives the access register number associated with the base register number. Works as follows. The conversion mechanism 11 uses the above-described AR
An ALE provided from the access register 10 which is constituted by a conversion mechanism alone or by adding the above-mentioned ALB to the conversion mechanism.
It operates to specify the segment table specifier specified by T. The conversion index register 12 stores the conversion mechanism 11
Manages the correspondence between the access register number and the segment table specifier specified by, and outputs the corresponding segment table specifier when the access register number is given from the access request source. When there is no valid segment table specifier in the conversion index register 12, the conversion mechanism 11 operates.

The dynamic address translation mechanism 13 operates to execute the address translation from the virtual address to the real address by using the translation look-up register 12 or the segment table specified by the segment table designator obtained by the translation mechanism 11. . The AR load instruction issuing unit 14 operates to issue an AR load instruction requesting execution of data loading of a specified location / designated area to an entry / entry area of the designated access register 10. SA
The R data registration unit 15 operates to execute a process of registering management data in the conversion index register 12. When the AR load instruction issuing unit 14 issues the AR load instruction, the AR data registration unit 16 loads the load data specified by the AR load instruction into the entry of the access register 10 specified by the AR load instruction. Works as follows.

[0020]

According to the present invention, when the AR load instruction issuing unit issues an AR load instruction by designating a specified location / designated area of a load source and an access register number / number range of a load destination, the SAR data registration unit 15 When the load data to be loaded into the access register 10 for the entry of the conversion index register 12 indicated by the load destination access register number is an ALET value that specifies the segment table specifier of the primary space, When the segment table specifier is loaded and the ALET value is to designate the segment table specifier in the secondary space, processing is performed to load the segment table specifier in the secondary space.

As described above, according to the present invention, the access register 10 designated according to the issuance of the AR load instruction.
When the ALET value is loaded into the load destination entry, the corresponding segment table specifier is also loaded into the corresponding entry of the conversion index register 12. Therefore, when the entry data of the access register specified by the AR load instruction is used after the issuance of the AR load instruction, a desired segment table specifier can be obtained immediately according to the conversion index register 12. As a result, address conversion from a virtual address to a real address can be executed at high speed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 2 shows a system configuration of a multiple virtual storage system to which the present invention is applied. In the figure, as described with reference to FIG. 1, reference numeral 10 denotes an access register, reference numeral 12 denotes a translation index register, and reference numeral 13 denotes a dynamic address translation mechanism. FIG.
However, as shown in this figure, the conversion index register 12 manages the valid / invalid of the registered segment table specifier according to the valid bit. Although not shown, a TLB is provided corresponding to the dynamic address translation mechanism 13. Reference numeral 11a denotes an AR conversion mechanism corresponding to the conversion mechanism 11 of FIG. The AR conversion mechanism 11a receives the ALET given from the access register 10, the ALDSO information for indirectly displaying the expanded area of the access list, and the domain ID information, and receives the ALET described in FIG.
By executing the conversion process of the conversion route of the ASN second table, processing is performed so as to specify the segment table specifier. Although not shown, this AR conversion mechanism 11
ALB will be provided corresponding to a.

FIG. 3 shows a signal relationship between the conversion index register 12 and the SAR data registration unit 15 described with reference to FIG. 1 for executing management data registration processing of the conversion index register 12.

As shown in FIG. 3, the conversion index register 12 manages a segment table specifier accessed by an access register number and a valid bit indicating validity / invalidity of the segment specifier. When the access register number of the read request is given from the request source, and the segment table specifier associated with the access register number is valid data, the segment table specifier is notified to the TLB so that the virtual address is obtained from the virtual address. It operates to realize high-speed address conversion to a real address.

The SAR data registration unit 15 executes a process of registering the management data of the conversion index register 12, and implements the access register 1 in order to realize the present invention.
AR load instructions such as a LAM instruction for requesting loading of main storage data into an entry area of a load destination of 0, and a SAR instruction requesting loading of storage data of a general-purpose register for an entry of a load destination of the access register 10 When the is issued, it operates to execute the registration process characteristic of the present invention. Next, the SAR data registration unit 15 will be described with reference to FIG.
The registration process executed by the data registration unit 15 will be described in detail. Here, FIG. 4 assumes that a LAM instruction is issued as an AR load instruction.

The SAR data registration unit 15 obtains the correspondence between the access register number and the segment table designator by executing the AR conversion by the AR conversion mechanism 11a. AR by LAM = 0 "
As shown in the column of (1), the segment table specifier "STD _ART " obtained by the AR conversion mechanism 11a is entered into the entry of the conversion index register 12 indicated by the access register number (in FIG. 4, represented by i = 1). Is registered, and the valid bit of the entry is set to "1" to register that the data is valid data.

When the LAM instruction is issued, "Set AR by LAM = 1, where AR conversion = 0" in FIG.
As shown in the column of FIG. 4, each entry of the conversion index register 12 indicated by the load destination access register number range specified by the LAM instruction (represented by i = 1 in FIG. 4) is stored in the corresponding access register 10. When the ALET value from the main memory loaded to the entry is “00 to 00”, the segment table specifier “STD” of the primary space managed by the first control register (CR1)
_CR1 ”is registered, and the loaded ALET value is“ 00-0 ”.
If it is "1", the segment table specifier "STD _CR7 " of the secondary space managed by the seventh control register (CR7) is registered, and the valid bits of those entries are set to "1" to be valid. Register that it is data and AL to be loaded
If the ET value is a value other than “00-00” and “00-01”, the valid bit of the entry of the conversion index register 12 indicated by the load destination access register number is dropped to “0” so that the data becomes invalid data. Set to.

On the other hand, when the AR conversion mechanism 11a does not execute the AR conversion and when the LAM instruction is not issued, the SAR data registration unit 15 reads “AR conversion = 0, Se in FIG.
As shown in the column t ARby LAM = 0 ", no do not want to perform the registration processing for converting the index register 12.

As described above, the SAR data registration unit 15 of the present invention stores the load destination entry of the access register 10 in accordance with the issuance of the AR load instruction such as the LAM instruction or the SAR instruction as shown in FIG. Primary space /
When loading an ALET value that will specify the secondary space segment table specifier,
Processing is performed so that the corresponding entry of the conversion index register 12 is loaded with the corresponding segment table specifier of the primary space / secondary space.

[0030]

As described above, according to the present invention,
In connection with issuance of an AR load instruction such as a LAM instruction or a SAR instruction, when the entry data of the access register specified by the AR load instruction is subsequently used,
According to the conversion index register 12, the desired segment table specifier can be obtained immediately. From now on, AR
Even after the issuance of the load instruction, the address conversion from the virtual address to the real address can be executed at high speed.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a system configuration diagram of a multiple virtual storage system to which the present invention is applied;

FIG. 3 is an explanatory diagram of a peripheral mechanism of a conversion index register.

FIG. 4 is an explanatory diagram of a registration process executed by a SAR data registration unit.

FIG. 5 is an explanatory diagram of the processing of the present invention.

FIG. 6 is an explanatory diagram of address control of a multiple virtual storage system to which the present invention is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data processing apparatus 10 Access register 11 Conversion mechanism 12 Conversion index register 13 Dynamic address conversion mechanism 14 CPYA instruction issuing unit 15 SAR data registration unit 16 AR data registration unit

Claims (2)

(57) [Claims] 1. A conversion mechanism for specifying a segment table specifier from a code value managed by an access register accessed by an access register number, and a correspondence between the access register number specified by the conversion mechanism and the segment table specifier. And a conversion index register that manages a data type. When a load instruction is issued to the access register to load data indicating a space type stored in a specified location, the load instruction A first registration unit that loads the data with respect to an entry of the access register indicated by the specified load destination access register number ;
The data loaded in the access register is primary empty
To indicate the interval, the load destination access register number
The conversion index register entry pointed to by
Load the segment table specifier in the Imari space and
When indicating the Candary space, the access destination
The conversion index register entry pointed to by the
The secondary space segment table specifier
The primary space and the secondary space.
Otherwise, the load destination access register number
Second invalidate entries of the translation lookaside register pointing
And a registration unit . 2. A conversion mechanism for specifying a segment table specifier from a code value managed by an access register accessed by an access register number, and a correspondence between the access register number specified by the conversion mechanism and the segment table specifier. And a conversion index register that manages a data type. When a load instruction is issued to the access register to load data indicating a space type stored in a specified area, the load instruction for each entry in the access register pointed to load destination access register number range specified, when the first registration unit to load the data, the first registration unit performs the load process, the
Access register within load destination access register number range
For each data number, specify the load destination access register number
The data loaded into the access register is the primary
When indicating the space, the load destination access register number
The entry in the conversion index register pointed to by the
Load the primary space segment table specifier,
When indicating the secondary space, access to the above load destination
In the entry of the above conversion index register indicated by the register number,
On the other hand, the segment table specifier
Load, both primary and secondary space
If not shown, the above load destination access register number
The data processing apparatus further comprising a second registration unit you invalidate entries of the translation lookaside register, characterized pointed.