JPH06259329A - Information processor equipped with address converting function - Google Patents

Abstract

PURPOSE:To decrease the miss rate of a TLB without increasing the cost of a system by providing the TLB on a memory for the external memory of a processor and using signal pins and a control circuit, which are necessary for an external TLB, for the external cache memory in common. CONSTITUTION:The information processor which has primary TLBs 102 and 103, and primary cache memories 104, 105, 106, and 107 in a CPU 100 and a main storage 125 and external high-speed memories 130 and 131 outside the CPU 100, and the external high-speed memory 131 is used while divided into a secondary cache memory 122 for operands, a secondary cache memory 123 for instructions, and a secondary TLB 124. Index addresses for accessing the high-speed memories 130 and 131 are generated by an index address generating circuit 113 which inputs a logical address LADDR, a physical address PADDR, an SCM select signal 250, and an STLB select signal 240.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which employs a virtual memory system.

[0002]

2. Description of the Related Art Conventionally, in order to access information stored in a main memory at a higher speed, a cache memory or a TLB (Translation Lookas) is used.
A high-speed memory such as an "idebuffer" is used. However, since a high speed memory is expensive, increasing the capacity causes a high cost. Therefore, IPSJ Journal V
ol. 27 No. 6 p. As shown in 582 to 592, it is an effective method to combine a high-speed and expensive memory with a low-cost but low-speed memory to form a hierarchical memory system. This is a known method.

A description will be given with reference to FIG. FIG. 2 shows an information processing apparatus having a three-level memory structure of a primary cache memory 2, a secondary cache memory 3, and a main memory 4. The primary cache memory 2 is the central processing unit 1.
It is a high-speed and small-capacity cache memory provided in the (CPU1). In addition, the secondary cache memory 3
It is a cache memory that is slower and has a larger capacity than the primary cache memory 2 provided outside the CPU 1, generates an address in the external high speed memory index address generation circuit 5, and is accessed via the bus 6. Further, the main storage device 4 is accessed via the bus 7.

CPU 1 in the primary cache memory 2, secondary cache memory 3 and main memory 4
From t1, t2, t3
In general, these magnitude relationships are expressed by the following equation.

[0005]

## EQU00001 ## t1 <t2 <t3 (Equation 1) In the information processing device that does not access the secondary cache memory when the primary cache memory hits, the hit ratio of the primary cache memory with respect to the number of memory accesses, the secondary cache memory The average memory access time T1 required to access the information stored in the hierarchical memory from the CPU 1 is given by the following equation, where P1 and P2 are the hit ratios.

[0006]

## EQU00002 ## T1 = P1.times.t1 + P2.times.t2 + (1-P1-P2) .times.t3 (Equation 2) If the hit rate of the cache memory becomes high, the rate of directly accessing the main memory device decreases. Therefore, according to the memory hierarchization method, the average memory access time T1 of the CPU 1 is reduced, and high-speed access is possible.

On the other hand, the TLB 8 shown in FIG. 2 is a high-speed memory for storing address conversion information used for high-speed generation of a physical address used for accessing the main memory device, and is often used in today's information processing devices. It is a known technique. When the target address translation information does not exist in the TLB, a process of reading the address translation information managed by the operating system from the main storage device is performed. Therefore, generally, when a TLB is missed, the time required for address conversion is large, and in a computer system such as a large-scale computer or a server, as shown in Japanese Patent Application Laid-Open No. 3-218546, the TLB is hierarchized. In some cases, the technique may be applied to reduce the TLB miss rate.

[0008]

Generally, when the software is executed, the average data access time T required to access the information in the main memory is equal to the average address translation time required for the address translation. , Is expressed as the sum of the times when the hierarchical memory is actually accessed, and can be calculated by the following formula.

[0009]

T = T1 + {Q1 × t4 + (1−Q1) × t5} (Equation 3) T1 is the average memory access time, t4 is the TLB access time, and t5 is the address translation time when the TLB is missed. , Q1 indicate the TLB hit rate with respect to the number of memory accesses.

Nowadays, with the expansion of the virtual space and the amount of data, the sizes of the TLB and the cache memory are increasing in order to satisfy the demand for the speeding up of the information processing apparatus. However, a low-cost information processing apparatus can have only a small capacity of a high-speed and expensive memory built in the processor. It is also a fact that this is one of the causes of lowering the hit rate and increasing the average data access time.

The above-mentioned Japanese Laid-Open Patent Publication No. 3-218546 describes that not only the secondary cache memory but also the secondary TLB is provided, which avoids a decrease in hit rate and an increase in average data access time. The performance may be improved simply, but with that alone, the number of signal pins for the secondary TLB, high-speed memory and secondary TL required on the CPU side
This leads to an increase in the B control circuit, which complicates the device and increases the cost of the CPU and the entire information processing device.

Therefore, the present invention provides a secondary TL in an information processing device having a secondary cache memory as an external high speed memory.
By configuring the signal pin required for B to share the control circuit with that for the secondary cache memory, the secondary TLB is realized with a simple configuration without increasing the cost. The purpose is to improve performance.

[0013]

In order to solve the above-mentioned problems, the present invention requires the logic for generating the index address of the external high speed memory to generate the index address for the secondary TLB. Logical address, secondary cache memory in external high speed memory and secondary T
A signal for selecting LB is provided as an input signal. Further, the CPU is provided with a logical address bus necessary for the logic for generating the index address and a bus for sending address conversion information from the secondary TLB to the primary TLB. A means for generating an index address for selectively accessing the external high speed memory as a secondary cache memory or a secondary TLB is provided.

[0014]

By using the index address generation circuit of the external high speed memory, the index address for accessing the secondary cache memory for operand and the secondary cache memory for instruction are accessed to the high speed memory provided outside the CPU. Or an index address for accessing the secondary TLB is generated. Then, this index address is sent to the external high-speed memory, and the target data is sent to the CPU via the data signal line for the external high-speed memory of the CPU. Therefore, it is possible to realize the information processing apparatus including the secondary TLB without changing the configuration of the conventional information processing apparatus shown in FIG.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Will be described.

FIG. 1 is a diagram for explaining the flow of data relating to the TLB of the operand system and the cache memory in one embodiment of the present invention. In FIG. 1, reference numeral 100 denotes a central processing unit (hereinafter referred to as CPU), which is integrated into one chip as an LSI and exchanges with the outside through pins 150 to 155 and the like. An external high speed memory 130 for tags, an external high speed memory 131 for data, and a main storage device 125 are provided outside the CPU 100. In this embodiment, the capacity of the data memory 131 is 256 KB (kilobytes), which is 1
Access is made in units of 32B (byte) called a block. Further, the information processing apparatus shown in FIG. 1 employs a virtual memory system, and in the present embodiment, it has 64K 4GB (gigabyte) virtual address space by 48-bit address information, and in units of pages of 4KB. It is subdivided.

Reference numeral 101 is an instruction processing unit for fetching, decoding and operating instructions inside the CPU. 102,
103 is a primary TLB built in each CPU 100
A memory for tags (hereinafter referred to as FTLB) and a data memory for storing physical addresses. 104, 105, 106,
Reference numerals 107 are a tag memory and a data memory of a primary cache memory (hereinafter referred to as FCM) for operands and instructions, respectively. The configuration of FTLB in this embodiment is 64
It is an entry direct map system, and the FCM structure is 8 KB for instruction FCM and 4 K for operand FCM.
B, which uses the direct map method. FT
LB and FCM are logical addresses LADD sent from the instruction processing unit 101 via the logical address bus 10.
Accessed using R.

120 and 121 are for operand 2 respectively
Next cache memory (SCM) tag and SC for instruction
M tag memories, 122 and 123 are operand SCM and instruction SCM data memories, respectively. Operand SCM tag memory 120, instruction S
The tag external high-speed memory 130 including the CM tag memory 121, the operand SCM data memory 122, the instruction SCM data memory 123, and other data external high-speed memory 131 are transmitted via the physical address bus 11 in the CPU 100. An index address generated by an external high speed memory index address generation logic (to be referred to as IAC hereinafter) 113, which will be described later, is received from the physical address PADDR to be accessed via a pin 155.
The configuration of the SCM is 64 KB for the instruction SCM and 128 KB for the operand SCM, and both adopt the direct map method.

Reference numeral 124 is a secondary TLB (hereinafter referred to as STLB), which is also based on the logical address LADDR sent via the logical address bus 10 in the CPU 100, and will be described later.
The index address generated by the AC 113 is received via the pin 155 and accessed. STLB1
24 is configured with a 2-way set 2-way set associative system. In the present embodiment, the external high-speed memory 131 is composed of the SCM 122 for operand and the SC for instruction.
The M123 and STLB124 are divided at a ratio of 2: 1: 1.

Reference numeral 125 is a main memory, and the address bus 2
3, using the data bus 24, pin 151 and pin 152
Is accessed via.

The FTLB hit judgment circuit 110 is provided with a logical address LADD sent via the logical address bus 10.
This is a circuit for comparing whether R <0:30> and the logical address tag read from the FTLB tag memory 102 match.

The FCM hit determination circuit 111 is a FTLB
This is a circuit for comparing whether the physical address PADDR <0:19> read from the data 103 via the bus 11 and the physical address tag read from the FCM tag memory 104 match.

The SCM hit determination circuit 112 receives the physical address PADDR sent via the physical address bus 11.
The circuit compares <0:14> with the physical address tag read from the tag external high-speed memory 130 via the pin 154 using the data bus 21.

The hit determination circuits 110, 111, 11
In 2, when the comparison targets match, it is called a hit.
Indicates that valid information exists in the corresponding data memory. On the other hand, the case where the comparison targets do not match is called a miss, which means that valid information does not exist in the data memory. For example, in the case of FTLB hit in the FTLB hit determination circuit 110, it indicates that the FTLB data 103 has valid address translation information.
In the case of FTLB miss, it indicates that the FTLB data 103 does not have valid address translation information.

The external high speed memory index address generation logic (hereinafter referred to as IAC) 113 is used for the logical address bus 10.
Address LADDR <25:35 sent via
> Bits and 12 bits of the physical address PADDR <15:26> sent via the bus 11,
It is a circuit that generates an index address for accessing the external high-speed memory.

Next, the flow of the access processing of the operand in the case of the FTLB hit in this embodiment will be described.

(1) Processing in the case of FTLB hit or FCM hit After the FCM hit determination, the FCM data obtained using the 10 bits of LADDR <36:45> sent via the logical address bus 10 is the data bus 12. Is transferred to the instruction processing unit 101 via.

(2) FTLB hit, FCM miss, SC
Processing in case of M hit In order to obtain data from SCM after judgment of FCM mistake,
In the IAC 113, 12 bits of PADDR <15:26> sent via the physical address bus 11 are used to generate 13 bits of the index address INDEX <0:12>. The index address is sent to the external high speed memory via the index address bus 20,
The SCM tag 120 and SCM data 122 are accessed. SCM hit determination tag information is sent from the SCM tag 120 via the data bus 21 to the SCM hit determination circuit 11
SCM hit judgment is performed. Also, S
SCM data from the CM data 122 is data bus 2
2, sent to the instruction processing unit 101 via the pin 153 and the data bus 12, and simultaneously registered in the FCM data 105 via the data bus 12.

(3) FTLB hit, FCM miss, SC
Processing in case of M miss After physical error judgment of SCM, physical address bus 11, pin 15
1. The main memory 125 is accessed by the physical address sent via the address bus 23, and the data is sent via the data bus 24 and the pin 152. At the same time, the data in the main memory 125 is registered in the FCM data 105 via the data bus 12 and in the SCM data 122 via the pin 153 and the data bus 22.

Next, the flow of operand access processing in the case of an FTLB miss in this embodiment will be described.

After the FTLB miss judgment, 11 of LADDR <25:35> sent via the logical address bus 10 in the IAC 113 to access the STLB.
Index address INDEX <0:
12> 13 bits are generated. INDEX <0: 1
2> is the external high-speed memory 131 via the address bus 20.
STLB124 in the external high speed memory for data
Area is accessed. 32 in the area of STLB124
B data is transferred to FTLB1 via the data buses 22 and 12.
It is sent to 02 and 103, and registration and hit determination are performed for each 16B.

In this embodiment, after registration in FTLB, FTL
The B hit decision circuit 110 is used to make a hit decision on the TLB information sent from the STLB. Hit judgment is 2
The entries are sequentially performed, and if the result of the determination is a hit, the hit entry is left in the FTLB. Then, the FTLB hit process is performed, and access to the cache memory is started. On the other hand, if the determination results are both mistakes, the address translation information is retrieved from the address translation table managed on the main memory 125. The address translation information is sent to the STL via the data buses 24 and 22.
It is registered in B124, and at the same time F via bus 12
It is registered in the TLBs 102 and 103.

Although only the operand access is described with reference to FIG. 1, the instruction access also applies to the SCM tag 12.
1, except that the SCM data 123 is used.

Next, the IAC 113 will be described in detail with reference to FIGS.

FIG. 3 is a block diagram of main parts showing an input signal and an output signal to the IAC 113. IAC113 is S
Physical address PADDR <1 for accessing CM
5:26>, the logical address LADDR <25:35> for accessing the STLB, and the STLB selection signal 2
40 and an index address IND for accessing the external high speed memory by inputting the SCM selection signal 250.
EX <0:12> is generated.

The STLB selection signal 240 is a control signal generated inside the CPU 100, and a logical value "1" is sent when the STLB is accessed, and a logical value "0" is sent otherwise.

The SCM selection signal 250 is a control signal generated inside the CPU 100. When accessing the operand SCM, a logical value "1" is sent, and in other cases, a logical value "0" is sent. To be However, the STL
The logical values of the B selection signal 240 and the SCM selection signal 250 never become "1" at the same time.

Next, the upper 2 bits INDEX <0: 1> of the index address for accessing by dividing the areas of the external high speed memories 130 and 131 at a ratio of 2: 1: 1.
The method of generating will be described. FIG. 7 is a diagram showing a 256 KB memory space. The upper memory area 700 is an area accessed at addresses 0x000 to 0x7FF. The lower memory area is further divided into an upper side and a lower side, and the lower half upper side memory area 710 has an address 0x800.
˜0xBFF, the memory area 720 in the lower half of the lower half is at addresses 0xC00 to 0xF.
This area is accessed by FF. That is, when the upper 2 bits are “00” or “01”, the memory area 700 is accessed, when the upper 2 bits are “10”, the memory area 710 is accessed and the upper 2 bits are “11”. Memory area 720 is accessed.

FIG. 4 shows an embodiment of the logic of the IAC 113.

The upper 2 bit generation logic 310 uses the STLB
INDEX <0: 1> using the selection signal 240, the SCM selection signal 250, and the physical address PADDR <15>
Is generated and the following logical values are generated as shown in Table 1.

[0041]

[Table 1]

(1) When the logical value of the STLB selection signal 240 is "0" and the logical value of the SCM selection signal 250 is "1" INDEX <for accessing the operand SCM
The logical value of 0> is set to “0”. The value of PADDR <15> is used as the logical value of INDEX <1>.

(2) When the logical value of the STLB selection signal 240 is "0" and the logical value of the SCM selection signal 250 is "0": The logical value of INDEX <0> is "1" for accessing the instruction SCM. And set the logical value of INDEX <1> to “0”.

(3) When the logical value of the STLB selection signal 240 is "1" and the logical value of the SCM selection signal 250 is "0" Set the logical value of INDEX <0> to "1" to access the STLB, The logical value of INDEX <1> is set to “1”.

Selector circuits 311-0 to 311-10
STLB selection signal 240, PADDR <16:26
> And LADDR <25:35>
This is a circuit that generates each bit of X <2:12>.

STLB is accessed using an index address generated from the logical address LADDR,
The instruction SCM and the operand SCM are accessed using an index address generated from the physical address PADDR. Therefore, the STLB selection signal 24
If the logical value of 0 is “0”, PADDR <16:26>
11 bits are selected as INDEX <2:12> and the logical value of the STLB selection signal 240 is “1”,
11 bits of LADDR <25:35> are INDEX <
2:12>.

FIG. 5 shows the IAC1 of the second embodiment of the present invention.
13 is a circuit diagram of FIG. The second embodiment has a function that allows the user of the information processing apparatus to select whether the external high speed memory has STLB or not. In order to realize the above function, the secondary TLB use mode selection signal 26
0 is newly set. Then, using the secondary TLB usage mode selection signal 260, the operand SCM, the instruction SCM, and the STLB are set to 2 from the higher order of the address area of the external high-speed memory.
Assigned one-to-one, or operand SCM,
It is possible to select whether to allocate the instruction SCM one-to-one. As the STLB use mode selection signal 260, a logical value “1” is sent when the STLB is included in the external high-speed memory, and a logical value “0” is sent when the STLB is not included. However, the logical value of the STLB use mode selection signal does not become "0", and the STLB selection signal does not become "1".

In FIG. 5, upper 2 bit generation logic 500
Is an STLB selection signal 240, an SCM selection signal 250,
This is a circuit that generates INDEX <0: 1> using the secondary TLB usage mode selection signal 260 and the physical address PADDR <15>, and generates the logical values shown in Table 2. The selector circuits 311-0 to 311-10 are the same circuits as the circuits that generate the bits of INDEX <2:12> of the first embodiment.

[0049]

[Table 2]

Next, INDEX <0: 1> of the second embodiment.
The method of generating will be described.

(1) When the logical value of the STLB selection signal 240 is "0" and the logical value of the SCM selection signal 250 is "1" The memory area of the SCM for operand is always in the higher order regardless of the selection of the STLB use mode. Occupy half. Therefore, to access the SCM for operands, IND
The logical value of EX <0> is “0”, and the logical value of INDEX <1> is the value of PADDR <15>.

(2) When the logical value of the STLB selection signal 240 is "0", the logical value of the SCM selection signal 250 is "0", and the logical value of the secondary TLB use mode selection signal 260 is "0" External high speed Since STLB is not used for the memory, the lower half address area is used as an instruction SCM. Therefore, the logical value of INDEX <0> is set to “1”, and IN
The value of PADDR <15> is used as the logical value of DEX <1>.

(3) When the logical value of the STLB selection signal 240 is "0", the logical value of the SCM selection signal 250 is "0", and the logical value of the secondary TLB use mode selection signal 260 is "1". In order to access the instruction SCM in the external high-speed memory, the logical value of INDEX <0> is set to “1” and the logical value of INDEX <1> is set to “0”.

(4) When the logical value of the STLB selection signal 240 is "1", the logical value of the SCM selection signal 250 is "0", and the logical value of the secondary TLB use mode selection signal 260 is "1". In order to access the STLB in the external high speed memory, the logical value of INDEX <0> is set to “1”,
The logical value of INDEX <1> is set to “1”.

Next, INDEX <in the second embodiment
A method of generating 2:12> will be described. When the logical value of the STLB usage mode selection signal is “0”, PADDR <
16:26> is selected as INDEX <2:12>. When the logical value of the TLB usage mode selection signal is "1", the method of generating INDEX <2:12> is the same as that of the first embodiment.

By the above operation, the index address INDEX <for the external high speed memory is set in the IAC 113.
0:12> is generated and the operand SCM or instruction SCM or STLB in the external high speed memory can be accessed.

In the present embodiment, the capacities of the cache memory and the TLB are fixed and the direct map method is explained. However, in the case where the FCM is not provided or another capacity is used,
Alternatively, even when the cache memory and the TLB of the full associative method or the set associative method are provided, the present invention can be applied with a slight modification which can be easily analogized.

Further, in the present embodiment, the hit determination circuit of FTLB is diverted without providing the hit determination circuit of STLB and S
A method for making a TLB hit determination is presented. Therefore, the FT that was accessed when the FTLB was missed
The LB information is overwritten and erased. But F
Even when it is determined that the TLB information registered in the TLB is a mistake, finally, the correct TLB information retrieved from the address conversion table managed in the main memory 125 is again FT.
Since it is registered in the LB, there is no problem in registering in the FTLB before performing the hit determination of the STLB information.

Further, the effect of the present invention does not change even if a hit determination circuit for STLB is separately provided.

Further, in the present embodiment, the operand SCM, the instruction SCM, from the upper part of the address area of the external high speed memory,
Although the STLB is allocated, the external high speed memory may be configured by changing the allocation order of the memory space.

Further, in this embodiment, the ratio of the operand SCM, the instruction SCM and the STLB in the external high speed memory is set to 2: 1: 1, but the ratio of division of the memory space may be changed.

Further, although the present embodiment describes the CPU provided with the external high speed memory and the main memory, it is applied to the information processing system as shown in FIG. 6, for example. That is, it is configured by a chip-like CPU 1 including a primary cache memory, a primary TLB, and a built-in external high speed memory index address generation circuit 5, an SRAM, and the like.
A minimum signal line 6 connects between the secondary cache memory and the external high-speed memory 3 forming the secondary TLB. The index address generation logic (IA) shown in FIG.
If C) is used, the external high speed memory index address generation circuit 5 in the CPU 1 needs only a few gates and the secondary TL.
The effort to achieve B can be minimized. Further, the CPU 1 causes the main storage device 4 and the input / output control device 610-a (the input / output device 60) via the system bus 7.
0) and the input / output control device 610-b (secondary storage device), and by these configurations, a high-speed and high-performance information processing system can be formed.

In this embodiment, a part of the instruction cache memory is reduced to realize the secondary TLB. ACM si
garch CompArch News No. Two
June 1990, p. According to the hit rates of the instruction cache memories shown in Nos. 61 to 68, the hit rates do not significantly decrease in the 128 KB and 64 KB instruction cache memories assumed in this embodiment.
The effect of realizing the second-order TLB can be obtained.

[0064]

As described above, by applying the present invention to the CPU, the secondary TLB can be realized at a low cost with a simple structure without drastically changing the structure of the information processing apparatus. The performance of the information processing device can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a data flow in an information processing device that implements the present invention.

FIG. 2 is a block diagram of an information processing apparatus including a conventional external high speed memory.

FIG. 3 is a schematic block diagram of an index address generation circuit of an external high speed memory that implements the present invention.

FIG. 4 is a diagram of an index address generation logic for an external high speed memory for explaining the first embodiment of the present invention.

FIG. 5 is a diagram of an index address generation logic for an external high speed memory for explaining a second embodiment of the present invention.

FIG. 6 is a configuration diagram of an information processing system to which the present invention is applied.

FIG. 7 is a diagram of a memory accessed at a ratio of 2: 1: 1 for explaining the external high speed memory of the present invention.

[Explanation of symbols]

1 ... Central processing unit, 2 ... Primary cache memory 2, 3 ...
External high-speed memory, 4 ... Main memory device, 5 ... External high-speed memory index address generation circuit, 6 ... External high-speed memory bus, 7 ... System bus, 8 ... TLB, 10 ... Logical address bus, 11 ... Physical address bus, 12 ... data bus, 20 ... index address bus, 21, 22, 2
4 ... Data bus, 23 ... Address bus, 100 ... Central processing unit, 101 ... Instruction processing unit, 102 ... Primary TL
B tag, 103 ... Primary TLB data, 104 ... Operand primary cache memory tag, 105 ... Operand primary cache memory data, 106 ... Instruction primary cache memory tag, 107 ... Instruction primary cache memory data, 110 ... Primary TLB hit determination circuit, 111
... primary cache memory hit determination circuit, 112 ... secondary cache memory hit determination circuit, 113 ... external high speed memory index address generation circuit, 120 ... operand secondary cache memory tag, 121 ... instruction secondary cache memory tag, 122 ... Operand secondary cache memory data, 123 ... Instruction secondary cache memory data, 124 ... Secondary TLB, 125 ... Main memory, 1
30 ... External high-speed memory for tag, 131 ... External high-speed memory for data, 240 ... STLB selection signal, 250 ... SCM
Selection signal 260 ... STLB use mode selection signal, 31
0 ... Index high-order 2-bit generation circuit for external high-speed memory in the first embodiment, 311 ... Logical address / physical address selection circuit, 500 ... Index high-order 2-bit generation circuit for external high-speed memory in the second embodiment, 60
0 ... I / O device, 610 ... I / O control device, 620 ... 2
Next storage device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuhiko Okada 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Osamu Nishii 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Tsuneo Funabashi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Semiconductor Design & Development Center, Ltd. (72) Inventor Takehisa Hayashi 1-280, Higashi Koikeku, Kokubunji, Tokyo Stock Central Research Laboratory of Hitachi, Ltd.

Claims (6)

[Claims] 1. A central processing unit having an address translation mechanism, a main storage unit for holding instructions and data for controlling the central processing unit, and an external unit for holding a copy of some information in the main storage unit. An information processing apparatus having a memory, comprising an address conversion mechanism characterized in that it has means for generating an index address for accessing the external memory by inputting a logical address and a physical address in the central processing unit. Information processing equipment. 2. A main memory for holding instructions and data for controlling a central processing unit, a primary cache memory for holding a copy of part of the information in the main memory, and a physical address. A central processing unit that includes a primary TLB for storing the address translation information of the above, and is provided with an address translation mechanism, and holds a copy of part of the information in the storage unit.
An information processing device comprising a secondary cache memory and an external memory forming a secondary TLB for storing address translation information for generating a physical address, wherein a logical address and a physical address are input into the central processing unit. As an index address for accessing the secondary cache memory with respect to the external memory, and a secondary T
It has a means for generating an index address for accessing the LB, a bus for a logical address necessary for the logic for generating the index address, and a bus for sending the primary TLB address conversion information from the secondary TLB. An information processing apparatus having a characteristic address translation mechanism. 3. An information processing apparatus having an address conversion mechanism according to claim 2, wherein said index address generating means has means for selecting a logical address when a secondary TLB miss occurs. 4. The index address generating means has means for selecting whether to selectively use a physical address and a logical address as an index address, or to use only a physical address as an index address. An information processing apparatus provided with the described address translation mechanism. 5. The external memory is used by being divided into three areas of a secondary cache memory dedicated to an operand, a secondary cache memory dedicated to an instruction, and a memory dedicated to a secondary TLB,
3. The information processing apparatus having an address conversion mechanism according to claim 2, wherein the ratio of each area is set to 2: 1: 1. 6. A central processing unit integrated into one chip as an LSI, which stores a primary cache memory for holding a copy of a part of the information in a main memory and address conversion information for generating a physical address. Including the primary TLB
An index address for accessing the secondary cache memory and the secondary TLB has means for generating an index address for accessing a secondary cache memory and an external memory forming the secondary TLB by inputting the logical address and the physical address. A central processing unit having an address translation mechanism configured to transfer the data from a common pin to the external memory.