JP2751680B2 - LCD drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD (Liquid Crystal Display) driving circuit, and more particularly to an LCD driving circuit which is designed to be built in a single chip microcomputer or the like.

[0002]

2. Description of the Related Art FIG. 2 shows a circuit configuration of a segment output section of a conventional LCD drive circuit. The circuit configuration of the common output section is almost the same, and is not shown here. Transistor in LCD driving circuit T _r1: 1 from transistor T _r4: by turning on and off in accordance with the timing generated fourth four transistors by the LCD drive timing generating circuit 5, V to the LCD drive power supply terminal _LC0
The LCD is driven by supplying the voltage level supplied from ＶV _LC3 to the SEG terminal.

As shown in FIG. 2, when the data of the segment data latch 6 is 11O1B (bit 0 corresponds to COM0, 1 is selected and 0 is not selected), this LCD driving circuit is 4 time division, 1 / An output waveform (e) from the SEG terminal when operating in the 3-bias drive mode, output waveforms (a) to (d) from common output terminals COM0 to COM3 (not shown), and COM0- S
Applied voltage waveform (f) of LCD pixel specified by EG, C
FIG. 3 shows an applied voltage waveform (g) of the LCD pixel specified by OH1-SEG.

FIGS. 3A to 3D show common output CO.
The waveforms output from M0 to M3 are shown, and V _LC3 and V _LC3
The timing of outputting the voltage level of _LC0 is when the terminal is selected. At other _times , V _LC2 and V _{LC
This is when} the voltage level of _LC1 is output and not selected.

In the output waveform of the SEG terminal shown in FIG. 3 (e), the voltage levels of V _LC0 and V _LC3 are output at the timings corresponding to COM0, COM2 and COM3 in accordance with the data 11O1B of the segment data latch 6, and The non-selection levels of V _LC2 and V _LC1 are output at the timing corresponding to COM1.

[0006] V _LC0 and each transistor T to output a selection level of V _{LC3 r1:} 1 and T _r4: 4 is turned on, the outputs of V _LC1, V _LC2 unselected level, the transistor T _r2: 2, the timing is generated so that _Tr3 : 3 is turned on.

[0007]

The conventional LCD driving circuit has a sufficient function for the original function of driving the LCD. However, when it is built into a single-chip microcomputer, the number of pixels of the LCD display changes variously depending on the application device, and when an extra LCD drive terminal is generated, this extra terminal is used for other purposes-a normal output port or input. There was a drawback that the port could not be used.

[0008]

An LCD drive circuit according to the present invention comprises a conventional LCD drive circuit having an output data latch, an input / output mode register, and a three-state whose output state is determined by the output data latch and the input / output mode register. An output buffer and an input buffer for inputting the level of the LCD drive terminal are provided, and all the LCD drive transistors are turned off according to the states of the output data latch and the input / output mode register.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. At a drawing, a transistor for driving the LCD T _r1: 1
Through T _r4: 4, LCD drive timing generating circuit: 5, segment data latches: construction of 6 is the same as the conventional.

The output data latch is written through the internal bus 10 and holds the data output from the output buffer 8 when the input / output mode register 11 selects the output mode.
The operation of the drive timing generation circuit 5 is controlled.

The input / output mode register 11 is connected to the internal bus 10
, Holds data for controlling the permission and prohibition of the output of the three-state output buffer 8, and its output controls the operation of the LCD drive timing generation circuit 5 through the AND gate 9.

The three-state output buffer 8 outputs the data held by the output data latch 7 to the SEG terminal when the output of the input / output mode register 11 is at a low level, and outputs the data when the output of the input / output mode register 11 is at a high level. Turns off the output and enters a high impedance state. The input buffer 12 is a buffer for taking the data of the SEG terminal into the internal bus.

According to such a configuration, when the data held in the input / output mode register 11 becomes low level and the output mode is selected, regardless of the data held in the output data latch 7, the LCD drive is performed through the AND gate 9. A low-level input is applied to the timing generation circuit 5. LCD drive timing generating circuit 5 by the input transistor T _r1: 1~T _r4: turns off all the transistors of the 4. At this time, since the three-state output buffer 8 outputs the data held in the output data latch 7, the value is output from the SEG terminal.
It operates as an OS output terminal.

When the data held in the input / output mode register 11 goes high and the input mode is selected,
The operation of the CD drive circuit differs depending on the data held in the output data latch 7. When the data held in the output data latch 7 is at the low level, the low level is input to the LCD drive timing generation circuit 5 through the AND gate 9. By this low level input, LC
D drive timing generating circuit 5 is a transistor T _r1:. 1 to
Turn off all the transistors of _Tr4 : 4. Therefore,
The SEG terminal becomes a high impedance state, and the state applied from the outside to the SEG terminal can be read into the internal bus 10 through the input buffer 12. That is, SE
The G terminal operates as an input port.

On the other hand, when the data held in the output data latch 7 is at a high level,
A high level is input to the D drive timing generation circuit 5. In response to this high level input, the LCD drive timing generation circuit 5 outputs the output of FIG. 3 (e) to the SEG terminal according to the data held in the segment data latch 6, as described in the conventional example. Therefore, the SEG terminal is
Operates as a drive terminal.

As apparent from the above description, according to the present embodiment, it is possible to cope with three usages of the LCD drive output; the output port and the input port without requiring any special means for switching the operation mode. Can be. Therefore, when the number of pixels of the LCD display is small and the LCD drive terminals are left,
It can be used as an output port or an input port, and has an effect that terminals are not wasted.

FIG. 4 shows a second embodiment of the present invention. In the present embodiment, the transistors _Tr5 : 13,
_Tr6 : 14 is added. According to such a configuration, the transistor T _r1: 1~T _r4: regardless off states of the 4, the transistor T _r5: 13 and T _r6:
By turning off the two 14 transistors, L
The CD drive output can be turned off. That is, when the output of the AND gate 9 is at a low level, the AND gate 16
Output Nch MOS transistor goes low T of _r6: 14 is turned off, Pch MOS transistors T _r5 output of NAND gate 15 becomes high level: 13 also turned off so that the transistor T _r1: 1 to T _r4: 4 on-off state Regardless, the LCD drive output can be turned off.

The effect of such a configuration is that, in the embodiment shown in FIG. 1, four transistors are required for each segment terminal, whereas in the present embodiment, two transistors can be used for control. It is more economical. The realized LCD drive waveform can be made exactly the same as that of the first embodiment by the configuration of the LCD drive timing generation circuit 5.

In both the first embodiment and the second embodiment, an intermediate level potential is applied to the input buffer 12 when an LCD drive output waveform is output. Therefore, the input buffer 12
Is turned on, a through current flows. For this reason, the input buffer 12 is configured to be turned on only when data is taken into the internal bus 10.

In both the first and second embodiments, the segment terminal and the general-purpose input / output port are shared.
Exactly the same configuration is possible for the common terminal.

In the previous two embodiments, one bit of the terminal was described. However, when used as an input / output port, several bits are put together and one address is given as a port for access. Then, when a bit manipulation instruction for a certain output buffer is executed, read-modify-write execution is performed for all the bits of the port.

Here, in both embodiments, writing to the output data latch 7 was always possible. Therefore, when a port is subjected to read-modify-write, the value of the input data is directly written into the output data latch 7 for bits other than those to be modified. Therefore, the value held by the output data latch 7 changes depending on the value of the SEG terminal. Here, when the input mode is selected by the input / output mode register 11, there is a problem that the state of the SEG terminal is changed from the input port state to the LCD drive terminal state contrary to the wishes.

However, if writing to the output data latch 7 is always prohibited, if the output mode is selected by the input / output mode register 11, it is impossible to modify the modification target bit, and furthermore, a simple write instruction is not allowed. It becomes possible.

In order to solve this problem, as a third embodiment, a read-modify-write operation is performed without affecting a write instruction and without affecting an output mode terminal during read-modify-write operation. When you execute the light,
The method in which the state of the terminal in the input mode does not change will be described.

FIG. 5 is a block diagram of a third embodiment of the present invention. FIG. 6 is a timing chart at the time of execution of the read-modify-write operation of the present embodiment.

First, each component will be described. The components 1 to 6, 8 to 12 are the same as in the embodiment of FIG. The address decoder 21 outputs a high level while a port address is being input from the internal bus 10. Here, it is assumed that the address is continuously input from the internal bus 10 from the read timing to the write timing at the time of the read-modify-write operation as shown in FIG.
The write inhibit latch 22 holds the high level when the address decoder 21 outputs the high level and the read signal goes to the high level. When the output of the address decoder 21 goes low, the low level is maintained. The output data latch 23 outputs the held data to the internal bus 10 when the read signal is transmitted from the read signal line 24 while the address decoder 21 is outputting the high level, and outputs the write signal from the write signal line 25. Is written through the internal bus 10 when transmitted. The read signal line 24 transmits a read signal. The write signal line 25 transmits a write signal. The NANDs 26 and 27 inhibit the write signal line 25 from transmitting a write signal to the output data latch 23 when the write inhibit latch 22 outputs a high level and the input / output mode register outputs a high level.

Next, the operation will be described. When the read-modify-write operation is performed, the address is input to the address decoder 21 through the internal bus 10 at the address timing. If this is the address of the port,
The address decoder 21 outputs a high level. When the read signal line transmits a read signal while the address decoder 21 is outputting a high level, the write inhibit latch 2
2 latches high level. In the input mode, the input / output mode register 11 outputs a high level. Therefore, by the NAND 26 and the AND 27,
The transmission of the write signal by the write signal line 25 is prohibited. Here, when the read-modify-write operation is performed, the data is written at the write timing in this one machine cycle, so that writing to the output data latch 23 is prohibited.

Next, when the address timing ends, the output of the address decoder 21 goes low,
The write inhibition latch 22 holds the low level, and the inhibition of the write signal line 25 is released. As described above, when read-modify-write is executed in the input mode,
Writing to the output data latch 23 can be prohibited. In the output mode,
Output data latch 23 by executing modify write
Can be written to. At the time of executing the write instruction, writing to the output data latch 23 is possible regardless of the input mode and the output mode.

Here, it is assumed that the address signals are continuous as shown in FIG. 6. However, even when the address signals of the time division bus system or the like are not continuous, the write inhibit latch 2
2 can be handled by changing the latch and release timings.

[0030]

As described above, according to the present invention, a general-purpose input / output port is added to the LCD drive unit, and the LCD drive circuit is driven by the data held in the output data latch and the data held in the input / output mode register. It is possible to select whether to use as a port, an output port, or an input port, so that the terminal functions can be used properly according to the number of pixels of the LCD display, and the terminal is wasted. This has the effect of not being able to do so.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional LCD drive circuit.

FIG. 3 is a timing chart showing an LCD drive output waveform.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram of an LCD drive circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing an operation at the time of executing a read-modify-write operation of an LCD drive circuit according to a third embodiment of the present invention.

Claims (2)

(57) [Claims] 1. An LCD drive circuit comprising: an LCD drive transistor that outputs an LCD drive power supply to an LCD drive output terminal; and a timing generation circuit that generates drive timing of the LCD drive transistor. A three-state output buffer connected to the three-state output buffer; a first data latch for holding output data of the three-state output buffer; a second data latch for controlling on / off state of the three-state output buffer; An input buffer connected to an output terminal, wherein the second data latch holds a value for turning on the three-state output buffer, or the second data latch turns off the three-state output buffer. And the value held in the first data latch is the first value. At one time, the LCD driving transistor is configured to be turned off, and the second data latch holds a value for turning off the three-state output buffer, and a held value of the first data latch is a second value. The LCD drive circuit according to claim 1, wherein the LCD drive transistor is turned on / off by a drive timing generated by the timing generation circuit. 2. When the second data latch holds a value for turning off the three-state output buffer, a read to the first data latch is detected, and a signal to the first data latch is detected. 2. The system according to claim 1, further comprising a third data latch for holding a value for inhibiting writing.
LCD drive circuit as described.