JPH05224790A - Input/output circuit - Google Patents

Abstract

PURPOSE:To reduce the area of the circuit without lowering the function of the input/output circuit at a single-chip microcomputer. CONSTITUTION:An input buffer circuit 12, output buffer circuit 11, pull-up resistor R1, first switch circuit Tr 3, pull-down resistor R2, second switch circuit Tr 4, input/output switching register 4, selection designating register 16 and an enable register 17 are connected to an input/output terminal 2. On the other hand, decode circuits 13a, 13b and 13c enabling the reload of stored data are respectively connected to the respective registers. Further, the decode circuit 13a to activate the input buffer circuit 12 is connected to the input buffer circuit 12 and, between the respective registers and the output buffer circuit 11 and between the first and second switch circuits Tr 3 and Tr 4, a logic circuit 18 is provided to drive the output buffer circuit 11 and the first and second switch circuits Tr 3 and Tr 4 based on stored data in the respective registers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output circuit of a single chip microcomputer.

In recent years, in the input / output circuit of a single chip microcomputer, a pull-up resistor or an input / output terminal level for raising the input / output terminal level to a predetermined level in order to reduce the number of parts of a device using the single chip microcomputer. It is becoming more common to incorporate a pull-down resistor that pulls down to a predetermined level.
However, since whether or not to use the built-in pull-up resistor or pull-down resistor depends on the user, it is possible to select whether or not to use the pull-up resistor or pull-down resistor by a preset program.

[0003]

2. Description of the Related Art An example of an 8-bit input / output circuit of a conventional single-chip microcomputer will be described with reference to FIG. 5. 8-bit input / output circuits 1a-1h are provided with input / output terminals 2a-2h, respectively. , The input / output circuits 1a to 1h are connected to the bus 3, respectively.

Since the input / output circuits 1a to 1h have the same structure, the structure of the input / output circuit 1a will be described below.
The input / output circuit 1a is provided with four registers, an input / output switching register 4, an output data register 5, a pull-up enable register 6 and a pull-down enable register 7, and each register is output from the bus 3, respectively. 1-bit write data can be stored.

The output signal of the input / output switching register 4 is input to one input terminal of the NAND circuit 8a and also to one input terminal of the NOR circuit 10a via the inverter circuit 9a.

The output signal of the output data register 5 is input to the other input terminals of the NAND circuit 8a and the NOR circuit 10a. The output signal of the NAND circuit 8a is the P channel M which constitutes the output buffer circuit 11.
The output signal of the NOR circuit 10a, which is output to the gate of the OS transistor Tr1, is also output to the gate of the N-channel MOS transistor Tr2 that also forms the output buffer circuit 11. The buffer circuit 11 is a transistor Tr
1 and Tr2 are connected in series between the high potential side power source Vcc and the low potential side power source Vss, and the drains of both transistors Tr1 and Tr2 are connected to the input / output terminal 2a.

The output signal of the pull-up enable register 6 is input to the gate of a P-channel MOS transistor Tr3 forming a switch circuit via an inverter circuit 9b, the source of the transistor Tr3 is connected to a power supply Vcc and the drain is It is connected to the input / output terminal 2a via a pull-up resistor R1.

The output signal of the pull-down enable register 7 is output to the gate of an N-channel MOS transistor Tr4 which constitutes a switch circuit, and the transistor Tr4 is provided.
Is connected to the power supply Vss, and the drain is connected to the input / output terminal 2a through the pull-down resistor R2.

The input / output terminal 2a is the input buffer circuit 1
2 and the output signal of the input buffer circuit 12 is output to the bus 3. Address decoder latch circuits 13a to 13d for selecting the registers 4 to 7 and the input buffer circuit 12 and writing data to the registers 4 to 7 or activating the input buffer circuit 12 are connected to the bus 3. Has been done. Then, when an address signal that matches an address set in advance in each of the address decoder latch circuits 13a to 13d is input from the bus 3, each of the address decoder latch circuits 13a to 13d.
13d outputs a signal of H level, and when the latch signal ALE is input in that state, each of the address decoder latch circuits 13a to 13d latches the output signal.

Address decoder latch circuits 13a ...
Since the configuration of 13d is the same except for the address signal set in advance, the configuration of the address decoder / latch circuit 13a will be described with reference to FIG. 6. Of the eight bus lines B0 to B7 forming the bus 3, B0,
B1, B4, B5, B7 are connected to the input terminal of the NAND circuit 8b, B2, B3, B6 are connected to the input terminal of the NOR circuit 10b, and the output signal of the NAND circuit 8b is input to the NOR circuit 10b. .. Therefore, bus line B
The address signal output to 0 to B7 is "1100110".
Since the NOR circuit 10b outputs an H level signal only when it becomes "1", the preset address is "1100" in the address decoder latch circuit 13a.
1101 ".

The output signal of the NOR circuit 10b is input to one input terminal of the NAND circuit 8c via the inverter circuits 9i and 9h. Further, the latch signal ALE is input to the inverter circuit 9h, and the latch signal ALE becomes H level.
At the level, the inverter circuit 9h is activated and N
The output signal of the OR circuit 10b is input to the NAND circuit 8c.

The H-level reset signal RS is always input to the other input terminal of the NAND circuit 8c. The output signal of the NAND circuit 8c is output via the inverter circuit 9c, and
It is inputted to one input terminal of the NAND circuit 8c via d and the latch signal ALE is inputted to the inverter circuit 9d.
Is inputted through the inverter circuit 9e and the output signal of the inverter circuit 9e becomes H level, the inverter circuit 9d is activated.

Therefore, when the H-level latch signal ALE is input to the inverter circuit 9h and the inverter circuit 9e, the inverter circuit 9h is activated and the output signal of the NOR circuit 10b is output to the NAND circuit 8c. When the latch signal ALE becomes L level, the inverter circuit 9d is activated and the output signal of the NAND circuit 8c is latched.

The output signal of the address decoder latch circuit 13a is input to one input terminal of the AND circuits 14a and 14c, and the read signal RD is input to the other input terminal of the AND circuit 14a. When the output signal of the address decoder / latch circuit 13a and the read signal RD become H level, the AND circuit 14a outputs an H level signal to the input buffer circuit 12, and the same input buffer circuit 12 becomes the H level signal. Is activated based on.

The output signal of the address decoder / latch circuit 13b is input to one input terminal of the AND circuit 14b, and the write signal WR is input to the other input terminal.
Is input and both the output signal of the address decoder latch circuit 13b and the write signal WR become H level, A
The ND circuit 14b outputs an H level signal to the input / output switching register 4. Then, the input / output switching register 4 rewrites the stored data into the write data input from the bus 3 based on the H level signal.

The write signal WR is input to the other input terminal of the AND circuit 14c, and when the output signal of the address decoder / latch circuit 13a and the write signal WR both become H level, the AND circuit 14c outputs the signal of H level as the output data. Output to register 5. Then, the output data register 5 rewrites the stored data into the write data input from the bus 3 based on the H level signal.

The output signal of the address decoder / latch circuit 13c is input to one input terminal of the AND circuit 14d, and the write signal WR is input to the other input terminal.
Is input and both the output signal of the address decoder latch circuit 13c and the write signal WR become H level, A
The ND circuit 14d outputs an H level signal to the pull-up enable register 6. Then, the pull-up enable register 6 rewrites the stored data with the write data input from the bus 3 based on the H level signal.

The output signal of the address decoder / latch circuit 13d is input to one input terminal of the AND circuit 14e, and the write signal WR is input to the other input terminal.
Is inputted and both the output signal of the address decoder latch circuit 13d and the write signal WR become H level, A
The ND circuit 14e outputs an H level signal to the pull-down enable register 7. Then, the pull-down enable register 7 rewrites the stored data into the write data input from the bus 3 based on the H level signal.

The operation of the input / output circuit 1a configured as described above will be described. At the time of an input operation, the address decoder latch circuit 13b outputs an H level signal based on the address signal output to the bus 3 prior to the input operation. And the write signal WR becomes H level and AND
An H level signal is output from the circuit 14b to the input / output switching register 4. Then, the data “0” is written in the input / output switching register 4 by the write data output from the bus 3 to the input / output switching register 4.

Then, from the input / output switching register 4 to L
A level signal is output to the output buffer circuit 11, and based on the output signal, both the transistors Tr1 and Tr2 are turned off, and the output buffer circuit 11 does not operate.

Further, based on the address signal output to the bus 3, the address decoder / latch circuits 13c and 13d output H level signals, and the write signal WR becomes H level and the AND circuits 14d and 14e output H level signals. The signal is output to the pull-up enable register 6 and the pull-down enable register 7. Then, the write data output from the bus 3 to the pull-up enable register 6 and the pull-down enable register 7 writes “0” or “1” data to the pull-up enable register 6 and the pull-down enable register 7.

Then, for example, if data "0" is written in the pull-up enable register 6 and data "1" is written in the pull-down enable register 7, the transistor Tr3 is written.
Is turned off and the transistor Tr4 is turned on, so that the input / output terminal 2a is connected to the power supply Vss via the pull-down resistor R2. When the write data is reversed, the input / output terminal 2a is connected to the power supply Vcc via the pull-up resistor R1.

When the data stored in each of the registers 6 and 7 is opposite to the above, the input / output terminal 2a has a pull-down resistor R.
When the data stored in the registers 6 and 7 are both "0", the input / output terminal 2a is not connected to either the power source Vcc or the power source Vss.

Then, based on the address signal output to the bus 3, the address decoder / latch circuit 13a outputs an H level signal and the read signal RD becomes H level, and the AND circuit 14a outputs H to the input buffer circuit 12.
Input buffer circuit 1 by outputting a level signal
2 is activated and the input signal input to the input / output terminal 2a is output to the bus 3 via the input buffer circuit 12.

During the output operation, data "1" is written in the input / output switching register 4 prior to the output operation, the output data is written in the output data register 5, and the pull-up enable register 6 and the pull-down enable register 7 are written. Data of "0" is written. Further, the read signal RD becomes L level, and the input buffer circuit 12 does not operate.

Then, the pull-up enable register 6
And the transistors Tr3 and Tr4 are both turned off by the L level output signal of the pull-down enable register 7,
The H level output signal of the input / output switching register 4 causes the NAND circuit 8a and the NOR circuit 10a to wait for the output signal of the output data register 5.

Here, for example, when the output data register 5 is H
When a level signal is output, the transistor Tr1 of the output buffer circuit 11 is turned on to output an H level output signal from the input / output terminal 2a, and when the output data register 5 outputs an L level signal, the transistor Tr2 of the output buffer circuit 11 is output. Is turned on and an L level output signal is output from the input / output terminal 2a.

The input / output circuit 1a operates as described above, and the other input / output circuits 1b-1h similarly operate with the address decoder latch circuit connected.

[0029]

However, the input / output circuit 1 of the single chip microcomputer as described above is used.
In each of a to 1h, four address decoder latch circuits 13a to 13d are required, and each address decoder latch circuit 13a to 13d is composed of a large number of logic circuits as shown in FIG.
Since the ND circuit 8b and the multi-input NOR circuit 10b are composed of a large number of transistors, the circuit area increases. Although the conventional example has an 8-bit configuration, the 16-bit configuration has a problem that the number of address decoder latch circuits is further increased and the circuit area is greatly increased.

An object of the present invention is to reduce the circuit area without deteriorating the function of the input / output circuit of the single chip microcomputer.

[0031]

FIG. 1 illustrates the principle of the present invention. That is, the input buffer circuit 12 and the output buffer circuit 11 are connected to the input / output terminal 2, and the high potential side power source Vcc is connected to the input / output terminal 2 via the pull-up resistor R1 and the first switch circuit Tr3. The input / output terminal 2 has a pull-down resistor R2 and a second switch circuit T.
The low-potential-side power supply Vss is connected via r4, the input / output switching register 4 for storing data for selecting whether to activate the output buffer circuit 11, and the output output from the output buffer circuit 11. A selection designation register 16 for storing either data or data for selecting a closing operation of one of the first and second switch circuits Tr3, Tr4; and the first and second switch circuits T
An enable register 17 for selecting whether or not to operate r3 and Tr4 is provided, and each of the registers 4, 16 and 17 is provided.
The registers 4, 16 and 17 are selected based on the address signal and the write signal WR input from the bus 3 and the write data output from the bus 3 to the registers 4, 16 and 17 are selected. Decoding circuits 13a, 13b, 13c for making it possible to rewrite the data stored in the register
And an address signal and a read signal RD input from the bus 3 to the input buffer circuit 12.
A decode circuit 13a for activating the input buffer circuit 12 is connected to each of the registers 4, 16,
Each of the registers 4, 17 is provided between the output buffer circuit 17 and the first and second switch circuits Tr3, Tr4.
A logic circuit 18 for driving the output buffer circuit 11 and the first and second switch circuits Tr3, Tr4 based on the stored data of 16, 17 is provided.

Further, as shown in FIG. 3, the pull-up resistor and the pull-down resistor are composed of a common resistor R3, and the resistor R3 and the first switch circuit Tr3 are connected from the input / output terminal 2.
Is connected to the high potential side power source Vcc through the input / output terminal 2 and the resistor R3 and the second switch circuit T.
It is connected to the low-potential-side power supply Vss via r4.

Further, as shown in FIG. 4, the pull-up resistor and the first switch circuit have a P-channel M provided with a predetermined ON resistance between the input / output terminal 2 and the high potential side power source Vcc.
An OS transistor Tr5 is connected, and the pull-down resistor and the second switch circuit connect an N-channel MOS transistor Tr6 having a predetermined ON resistance between the input / output terminal 2 and the low potential power supply Vss. Consists of

[0034]

When the output buffer circuit 11 is activated based on the data stored in the input / output switching register 4, the data stored in the selection designation register 16 is output from the input / output terminal 2 via the output buffer circuit 11 as output data. .. When the output buffer circuit 11 becomes inactive based on the data stored in the input / output switching register 4, either the first switch circuit Tr3 or the second switch circuit Tr4 is selected based on the data stored in the selection designation register 16. Is selected. At this time, it is selected whether to close the first switch circuit Tr3 or the second switch circuit Tr4 selected based on the data stored in the enable register 17 to perform the pull-up operation or the pull-down operation. ..

Therefore, the data stored in the selection designating register 16 becomes data for setting different operations during the output operation and the input operation, and it becomes possible to share the register.
As a result, the number of registers and address decoder latch circuits for selecting the registers and performing the write operation is reduced.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
Follow the instructions below. The same components as those of the conventional example are designated by the same reference numerals, and detailed description thereof will be omitted.

Input / output circuits 15a to 15h having an 8-bit structure
Are connected to the bus 3 and to the input / output terminals 2a to 2h, respectively. Each input / output circuit 15
Since a to 15h have the same configuration, the configuration of the input / output circuit 15a will be described. In the same input / output circuit 1a, the input / output switching register 4 and the output data are stored or the pull-up operation and the pull-down operation are performed. There are provided three registers, a selection designation register 16 for storing designation data for designating a state for selecting one of them, and an enable register 17 for selecting a pull-up operation or a pull-down operation. The output 1-bit write data can be stored.

The output signal of the input / output switching register 4 is input to one input terminal of the NAND circuit 8d and the NOR circuit 10d, and the inverter circuit 9f.
Through one input terminal of the NOR circuit 10c and NAN
It is input to the input terminal of the D circuit 8e.

The output signal of the selection designation register 16 is the NAND circuits 8d and 8e and the NOR circuits 10c and 10.
It is input to the input terminal of d. The output signal of the enable register 17 is input to the input terminal of the NAND circuit 8e and also to the input terminal of the NOR circuit 10d via the inverter circuit 9g.

The output signal of the NAND circuit 8d is output to the gate of the transistor Tr1 of the output buffer circuit 11, and the output signal of the NOR circuit 10c is output to the gate of the transistor Tr2.

The output signal of the NAND circuit 8e is connected to the gate of the transistor Tr3 for pull-up operation, and the output signal of the NOR circuit 10d is connected to the gate of the transistor Tr4 for pull-down operation.

Three address decoder latch circuits 13
a, 13b, 13c and AND circuits 14a, 14b, 1
4c and 14d have the same configuration as the conventional example, the output signal of the AND circuit 14a is output to the input buffer circuit 12 as in the conventional example, and the output signal of the AND circuit 14b is input / output switched as in the conventional example. The output signal of the AND circuit 14c is output to the register 4 and the output signal of the AND circuit 14d is output to the enable register 17. When each AND circuit outputs an H level signal, the stored data can be rewritten in each register.

Next, the operation of the input / output circuit configured as described above will be described. At the time of input operation, "0" data is written in the input / output switching register 4 prior to the input operation, desired data of "1" or "0" is written in the selection designation register 16, and the enable register 17 is written. Data of "1" or "0" is written.

When an L level signal is output from the input / output switching register 4 based on the data stored in each of the above registers, the output signal of the NAND circuit 8d becomes the H level and the output signal of the NOR circuit 10c becomes the L level. The buffer circuit 11 becomes inoperative.

When the data stored in the selection designation register 16 and the enable register 17 is "1", NAN
The output signal of the D circuit 8e becomes L level and NOR
The output signal of the circuit 10d becomes L level, the transistor Tr3 is turned on, and the input / output terminal 2a has a pull-up resistor R1.
Is connected to the power source Vcc via.

On the other hand, when the data stored in the selection designation register 16 is "0" and the data stored in the enable register 17 is "1", the output signal of the NAND circuit 8e becomes H level and the output signal of the NOR circuit 10d becomes high. Transistor Tr4 is turned on at the H level and input / output terminal 2
a is connected to the power supply Vss via the pull-down resistor R2.

When the data stored in the enable register 17 is "0", both the transistors Tr3 and Tr4 are turned off regardless of the data stored in the selection designation register 16. In this state, the address signal corresponding to the address set in the address coder latch circuit 13a is output to the bus 3, the read signal RD becomes H level, and the output signal of the AND circuit 14a becomes H level, and the input buffer The circuit 12 is activated. And input / output terminal 2
The input data input to a is input to the bus 3 via the input buffer circuit 12.

During the output operation, data "1" is written in the input / output switching register 4 and the desired output data "1" or "0" is written in the selection designation register 16 prior to the input operation, and the enable operation is enabled. Register 1
Data of “0” is written in 7.

An L level signal is output from the enable register 17 based on the data stored in each of the above registers,
The output signal of the NAND circuit 8e becomes H level and the output signal of the NOR circuit 10d becomes L level, and the transistors Tr3 and Tr4 are turned off.

When the H-level signal is output from the input / output switching register 4, the NAND circuit 8d and the NOR circuit 10c wait for the output signal of the selection designating register 16 and, for example, the data stored in the selection designating register 16 is " 1 "and the output signal is at the H level, the transistor Tr1 is turned on and the H level signal is input / output terminal 2
If the stored data is "0" and the output signal is L level, the transistor Tr2 is turned on and L
A level signal is output to the input / output terminal 2a.

As described above, in the input / output circuit 15a, the register for storing the output data and the register for selecting the pull-up operation or the pull-down operation are configured by the common selection designation register 16, and the pull-up operation or the pull-down operation is performed. The register for storing the data for selecting whether or not to be configured is one enable register 17.

Therefore, a total of three registers are required for one input / output circuit 15a, and a total of three address decoder latch circuits 13a to 13c are required to select the three registers and the input buffer circuit 12. Become. Therefore, it is possible to reduce the number of registers and address decoder latch circuits while ensuring the same function as the input / output circuits 1a to 1h of the conventional example, so that the circuit area can be reduced.

Next, a modified example of the input / output circuits 15a to 15h will be described with reference to FIG. Although the pull-up resistor R1 and the pull-down resistor R2 are separately provided in the above-described embodiment, as shown in FIG. 3, the drains of the transistors Tr3 and Tr4 are connected to the input / output terminal 2a via the resistor R3 to connect the drain of the transistor Tr3. The source is connected to the power supply Vcc and the source of the transistor Tr4 is connected to the power supply Vss. The NAND circuit 8 is provided at the gate of the transistor Tr3.
The output signal of the NOR circuit 10d is input to the gate of the transistor Tr4.

With such a configuration, the transistor Tr3
When the transistor Tr4 is turned on, the input / output terminal 2a is connected to the power source Vcc via the resistor R3 to perform the pull-up operation. When the transistor Tr4 is turned on, the input / output terminal 2a is connected to the power source Vss via the resistor R3. Pull-down operation is performed.

Therefore, with the above configuration, the pull-up resistor and the pull-down resistor can be made common to reduce the circuit area of the input / output circuits 15a to 15h. Next, another modification of the input / output circuits 15a to 15h will be described with reference to FIG.

In the above embodiment, the pull-up resistor R1 and the pull-down resistor R2 are provided separately, and each resistor R1,
Transistors Tr3 and Tr4 are provided as switch circuits for connecting R2 to the power supply Vcc or the power supply Vss, respectively.
As shown in FIG. 4, the drains of the small-sized P-channel MOS transistor Tr5 and N-channel MOS transistor Tr6 are connected to the input / output terminal 2a.
The source of r5 is connected to the power supply Vcc, and the source of the transistor Tr6 is connected to the power supply Vss.

The output signal of the NAND circuit 8e is input to the gate of the transistor Tr5, and the output signal of the NOR circuit 10d is input to the gate of the transistor Tr6.

With such a configuration, the transistor Tr5
When the transistor Tr6 is turned on, the input / output terminal 2a is connected to the power supply Vcc through the on resistance of the transistor Tr5 to perform a pull-up operation. When the transistor Tr6 is turned on, the input / output terminal 2a is turned on of the transistor Tr6. Power supply Vss via
And pull-down operation is performed.

Therefore, with the above configuration, the pull-up resistor and the transistor Tr5 as the switch circuit are formed by one element, and the pull-down resistor and the transistor Tr6 as the switch circuit are formed by one element. The circuit area of the input / output circuits 15a to 15h can be reduced.

[0060]

As described above in detail, the present invention exhibits an excellent effect that the circuit area can be reduced without deteriorating the function of the input / output circuit of the single chip microcomputer.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a modified example of the embodiment.

FIG. 4 is a circuit diagram showing another modification of the embodiment.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a circuit diagram showing an address decoder latch circuit.

[Explanation of symbols]

 2 input / output terminal 3 bus 4 input / output switching register 11 output buffer circuit 12 input buffer circuit 13 address decoder latch circuit 16 selection register 17 enable register 18 logic circuit R1 pull-up resistor R2 pull-down resistor Tr3 first switch circuit Tr4 second Switch circuit Vcc High-potential-side power supply Vss Low-potential-side power supply WR Write signal RD Read signal

Claims (3)

[Claims] 1. An input buffer circuit (12) and an output buffer circuit (11) are connected to an input / output terminal (2), and a pull-up resistor (R1) and a first input / output terminal (2) are connected to the input / output terminal (2). High potential side power supply (Vcc) via switch circuit (Tr3)
And a low potential power source (Vss) is connected to the input / output terminal (2) via a pull-down resistor (R2) and a second switch circuit (Tr4), and the output buffer circuit (1
Input / output switching register (4) for storing data for selecting whether to activate 1), output data output from the output buffer circuit (11) or the first and second switch circuits ( Tr3, Tr4) whether or not to operate the selection designation register (16) for storing any of the data for selecting the closed circuit operation and the first and second switch circuits (Tr3, Tr4) And an enable register (17) for selecting each register (4, 16, 17) based on an address signal and a write signal (WR) input from the bus (3). 16 and 17) and a decoding circuit (13a, 1) for rewriting the data stored in the register based on the write data output from the bus (3) to each register (4, 16, 17). b, and 13c) respectively connected, wherein the input buffer circuit (12) the bus (3)
A decode circuit (13a) that activates the input buffer circuit (12) based on an address signal and a read signal (RD) input from the register is connected to each of the registers (4, 1).
6, 17) and the output buffer circuit (11) and the first and second switch circuits (Tr3, Tr4) based on the data stored in the registers (4, 16, 17). An input / output circuit comprising a circuit (11) and a logic circuit (18) for driving the first and second switch circuits (Tr3, Tr4). 2. The pull-up resistor and the pull-down resistor are composed of a common resistor (R3), and the input / output terminal (2)
From the input / output terminal (2) to the resistor (R3) and the second switch circuit ( 2. The input / output circuit according to claim 1, wherein the input / output circuit is connected to a low potential side power source (Vss) via Tr4). 3. The pull-up resistor and the first switch circuit include a P-channel MOS transistor (Tr5) having a predetermined ON resistance between the input / output terminal (2) and the high potential side power supply (Vcc). The pull-down resistor and the second switch circuit are connected to form an N-channel MOS transistor (Tr6) having a predetermined ON resistance between the input / output terminal (2) and the low potential side power supply (Vss). The input / output circuit according to claim 1, wherein the input / output circuit is configured to be connected.