JP2745597B2 - BiCMOS integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a BiCMOS integrated circuit having bipolar transistors and complementary MOS transistors on the same substrate.

[Conventional technology]

BiCMOS integrated circuits are bipolar transistors (hereinafter
This is a semiconductor device formed by combining the advantages of each of a Bip Tr) and a complementary MOS transistor (hereinafter abbreviated as CMOS).
The OS must be formed in the same semiconductor substrate so as not to lose the advantage of low power consumption.

In addition, it is necessary to form a Bip Tr and a CMOS at the same time in one process to shorten the manufacturing period, and to reduce the device region by using the diffusion layer regions of the Bip Tr and the CMOS together.

Incidentally, a high-performance CMOS having a gate length of about 1 μm is used. When the gate length approaches 1 μm, the source,
A strong electric field is applied between the drains to generate hot carriers, which causes deterioration of MOS characteristics. Therefore, a MOS transistor structure is generally used in which a high-concentration region and a low-concentration region are provided in the drain region to reduce the electric field intensity between the source and the drain to suppress generation of hot carriers. In the case of a BiCMOS integrated circuit, a CMOS structure in which the above measures are taken is used.

 FIG. 3 is a sectional view of a conventional BiCMOS integrated circuit.

 This conventional example will be described along the manufacturing process.

In the drawing, 1 is a p-type silicon substrate, 2 is an n-type buried layer, 3 is a p-type buried layer, 4 is an n-type epitaxial layer, 5 is a p-well, and 6 is a field insulating film for separating elements. It is. The gate insulating film 7 is provided on the surface of the element region of such a semiconductor chip, and the base layer 24 is selectively provided on the Bip Tr region.

 Thereafter, gate electrodes 8, 9 are selectively formed.

Next, first n-type impurity atoms are ion-implanted using the gate electrode 8 as a mask material to form first source / drain regions 10-1 and 10-2 of the nMOS. Further, a second n-type impurity atom having a lower diffusion rate than the first n-type impurity atom is ion-implanted into the first source / drain region of the nMOS at a higher concentration than the first n-type impurity atom, to thereby form a second n-type impurity atom. Two source / drain regions 11-1 and 11-2 are formed.

Next, the first p-type impurity atom is ion-implanted in the same manner as in the nMOS to form the first source / drain regions 12-1, 12- of the pMOS.
2 is formed, and a second p-type impurity atom having a lower diffusion rate than the first p-type impurity atom is more concentrated than the first p-type impurity atom in the base layer 24 and the first source / drain region of the pMOS. To form a base electrode forming region 25 and second source / drain regions (13-1, 13-2).

Thereafter, an interlayer insulating film 20 is provided on the entire surface, an opening window is selectively formed, and a polycrystalline silicon film 14 is formed on the entire surface, and N is selectively formed.
The emitter region 26 is formed by ion-implanting the type impurity atoms.

Next, a metal film such as aluminum is deposited on the entire surface, and the aluminum and polycrystalline silicon films are selectively etched to form respective electrodes.

[Problems to be solved by the invention]

The above-mentioned conventional BiCMOS integrated circuit is mounted on the same semiconductor substrate.
CMOS area and Bip Tr area are provided independently, and CMOS
In addition, there is a disadvantage that it is difficult to improve the degree of integration because the Bip Tr is formed.

[Means for solving the problem]

The BiCMOS integrated circuit of the present invention has a first
A gate electrode provided on the conductive type semiconductor layer with a gate insulating film interposed therebetween, a second conductive type low-concentration semiconductor layer selectively provided with a portion immediately below the gate electrode therebetween, and the second conductive type low-concentration semiconductor layer A MOS transistor having a source (or drain) region composed of a second conductive type high concentration semiconductor layer provided in the second conductive type high concentration semiconductor layer and a second conductive type high concentration semiconductor layer provided in the second conductive type low concentration semiconductor layer A bipolar transistor having an emitter region of the first conductivity type.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

Although the portion A in the figure is an nMOS, it has the same structure as the conventional one, so that the description is omitted. B part is a pMOS formed using the present invention
And npnBip Tr. The portion B will be described below. An n-type buried layer 2, an n-type epitaxial layer 4, and an n-type epitaxial layer 4 on the surface of a semiconductor chip formed by selectively oxidizing the epitaxial layer 4 to form an element region on a p-type silicon substrate 1.
A gate insulating film 7 is provided thereon. In addition, a portion (B) having selectively formed gate electrodes 8 and 9 and excluding the region immediately below the gate electrode and the region where the collector electrode is formed is doped with, for example, 5 × boron atoms.
About 10 ¹³ 1 / cm ² ions are implanted and the p-type low-concentration semiconductor layer 12−
1,12-2 are formed. Further, the p-type low concentration semiconductor layer 12
-1 and 12-2 are selectively implanted with boron fluoride atoms, for example, at a concentration of 5 × 10 ¹⁵ 1 / cm ^2.
371, 13-2 are formed.

Thereafter, an interlayer insulating film 20 is formed on the entire surface to selectively form opening windows for the collector, the emitter, the base, the source, the drain, and the gate. At this time, the source or drain aperture window and the base aperture window 17-2 are also used and there is only one. Next, after a polycrystalline silicon film 14 is formed on the entire surface, N-type impurity atoms made of arsenic or the like are selectively ion-implanted, for example, at 1 × 10 ¹⁶ 1 / cm ² to form an n-type emitter region 15 in a p-type low concentration semiconductor layer. 12-1 is formed apart from the p-type high concentration semiconductor layer 13-1;
A metal film such as aluminum is deposited on the entire surface, and the metal film and the polycrystalline silicon film are selectively etched to form the respective electrodes of the transistor. The BiCM having the cross-sectional view shown in FIG.
Obtain an OS integrated circuit.

In this embodiment, the n-type epitaxial layer 4 is
And the p-type low-concentration semiconductor layer 12-1 is also used as a base region and a source (or drain).
Because it is also used as an area and also as an electrode, the conventional BiCMOS
The degree of integration can be greatly improved as compared with an integrated circuit.

FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.

In the figure, the A 'portion is an nMOS, the B' portion is an npnBip Tr and a pMOS, and only the B 'portion will be described below.

The steps up to the formation of the n-type buried layer 2 and the n-type epitaxial layer 4 on the p-type silicon substrate 1 are the same as in the first embodiment.

Next, by selective oxidation, the collector electrode formation region and MOST
The gate region is formed separately and the gate insulating film is selectively formed only in the MOS region. Next, a collector 22 and gate electrodes 8 and 9 are formed by selectively forming a polycrystalline silicon film containing a high concentration of phosphorus atoms on the entire surface.

Next, low-concentration boron atoms are ion-implanted into the MOST formation region except immediately below the gate electrode to form a p-type low-concentration semiconductor layer 12-1,
... is formed.

Next, a vapor growth oxide film is formed on the entire surface, and anisotropic etching is performed to form a sidewall 21 of an insulating film on the collector and gate electrode side walls with a thickness of 0.1 to 0.3 μm.

Then, boron fluoride atoms are selectively ion-implanted at a high concentration into the p-type low-concentration semiconductor layers 12-1,... To form the p-type high-concentration semiconductor layers 13-1,. .

Next, an opening window is selectively formed in the interlayer insulating film to form an opening window for forming the collector, emitter, base, source, drain, and gate electrodes. At this time, the aperture window of the source or drain and the aperture window of the base are also used.
Next, after a polycrystalline silicon film is formed on the entire surface, n-type impurity atoms such as arsenic are selectively ion-implanted to form a p-type low-concentration semiconductor layer 12.
The n-type emitter region 15 is formed at a distance of -1 from the p-type high concentration semiconductor layer 1371.

Next, after a wiring layer of aluminum or the like is deposited, the aluminum and polycrystalline silicon films are simultaneously etched to form collector, emitter, base, source, drain, and gate electrodes. The second embodiment shown in FIG. The state is as shown in the sectional view.

According to this embodiment, as in the first embodiment, the n-type epitaxial layer 4 also serves as a collector region and a well, and the p-type low-concentration semiconductor layer also serves as a base region and a source (or drain) region. The element area can be greatly reduced.

Also, since the collector extraction region 27 and the MOS formation region are separated by a field insulating film, after forming the p-type low concentration semiconductor layer,
It is possible to prevent impurity atoms in this layer from diffusing to the collector extraction region, and to obtain a BiCMOS integrated circuit with a high yield.

Further, since the side wall is formed with the side wall of the gate electrode, the distance between the p-type low-concentration semiconductor layer and the p-type high-concentration semiconductor layer can be formed stably. An excellent BiCMOS integrated circuit can be obtained.

〔The invention's effect〕

As described above, according to the present invention, by forming the emitter region of the Bip Tr in the low-concentration source (or drain) region of the CMOS, the size of the element formation region becomes substantially equal to the size of the CMOS integrated circuit. BiC with high integration, high frequency characteristics equivalent to Bip Tr, and low power consumption equivalent to CMOS
A MOS integrated circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention, and FIG. 3 shows a conventional BiCMOS integrated circuit. It is sectional drawing of the semiconductor chip shown. 1 ... p-type silicon substrate, 2 ... n-type buried layer, 3 ... p
Embedded layer, 4 n-type epitaxial layer, 5 p-well, 6 field insulating film, 7 gate insulating film, 8
…… nMOS gate electrode, 9… pMOS gate electrode, 10−
1,10-2... N-type low concentration semiconductor layer, 11-1, 11-2.
-Type high-concentration semiconductor layer, 12-1, 12-2 ... p-type low-concentration semiconductor layer, 13-1, 13-2 ... p-type high-concentration semiconductor layer, 14 ... polycrystalline silicon film, 15 ... n Type emitter region, 16-1, 16-2
... aluminum electrode of gate, 17-1 ... source or drain electrode, 17-2 ... electrode serving as source or drain and base, 18 ... emitter electrode, 19 ... collector electrode, 20 ... interlayer insulating film , 21 ... sidewall, 22 ...
... a collector electrode formed simultaneously with the gate electrode, 23 ... a base electrode, 24 ... a base layer, 25 ... a base electrode formation region, 26 ... an emitter region, 27 ... a collector extraction region.

Claims (1)

(57) [Claims] 1. A gate electrode provided on a first conductive type semiconductor layer on a surface of a semiconductor chip with a gate insulating film interposed therebetween, and a second conductive type low-concentration semiconductor selectively provided immediately below the gate electrode. A MOS transistor having a source (or drain) region composed of a layer and a second conductive type high concentration semiconductor layer provided in the second conductive type low concentration semiconductor layer; A bipolar transistor having a conductive type high-concentration semiconductor layer and a first conductive type emitter region provided at a distance therefrom.
CMOS integrated circuit.