JP2745597B2 - BiCMOS integrated circuit - Google Patents
BiCMOS integrated circuitInfo
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- JP2745597B2 JP2745597B2 JP63308209A JP30820988A JP2745597B2 JP 2745597 B2 JP2745597 B2 JP 2745597B2 JP 63308209 A JP63308209 A JP 63308209A JP 30820988 A JP30820988 A JP 30820988A JP 2745597 B2 JP2745597 B2 JP 2745597B2
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- concentration semiconductor
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は同一基板上にバイポーラ・トランジタスと相
補型MOSトランジスタを有するBiCMOS集積回路に関す
る。Description: BACKGROUND OF THE INVENTION The present invention relates to a BiCMOS integrated circuit having bipolar transistors and complementary MOS transistors on the same substrate.
BiCMOS集積回路は、バイポーラ・トランジスタ(以下
Bip Trと記す)と相補型MOSトランジスタ(以下CMOSと
記す)の各々の有する長所を組合わせて形成する半導体
装置であり、Bip Trの高周波特性の優れている利点、CM
OSの低消費電力である利点を損なわない様に同一半導体
基板内に形成する必要がある。BiCMOS integrated circuits are bipolar transistors (hereinafter
This is a semiconductor device formed by combining the advantages of each of a Bip Tr) and a complementary MOS transistor (hereinafter abbreviated as CMOS).
The OS must be formed in the same semiconductor substrate so as not to lose the advantage of low power consumption.
又一工程でBip TrとCMOSを同時に形成して製造工期を
短縮する事,Bip TrとCMOSの拡散層領域を互いに兼用し
て素子領域を小型化する事が必要条件である。In addition, it is necessary to form a Bip Tr and a CMOS at the same time in one process to shorten the manufacturing period, and to reduce the device region by using the diffusion layer regions of the Bip Tr and the CMOS together.
ところで高性能なCMOSではゲート長が1μm程度のも
のを用いる。ゲート長が1μm近傍になると、ソース,
ドレイン間に強電界が加わりホットキャリアが発生し
て、MOS特性劣化の原因となる。その為一般的にドレイ
ン領域に、高濃度と低濃度領域を設けてソース・ドレイ
ン間の電界強度を緩和してホットキャリアの発生を抑え
るMOSトランジスタ構造が用いられている。BiCMOS集積
回路に於いても上述した対策を施したCMOS構造を用い
る。Incidentally, a high-performance CMOS having a gate length of about 1 μm is used. When the gate length approaches 1 μm, the source,
A strong electric field is applied between the drains to generate hot carriers, which causes deterioration of MOS characteristics. Therefore, a MOS transistor structure is generally used in which a high-concentration region and a low-concentration region are provided in the drain region to reduce the electric field intensity between the source and the drain to suppress generation of hot carriers. In the case of a BiCMOS integrated circuit, a CMOS structure in which the above measures are taken is used.
第3図は従来のBiCMOS集積回路の断面図である。 FIG. 3 is a sectional view of a conventional BiCMOS integrated circuit.
この従来例をその製造工程に沿って説明する。 This conventional example will be described along the manufacturing process.
図中に於いて1はp型シリコン基板、2はn型埋込
層、3はp型埋込層、4はn型エピタキシャル層、5は
pウェル、6は素子間を分離するフィールド絶縁膜であ
る。このような半導体チップの素子領域表面にゲート絶
縁膜7を設けBip Tr領域にベース層24を選択的に設け
る。In the drawing, 1 is a p-type silicon substrate, 2 is an n-type buried layer, 3 is a p-type buried layer, 4 is an n-type epitaxial layer, 5 is a p-well, and 6 is a field insulating film for separating elements. It is. The gate insulating film 7 is provided on the surface of the element region of such a semiconductor chip, and the base layer 24 is selectively provided on the Bip Tr region.
その後ゲート電極8,9を選択的に形成する。 Thereafter, gate electrodes 8, 9 are selectively formed.
次にゲート電極8をマスク材として第1のn型不純物
原子をイオン注入してnMOSの第1のソース・ドレイン領
域10−1,10−2を形成する。更に第1のn型不純物原子
より拡散速度の遅い第2のn型不純物原子を第1のn型
不純物原子より高濃度に、nMOSの第1のソース・ドレイ
ン領域にイオン注入してnMOSの第2のソース・ドレイン
領域11−1,11−2を形成する。Next, first n-type impurity atoms are ion-implanted using the gate electrode 8 as a mask material to form first source / drain regions 10-1 and 10-2 of the nMOS. Further, a second n-type impurity atom having a lower diffusion rate than the first n-type impurity atom is ion-implanted into the first source / drain region of the nMOS at a higher concentration than the first n-type impurity atom, to thereby form a second n-type impurity atom. Two source / drain regions 11-1 and 11-2 are formed.
次にnMOSと同様にして第1のp型不純物原子をイオン
注入してpMOSの第1のソース・ドレイン領域12−1,12−
2を形成し、更に第1のp型不純物原子より拡散速度の
遅い第2のp型不純物原子を第1のp型不純物原子より
高濃度にベース層24及びpMOSの第1のソース・ドレイン
領域にイオン注入してベース電極形成領域25,第2のソ
ース・ドレイン領域(13−1,13−2)を形成する。Next, the first p-type impurity atom is ion-implanted in the same manner as in the nMOS to form the first source / drain regions 12-1, 12- of the pMOS.
2 is formed, and a second p-type impurity atom having a lower diffusion rate than the first p-type impurity atom is more concentrated than the first p-type impurity atom in the base layer 24 and the first source / drain region of the pMOS. To form a base electrode forming region 25 and second source / drain regions (13-1, 13-2).
その後全面に層間絶縁膜20を設けて選択的に開孔窓を
形成し全面に多結晶シリコン膜14を形成して選択的にN
型不純物原子をイオン注入してエミッタ領域26を形成す
る。Thereafter, an interlayer insulating film 20 is provided on the entire surface, an opening window is selectively formed, and a polycrystalline silicon film 14 is formed on the entire surface, and N is selectively formed.
The emitter region 26 is formed by ion-implanting the type impurity atoms.
次に全面にアルミニウム等の金属膜を全面に被着して
選択的にアルミニウム及び多結晶シリコン膜を選択エッ
チして各電極を形成する。Next, a metal film such as aluminum is deposited on the entire surface, and the aluminum and polycrystalline silicon films are selectively etched to form respective electrodes.
上述した従来のBiCMOS集積回路は同一半導体基板上に
CMOS領域、及びBip Tr領域をそれぞれ独立に設けてCMOS
及びBip Trを形成していたので集積度の向上が困難であ
るという欠点がある。The above-mentioned conventional BiCMOS integrated circuit is mounted on the same semiconductor substrate.
CMOS area and Bip Tr area are provided independently, and CMOS
In addition, there is a disadvantage that it is difficult to improve the degree of integration because the Bip Tr is formed.
本発明のBiCMOS集積回路は、半導体チップ表面の第1
導電型半導体層上にゲート絶縁膜を介して設けられたゲ
ート電極及び前記ゲート電極直下部を挟んで選択的に設
けられた第2導電型低濃度半導体層と前記第2導電型低
濃度半導体層に設けられた第2導電型高濃度半導体層か
らなるソース(又はドレイン)領域を有するMOSトラン
ジスタと、前記第2導電型低濃度半導体層に前記第2導
電型高濃度半導体層と離れてて設けられた第1導電型エ
ミッタ領域を有するバイポーラ・トランジスタとを含む
というものである。The BiCMOS integrated circuit of the present invention has a first
A gate electrode provided on the conductive type semiconductor layer with a gate insulating film interposed therebetween, a second conductive type low-concentration semiconductor layer selectively provided with a portion immediately below the gate electrode therebetween, and the second conductive type low-concentration semiconductor layer A MOS transistor having a source (or drain) region composed of a second conductive type high concentration semiconductor layer provided in the second conductive type high concentration semiconductor layer and a second conductive type high concentration semiconductor layer provided in the second conductive type low concentration semiconductor layer A bipolar transistor having an emitter region of the first conductivity type.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図は本発明の第1の実施例を示す半導体チップの
断面図である。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.
図中A部分はnMOSであるが従来と同じ構造であるので
説明を省略する。B部分が本発明を用いて形成したpMOS
とnpnBip Trであり以後B部分について説明する。p型
シリコン基板1上にn型埋込層2、n型エピタキシャル
層4、エピタキシャル層4を選択酸化して素子領域を形
成してなる半導体チップ表面のn型エピタキシャル層4
上にゲート絶縁膜7を有している。又、選択的に形成し
たゲート電極8,9を有しゲート電極直下及びコレクタ電
極形成領域を除く部分(B)にボロン原子を例えば5×
10131/cm2程度イオン注入してp型低濃度半導体層12−
1,12−2が形成されている。更にp型低濃度半導体層12
−1,12−2にはそれぞれ選択的にフッ化ボロン原子を例
えば5×10151/cm2イオン注入してp型高濃度半導体層1
371,13−2が形成されている。Although the portion A in the figure is an nMOS, it has the same structure as the conventional one, so that the description is omitted. B part is a pMOS formed using the present invention
And npnBip Tr. The portion B will be described below. An n-type buried layer 2, an n-type epitaxial layer 4, and an n-type epitaxial layer 4 on the surface of a semiconductor chip formed by selectively oxidizing the epitaxial layer 4 to form an element region on a p-type silicon substrate 1.
A gate insulating film 7 is provided thereon. In addition, a portion (B) having selectively formed gate electrodes 8 and 9 and excluding the region immediately below the gate electrode and the region where the collector electrode is formed is doped with, for example, 5 × boron atoms.
About 10 13 1 / cm 2 ions are implanted and the p-type low-concentration semiconductor layer 12−
1,12-2 are formed. Further, the p-type low concentration semiconductor layer 12
-1 and 12-2 are selectively implanted with boron fluoride atoms, for example, at a concentration of 5 × 10 15 1 / cm 2.
371, 13-2 are formed.
その後に全面に層間絶縁膜20を形成して選択的にコレ
クタ,エミッタ,ベース,ソース,ドレイン,ゲートの
各々の開孔窓を形成する。この時ソース又はドレインの
開孔窓とベース開孔窓17−2は兼用しており一つしかな
い。次に全面に多結晶シリコン膜14を形成後ヒ素等から
なるN型の不純物原子を例えば1×10161/cm2選択的に
イオン注入してn型エミッタ領域15をp型低濃度半導体
層12−1にp型高濃度半導体層13−1と離して形成し、
全面にアルミニウム等の金属膜を被着し金属膜及び多結
晶シリコン膜を選択的にエッチングしてトランジスタの
各電極を形成し第1図に示す断面図の状態を有するBiCM
OS集積回路を得る。Thereafter, an interlayer insulating film 20 is formed on the entire surface to selectively form opening windows for the collector, the emitter, the base, the source, the drain, and the gate. At this time, the source or drain aperture window and the base aperture window 17-2 are also used and there is only one. Next, after a polycrystalline silicon film 14 is formed on the entire surface, N-type impurity atoms made of arsenic or the like are selectively ion-implanted, for example, at 1 × 10 16 1 / cm 2 to form an n-type emitter region 15 in a p-type low concentration semiconductor layer. 12-1 is formed apart from the p-type high concentration semiconductor layer 13-1;
A metal film such as aluminum is deposited on the entire surface, and the metal film and the polycrystalline silicon film are selectively etched to form the respective electrodes of the transistor. The BiCM having the cross-sectional view shown in FIG.
Obtain an OS integrated circuit.
本実施例においてはn型エピタキシャル層4をBip Tr
のコレクタ領域、pMOSのウェルと兼用し、p型低濃度半
導体層12−1をベース領域及びソース(又はドレイン)
領域と兼用し且電極も兼用しているので、従来のBiCMOS
集積回路と比べ大幅に集積度を向上する事ができる。In this embodiment, the n-type epitaxial layer 4 is
And the p-type low-concentration semiconductor layer 12-1 is also used as a base region and a source (or drain).
Because it is also used as an area and also as an electrode, the conventional BiCMOS
The degree of integration can be greatly improved as compared with an integrated circuit.
第2図は本発明の第2の実施例を示す半導体チップの
断面図である。FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
図中A′部分がnMOS,B′部分がnpnBip TrとpMOSであ
り以後B′部分についてのみ説明する。In the figure, the A 'portion is an nMOS, the B' portion is an npnBip Tr and a pMOS, and only the B 'portion will be described below.
p型シリコン基板1上にn型埋込層2,n型エピタキシ
ャル層4を形成するまでは第1の実施例と同様である。The steps up to the formation of the n-type buried layer 2 and the n-type epitaxial layer 4 on the p-type silicon substrate 1 are the same as in the first embodiment.
次に選択酸化により、コレクタ電極形成領域及びMOST
形領域を分離して形成し、選択的にMOS領域のみゲート
絶縁膜を形成する。次に全面に高濃度のリン原子を含ん
だ多結晶シリコン膜を選択的に形成してコレクタ22及び
ゲート電極8,9を形成する。Next, by selective oxidation, the collector electrode formation region and MOST
The gate region is formed separately and the gate insulating film is selectively formed only in the MOS region. Next, a collector 22 and gate electrodes 8 and 9 are formed by selectively forming a polycrystalline silicon film containing a high concentration of phosphorus atoms on the entire surface.
次にゲート電極直下を除くMOST形成領域に低濃度のボ
ロン原子をイオン注入してp型低濃度半導体層12−1、
…を形成する。Next, low-concentration boron atoms are ion-implanted into the MOST formation region except immediately below the gate electrode to form a p-type low-concentration semiconductor layer 12-1,
... is formed.
次に全面に気相成長酸化膜を形成し異方性エッチを行
なってコレクタ及びゲート電極側壁に絶縁膜のサイドウ
ォール21を厚さ0.1〜0.3μm形成する。Next, a vapor growth oxide film is formed on the entire surface, and anisotropic etching is performed to form a sidewall 21 of an insulating film on the collector and gate electrode side walls with a thickness of 0.1 to 0.3 μm.
その後p型低濃度半導体層12−1、…に選択的にフッ
化ボロン原子を高濃度にイオン注入してp型高濃度半導
体層13−1、…を形成し全面に層間絶縁膜を形成する。Then, boron fluoride atoms are selectively ion-implanted at a high concentration into the p-type low-concentration semiconductor layers 12-1,... To form the p-type high-concentration semiconductor layers 13-1,. .
次に層間絶縁膜に選択的に開孔窓を形成してコレク
タ,エミッタ,ベース,ソース,ドレイン,ゲートの各
電極を形成する為の開孔窓を形成する。この時ソース又
はドレインの開孔窓とベースの開孔窓は兼用している。
次に全面に多結晶シリコン膜を形成後ヒ素等のn型不純
物原子を選択的にイオン注入してp型低濃度半導体層12
−1にp型高濃度半導体層1371と離してn型エミッタ領
域15を形成する。Next, an opening window is selectively formed in the interlayer insulating film to form an opening window for forming the collector, emitter, base, source, drain, and gate electrodes. At this time, the aperture window of the source or drain and the aperture window of the base are also used.
Next, after a polycrystalline silicon film is formed on the entire surface, n-type impurity atoms such as arsenic are selectively ion-implanted to form a p-type low-concentration semiconductor layer 12.
The n-type emitter region 15 is formed at a distance of -1 from the p-type high concentration semiconductor layer 1371.
次にアルミニウム等の配線層を被着後にアルミニウ
ム、多結晶シリコン膜を同時にエッチングしてコレク
タ,エミッタ,ベース,ソース,ドレイン,ゲートの各
電極を形成し第2図に示す第2の実施例の断面図の状態
となる。Next, after a wiring layer of aluminum or the like is deposited, the aluminum and polycrystalline silicon films are simultaneously etched to form collector, emitter, base, source, drain, and gate electrodes. The second embodiment shown in FIG. The state is as shown in the sectional view.
本実施例によれば第1の実施例と同様にn型エピタキ
シャル層4をコレクタ領域、ウェルと兼用し、p型低濃
度半導体層をベース領域及びソース(又はドレイン)領
域と兼用している為大幅に素子領域を縮小する事ができ
る。According to this embodiment, as in the first embodiment, the n-type epitaxial layer 4 also serves as a collector region and a well, and the p-type low-concentration semiconductor layer also serves as a base region and a source (or drain) region. The element area can be greatly reduced.
又コレクタ引出領域27とMOS形成領域をフィールド絶
縁膜により分離している為p型低濃度半導体層形成後、
この層の不純物原子がコレクタ引出領域まで拡散する事
を防止でき、歩留りの高いBiCMOS集積回路を得る事がで
きる。Also, since the collector extraction region 27 and the MOS formation region are separated by a field insulating film, after forming the p-type low concentration semiconductor layer,
It is possible to prevent impurity atoms in this layer from diffusing to the collector extraction region, and to obtain a BiCMOS integrated circuit with a high yield.
又ゲート電極の側壁とはサイドウォールを形成してい
る為p型低濃度半導体層とp型高濃度半導体層間の距離
を安定に形成できるのでホットキャリアの発生等を確実
に抑える事ができ信頼性上優れたBiCMOS集積回路を得る
事ができる。Further, since the side wall is formed with the side wall of the gate electrode, the distance between the p-type low-concentration semiconductor layer and the p-type high-concentration semiconductor layer can be formed stably. An excellent BiCMOS integrated circuit can be obtained.
以上説明したように本発明は、CMOSの低濃度ソース
(又はドレイン)領域内にBip Trのエミッタ領域を形成
することにより、素子形成領域の大きさがCMOS集積回路
とほぼ同等の大きさとなり、集積度が高く且つBip Trと
同等の高周波特性,CMOSと同等の低消費電力を有するBiC
MOS集積回路を得る事ができる。As described above, according to the present invention, by forming the emitter region of the Bip Tr in the low-concentration source (or drain) region of the CMOS, the size of the element formation region becomes substantially equal to the size of the CMOS integrated circuit. BiC with high integration, high frequency characteristics equivalent to Bip Tr, and low power consumption equivalent to CMOS
A MOS integrated circuit can be obtained.
第1図は本発明の第1の実施例を示す半導体チップの断
面図、第2図は本発明の第2の実施例を示す半導体チッ
プの断面図、第3図は従来のBiCMOS集積回路を示す半導
体チップの断面図である。 1……p型シリコン基板、2……n型埋込層、3……p
型埋込層、4……n型エピタキシャル層、5……pウェ
ル、6……フィールド絶縁膜、7……ゲート絶縁膜、8
……nMOSのゲート電極、9……pMOSのゲート電極、10−
1,10−2……n型低濃度半導体層、11−1,11−2……n
型高濃度半導体層、12−1,12−2……p型低濃度半導体
層、13−1,13−2……p型高濃度半導体層、14……多結
晶シリコン膜、15……n型エミッタ領域、16−1,16−2
……ゲートのアルミニウム電極、17−1……ソース又は
ドレイン電極、17−2……ソース又はドレインとベース
を兼用した電極、18……エミッタ電極、19……コレクタ
電極、20……層間絶縁膜、21……サイドウォール、22…
…ゲート電極と同時に形成したコレクタ電極、23……ベ
ース電極、24……ベース層、25……ベース電極形成領
域、26……エミッタ領域、27……コレクタ引出領域。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention, and FIG. 3 shows a conventional BiCMOS integrated circuit. It is sectional drawing of the semiconductor chip shown. 1 ... p-type silicon substrate, 2 ... n-type buried layer, 3 ... p
Embedded layer, 4 n-type epitaxial layer, 5 p-well, 6 field insulating film, 7 gate insulating film, 8
…… nMOS gate electrode, 9… pMOS gate electrode, 10−
1,10-2... N-type low concentration semiconductor layer, 11-1, 11-2.
-Type high-concentration semiconductor layer, 12-1, 12-2 ... p-type low-concentration semiconductor layer, 13-1, 13-2 ... p-type high-concentration semiconductor layer, 14 ... polycrystalline silicon film, 15 ... n Type emitter region, 16-1, 16-2
... aluminum electrode of gate, 17-1 ... source or drain electrode, 17-2 ... electrode serving as source or drain and base, 18 ... emitter electrode, 19 ... collector electrode, 20 ... interlayer insulating film , 21 ... sidewall, 22 ...
... a collector electrode formed simultaneously with the gate electrode, 23 ... a base electrode, 24 ... a base layer, 25 ... a base electrode formation region, 26 ... an emitter region, 27 ... a collector extraction region.
Claims (1)
にゲート絶縁膜を介して設けられたゲート電極及び前記
ゲート電極直下部を挟んで選択的に設けられた第2導電
型低濃度半導体層と前記第2導電型低濃度半導体層に設
けられた第2導電型高濃度半導体層からなるソース(又
はドレイン)領域を有するMOSトランジスタと、前記第
2導電型低濃度半導体層に前記第2導電型高濃度半導体
層と離れて設けられた第1導電型エミッタ領域を有する
バイポーラ・トランジスタとを含むことを特徴とするBi
CMOS集積回路。1. A gate electrode provided on a first conductive type semiconductor layer on a surface of a semiconductor chip with a gate insulating film interposed therebetween, and a second conductive type low-concentration semiconductor selectively provided immediately below the gate electrode. A MOS transistor having a source (or drain) region composed of a layer and a second conductive type high concentration semiconductor layer provided in the second conductive type low concentration semiconductor layer; A bipolar transistor having a conductive type high-concentration semiconductor layer and a first conductive type emitter region provided at a distance therefrom.
CMOS integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63308209A JP2745597B2 (en) | 1988-12-05 | 1988-12-05 | BiCMOS integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63308209A JP2745597B2 (en) | 1988-12-05 | 1988-12-05 | BiCMOS integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02153561A JPH02153561A (en) | 1990-06-13 |
JP2745597B2 true JP2745597B2 (en) | 1998-04-28 |
Family
ID=17978235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63308209A Expired - Lifetime JP2745597B2 (en) | 1988-12-05 | 1988-12-05 | BiCMOS integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2745597B2 (en) |
-
1988
- 1988-12-05 JP JP63308209A patent/JP2745597B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02153561A (en) | 1990-06-13 |
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