JP2740808B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a grooved element isolation structure and a method of manufacturing the same. [Prior Art] FIG. 4 is a diagram showing a DRAM having a trenched capacitor as an information charge storage region as an example of a conventional semiconductor device having this kind of element isolation structure. 2 is a trench dug in the semiconductor substrate 1, 3 is a first diffusion layer having the same conductivity type as the semiconductor substrate 1 formed at the bottom of the trench 2, 4 is an element isolation oxide film formed at the bottom of the trench 2 , 5
Denotes a semiconductor substrate 1 formed on the side and flat portions of the groove 2
A diffusion layer 6 having a conductivity type opposite to that of the trench 2; a thin oxide film 6 formed on the side wall and the plane of the groove 2; and a charge accumulation layer 7 formed on the bottom, the side wall and the plane of the groove 2 by polysilicon or the like. For the cell plate. A charge accumulation region is formed by the second diffusion layer 5, the thin oxide film 6, and the cell plate 7, and the charge accumulation region is formed by the first diffusion layer 3.
And the thick oxide film 4 are separated into two and each belongs to a different element. Further, 12 is a transfer gate (word line) formed of polysilicon or a high melting point metal polycide or a high melting point metal, 13 is a third diffusion layer having a conductivity type opposite to that of the semiconductor substrate 1, and 14 is a wiring layer between the wiring layers. An insulating film, 15 is a contact hole formed in the insulating film 14, and 16 is a bit line made of aluminum or a high melting point metal polycide or a high melting point metal. Transfer gate 12
A switching transistor is formed by the diffusion layer 13 on both sides of the switching transistor, and the charge transmitted from the bit line 16 is carried to the charge storage region via the contact hole 15 and the switching transistor and is stored therein. Also, conversely,
The charge stored in the charge storage region is drawn out to the bit line via the switching transistor and the contact hole. Although not shown in FIG. 4, after the cell plate 7 is formed, the trench 2 must be buried, the switching transistor must be formed stably in terms of process, and the buried portion must be planarized to improve its electrical characteristics. Representative examples of the process are shown in FIGS. 5 (a), (b) and (c). First, FIG. 5 (a) shows that after the cell plate 7 is formed, the groove 2 is buried with the oxide film 11 by a method such as low pressure CVD (Chemical Vapor Deposition), and is flattened by the etch back method. It is. Next, FIG. 5 (b) shows that after the cell plate 7 is formed, the trench 2 is buried with polysilicon 11 by a method such as low-pressure CVD and planarized by an etch-back method. Finally, FIG. 5 (c) shows that after forming the cell plate 7, a relatively thin oxide film 8 is deposited on the entire surface of the semiconductor substrate by, for example, a low pressure CVD method, the trench 2 is buried with polysilicon 9, and flattened by an etch back method. It is a thing. When the filling of the trench 2 and the planarization are completed, the process proceeds to the etching of the cell plate and the formation of the switching transistor. [Problems to be Solved by the Invention] Since the conventional semiconductor device is configured as described above, there are the following problems. First, in FIG. 5 (a), the embedding and flattening are performed by the CVD oxide film 1.
Is done by one. The CVD oxide film has poor coverage, so that a hollow is formed in the oxide film 11, so that complete burying and flattening cannot be expected, which greatly hinders realization of the process stabilization after the formation of the switching transistor. Further, the oxide film causes a large stress in the trench 2, and therefore, the stress between the diffusion layer 5 and the oxide film 6 increases the defect density and the interface state, thereby increasing the junction leakage and lowering the oxide film breakdown voltage. Next, in FIG. 5 (b), the buried flattening is performed by CVD polysilicon 1
This is done by 1 '. The CVD polysilicon has a good coverage and a small stress on the groove 2.
Therefore, complete embedding can be performed without applying stress to the groove 2. However, since both the cell plate 7 and the embedded material 11 'are made of polysilicon, it is impossible to detect the end point at the time of the etch back. Therefore, the cell plate 7 is etched at the time of the etch back, and the expected thickness of the cell plate is reduced. If not available or embedded polysilicon 1
There is a case where the buried polysilicon 11 'remains on the cell plate 7 because 1' cannot be completely flattened, and the flattening process by the etch back is not performed stably. Finally, in FIG. 5 (c), the burying flattening is performed by a multilayer structure of the CVD oxide film 8 and the CVD polysilicon. As described above, the CVD oxide film 8 has a poor coverage and a large stress on the groove 2, but since the CVD oxide film 8 is deposited relatively shallow, these two effects are extremely small. Since the actual embedding is performed by the CVD polysilicon 9, complete embedding is performed with good coverage and low stress. Further, regarding the flattening of the buried polysilicon 9 by etch-back, the CVD oxide film 9 serves as a monitor of the end point detection at the time of the etch-back, and the flattening of the buried polysilicon 9 by the etch-back can be stably performed in a process. it can. The thickness of the CVD oxide film 8 may be any thickness that has a function of detecting an end point during etch back. Thus, in terms of process, this multilayer structure is very convenient for burying and flattening. However, the polysilicon 9 buried and flattened in a device is in a floating state, and is affected by an upper layer structure of the device, for example, a potential change of a word line or a bit line. Although the cell plate 7 is fixed at a certain potential, the polysilicon used as the cell plate material has a relatively large sheet resistance. Therefore, the influence of the potential change caused by the word lines and the bit lines of the buried flattened polysilicon 9 is eliminated. Immediately they cannot be countered and are affected. Then, the diffusion layer 3 under the element isolation oxide film 4 is inverted, and the diffusion layers 5 on both sides of the groove 2 are inverted.
Are connected, and inter-cell interference occurs. As described above, in the conventional semiconductor device, there is a problem that it is very difficult to satisfy both a process requirement and a device requirement. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In a grooved type element, a groove is completely buried in a state of low stress, and flattening is performed by a method stable in manufacturing. Accordingly, it is an object of the present invention to provide a semiconductor device which can satisfy a process requirement and can also avoid a deterioration in device characteristics due to a floating electrode of an embedded flattening material. [Means for Solving the Problems] A semiconductor device according to the present invention has a main surface, a groove formed on the main surface, and a main surface extending from the inner surface of the groove to the periphery of the opening. A plurality of diffusion regions formed,
And on a semiconductor substrate having an element isolation region formed at the bottom of the groove so as to be sandwiched by the plurality of diffusion regions, a first insulating film is formed on the groove formed on the substrate and a peripheral portion of the groove. A first conductive layer such as a cell plate formed through the first conductive layer, and a flattened and buried surface of the substrate through a second insulating film in a groove formed by the first conductive layer. And a third conductive layer such as a polysilicon-based electrode material. [Operation] Polysilicon deposited on the entire surface of a semiconductor substrate connecting a second conductive layer such as a polysilicon-based buried material and a first conductive layer such as a polysilicon-based cell plate in the present invention. The third conductor layer, such as a system electrode material, prevents the second conductor layer, such as buried polysilicon, from floating, so that the second conductor layer, such as buried polysilicon, becomes a word line or a bit line. Is made less susceptible to influences. An embodiment of the present invention will be described below with reference to FIG. In the figure, 1 is a semiconductor substrate, 2 is a trench dug in the semiconductor substrate 1, 3 is a first diffusion layer of the same conductive type ion as the semiconductor substrate 1 formed in the bottom of the trench 2, and 4 is a bottom of the trench 2. The formed element isolation oxide film 5 has a second diffusion layer having a conductivity type opposite to that of the semiconductor substrate 1 formed on the side wall and the plane of the trench 2, and has a second diffusion layer 6 formed on the side wall and the plane of the groove 2. The thin oxide film 7 is a cell plate formed of polysilicon or the like on the bottom and side walls of the trench 2 and on the flat surface thereof. 8 is a relatively thin oxide film deposited on the entire surface of the semiconductor substrate by CVD or the like, 9 is a buried and flattened polysilicon material, and 11 is a polysilicon electrode for connecting the cell plate 7 and the buried polysilicon. Material. Next, the process flow will be described. FIG. 2 is a cross-sectional view at a main stage for explaining an embodiment of the present invention, and the reference numerals are the same as those in FIG. First, as shown in FIG. 2A, a groove 2 is formed on a semiconductor substrate 1 by using anisotropic etching, and an oxide film 6 is formed.
After being formed by CVD, heat treatment, etc., the cell plate 7
Is formed by, for example, a CVD method, and then an oxide film 9 is formed by a CVD method or the like, and then polysilicon is formed by a CVD method as a buried second diffusion layer 5, and then anisotropic etching or the like is used. The structure shown in FIG. 2 (b) is formed by flattening by etching back, and the oxide film 4 is removed by anisotropic etching or isotropic etching.
10 is deposited by a CVD method or the like (FIG. 2C), patterning is performed by a photoengraving process, and then a gate insulating film, a gate electrode wiring and the like are deposited by a CVD method or the like. In the above embodiment, the details of the present invention have been described with respect to the trench type element isolation structure, but the same effect can be obtained also with the trench type capacitor structure as shown in FIG. [Effects of the Invention] As described above, according to the present invention, on a semiconductor substrate having a main surface and a groove, the groove formed on the substrate and the peripheral portion of the groove are formed with the first insulating film interposed therebetween. A first conductor layer such as a formed cell plate and a trench formed by the first conductor layer are planarized and embedded to the surface of the substrate via a second insulating film via a second insulating film. A structure in which the third conductor layer such as a polysilicon-based electrode material is connected between the second conductor layer and the second conductor layer has a good coverage, a small stress applied to the groove, and an etch back end point that can be detected. Since the planarization can be realized and the floating of the polysilicon caused by the buried flattening can be avoided, the buried flattening of the trench can be stably realized in the process, and the buried flattening is applied to the device. Affect This has an effect that a semiconductor device having good performance can be obtained as a device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing the periphery of a groove of a semiconductor device according to one embodiment of the present invention, and FIG. 2 is a diagram showing a manufacturing process according to one embodiment of the present invention; FIG. 3 is a sectional view showing the periphery of a groove of a semiconductor device according to another embodiment of the present invention. FIG. 4 is a sectional view showing a conventional semiconductor layer device, and FIG.
FIGS. 1A, 1B and 1C are cross-sectional views showing the periphery of a groove of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is a trench, 3 is a first diffusion layer, 4 is an element isolation oxide film, 5 is a second diffusion layer, 6 is an oxide film, 7 is a cell plate, 8 is an oxide film, 9 is a polysilicon material, 10 is an electrode material, 11 is an oxide film, 11 'is polysilicon, 12 is a transfer gate, 13 is a third diffusion layer, 14
Is an insulating film, 15 is a contact hole, and 16 is a bit line. In the drawings, the same reference numerals indicate the same or corresponding parts.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Teruo Shibano               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd. (72) Inventor Masao Nagatomo               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd. (72) Inventor Yoshiki Okumura               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd. (72) Inventor Shunji Katayama               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd. (72) Inventor Ohno               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd. (72) Inventor Hiroyuki Morita               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd.                (56) References JP-A-63-4664 (JP, A)                 JP-A-61-244043 (JP, A)                 JP-A-62-101034 (JP, A)                 JP-A-62-42432 (JP, A)

Claims (1)

(57) [Claims] A main surface, a groove formed on the main surface, a plurality of diffusion regions formed on the main surface to extend from an inner surface of the groove to around the opening, and the plurality of diffusions on a bottom of the groove. A substrate having an element isolation region formed so as to be sandwiched between regions, a first insulating film formed on a surface inside the groove and on the main surface, and on the first insulating film; and A first conductor layer formed on a surface inside the groove and around an opening of the groove on the surface;
A second insulating film formed on the inner surface of the groove formed by the conductive layer, and a second conductive layer formed inside the groove formed by the second insulating film; The first conductor layer on the surface, the surface exposed portion of the second insulating film, and the surface exposed portion of the second conductor layer form a flat surface, and are provided so as to cover the flat surface. A third conductor layer, wherein the third conductor layer fixes the potentials of the first conductor layer and the second conductor layer to be the same. 2. 2. The semiconductor device according to claim 1, wherein an oxide film is used as said first and second insulating films. 3. 2. The method according to claim 1, wherein said first conductive layer, said second conductive layer, and said third conductive layer are formed of polysilicon.
13. The semiconductor device according to item 9. 4. A main surface, a groove located on the main surface, a plurality of diffusion regions located around an inner surface and an opening of the groove of the main surface, and a plurality of diffusion regions located at the bottom of the groove between the plurality of diffusion regions. Preparing a substrate having an element isolation region, forming a first insulating film on the inner surface and the main surface of the groove, on the insulating film and on the inner surface of the groove and the main surface; Forming a first conductive layer around the opening of the groove, forming a second insulating film on an inner surface of the groove formed by the first conductive layer, forming the second insulating film; Forming a second conductive layer inside the groove, a first exposed portion of the first conductive layer and the second insulating film on a main surface of the substrate, and a first exposed portion of the second conductive layer; And flattening the first conductive layer, the second insulating film, and the second conductive layer on the flattened first conductive layer, The method of manufacturing a semiconductor device forming a conductor layer. 5. 5. The method according to claim 4, wherein an oxide film is used as said first and second insulating films. 6. 5. The method according to claim 4, wherein said first conductive layer, said second conductive layer, and said third conductive layer are formed of polysilicon.
13. The method for manufacturing a semiconductor device according to the above item.