JP2740046B2 - Manufacturing method of pin grid array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an improvement in a method of manufacturing a pin grid array.

(Prior Art) As is well known, IC chips are widely used as various electronic circuit elements. For example, there is known a functional circuit element called a pin grid array, which is configured by mounting and mounting an IC chip formed as a bare chip on a substrate having many pins.

By the way, the above-mentioned pin grid array is generally manufactured as follows. That is, a bare chip (IC chip) is mounted on a predetermined board (circuit board) surface, and the I / O pad group of the bare chip and the pad group of the corresponding board are
A desired grid array is manufactured by connecting them by wire bonding.

(Problems to be Solved by the Invention) However, the above-described method of manufacturing a pin grid array has the following inconveniences in implementation. In other words, an IC chip (bare chip) mounted on a predetermined multi-pin board surface
Because the I / O pads of the board and the lead terminals of the board are connected by wire bonding, it is difficult to perform the wire bonding operation to increase the size of the bare chip or increase the number of I / O pads (narrow pitch). If electrical inspection is not possible, and even if a failure is determined in the electrical inspection after the pin grid array configuration, it is difficult to replace (repair) the mounted bare chip, and in fact it must be discarded as a defective product There are often.

The complexity of the operation and the difficulty of repair in the manufacturing process as described above are due to the large size (large capacity) or the large number of pins of IC chips in this kind of pinglit array.
This has made it more difficult to cope with a significant increase in the number of I / O pads on the IC chip and a reduction in the pitch of lead terminals on the substrate. Under the current situation where the number of electrode pads is increased or the pitch is reduced due to the increase in the capacity of IC chips and the like, and the miniaturization and the pitch of the inner leads are being demanded, this can be said to be an important issue.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a method for easily manufacturing a highly reliable pinglit array that can be repaired without causing a positional shift or the like, and can be repaired by detaching and replacing an IC chip. Aim.

[Constitution of the Invention] (Means for Solving the Problems) According to a method for manufacturing a pin grid array of the present invention, a step of forming a curable adhesive layer on a predetermined surface of a substrate with multiple pins, A step of arranging a TAB-formed bare chip on the adhesive layer and temporarily fixing the TAB with the adhesive layer, and sequentially bonding the I / O lead group of the temporarily fixed TAB-formed bare chip to a pad group on the substrate surface. And electrically hardening the adhesive layer after performing a predetermined electrical test on the connected component.

(Operation) According to the present invention as described above, in the step of sequentially bonding (single point bonding) the I / O leads of the corresponding TAB-formed bare chip and the lead terminals of the substrate, the TAB-formed bare chip includes: Since the adhesive is temporarily fixed to a predetermined position on the substrate surface by an adhesive, required electric connection can be easily achieved without causing displacement or the like. In this state, a predetermined electrical inspection is performed, and if a functional defect is detected in the mounted TAB-formed bare chip, the TAB-formed bare chip is only temporarily fixed to the substrate. Since it is not provided, it can be easily replaced and replaced. Moreover, since the IC chip is formed into a TAB in advance, single-point bonding to a pad on the substrate can be easily performed. That is, irrespective of the size or capacity of the IC chip or the narrow pitch pad of the substrate, the required connection can be achieved relatively easily without complexity.

Embodiment An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 to FIG. 3 are cross-sectional views of essential parts schematically showing an embodiment of a method of manufacturing a pin grid array according to the present invention for each stage.

First, a required multi-pin board (circuit board) 1 and a required IC chip as shown in FIG.
Bonded) bare chips are prepared.

Then, as shown in FIG.
A predetermined curable adhesive such as an epoxy resin-based conductive adhesive layer 2 is applied and formed on a predetermined surface, that is, on a die pad 1a on which an IC chip is mounted. In the drawing, 1b indicates a pad, and 1c indicates a lead pin.

Thereafter, the conductive adhesive layer 2 of the multi-pin substrate 1 is formed.
On the surface, a bare chip 3 in which the required IC chip is converted into a TAB
Are aligned and temporarily fixed by the conductive adhesive layer 2. In this state, the I / O leads 3a of the TAB-formed bare chip 3 are sequentially bonded (single point bonding) to the corresponding pads 1b on the surface of the multi-pin substrate 1 to perform electrical connection. FIG. 3 shows a state in which each I / O lead 3a of the bare chip 3 formed into a TAB is bonded and electrically connected to a corresponding pad 1b on the surface of the multi-pin substrate 1 in FIG. Indicates a tape body in which the IC chip is formed into a TAB.

As described above, when the TAB-formed bare chip 3 is arranged on the predetermined surface of the multi-pin substrate 1 and the required electrical connection is made, the intermediate structure which forms this structure, that is, the pink lid array, is formed. A predetermined electrical test is performed on the product. In the electrical inspection, if no functional defect or the like is detected in the TAB-formed bare chip 3, as the next step, the intermediate product is applied to the die pad 1a surface of the multi-pin substrate 1 by performing, for example, heat treatment. The formed conductive adhesive layer 2 is thermally cured, and
The bare chip 3 into a die pad on the substrate 1 with multiple pins
A desired pin grid array or package can be obtained by being fixedly integrated with the 1a surface.

On the other hand, in the electrical inspection, when a functional defect or the like is detected in the TAB-formed bare chip 3, the following operation is performed. That is, the TAB-formed bare chip 3 temporarily fixed by the uncured conductive adhesive layer 2 is detached and replaced (repaired), and the required electrical connection is again performed by single-point bonding to perform an electrical inspection. If no functional defect or the like is detected in the TAB-formed bare chip 3, as the next step, the intermediate product is subjected to, for example, heat treatment to form a conductive layer formed on the surface of the die pad 1 a of the multi-pin substrate 1. The bare chip 3 obtained by thermally curing the adhesive layer 2 and forming the TAB is used as the substrate 1 with multiple pins.
A desired pin grid array or package can be obtained by bonding and integrating with the surface of the die pad 1a.

In the above description, the adhesive layer is formed of a conductive adhesive, but may be formed of a non-conductive adhesive, or the adhesive may be a thermosetting material other than an epoxy resin. Good. Further, the number of TAB-formed bare chips to be mounted may be plural, and the structure is naturally not limited to the above example.

[Effects of the Invention] As described above, according to the pin grid array manufacturing method of the present invention, a TAB-formed bare chip positioned and disposed on a predetermined area surface of a multi-pin substrate is formed of a curable adhesive. The required electrical connection is made to the multi-pinned substrate while being temporarily fixed by the layers. In other words, the required electrical connection can be accurately and accurately achieved by single point bonding without causing a positional shift or the like with respect to a predetermined position. Thus, the electrical inspection of the finally configured pin grid array is performed before the final adhesion and fixing of the TAB-formed bare chip,
At this point, if it is found that the bare chip made into TAB is defective, the detachable replacement (repair) can be easily performed. Thus, the method of the present invention is mass-produced without requiring complicated operations, and can be easily repaired in the manufacturing process and can avoid waste of materials (improvement of yield). I / O
This can be said to be suitable for manufacturing a pin grid array for mounting a large-sized IC chip having a large number of leads and a narrow lead pitch.

[Brief description of the drawings]

FIGS. 1, 2 and 3 schematically show an embodiment of a method for manufacturing a pinlit array according to the present invention. FIG. 1 is a cross-sectional view of a multi-pin substrate to be used. FIG. 3 is a cross-sectional view showing a state in which an adhesive layer is applied and formed on a predetermined surface of a substrate with multiple pins, and FIG. 3 is a cross-sectional view showing a state in which single-point bonding is performed in the method of manufacturing a pinlit array according to the present invention. 1 ... board with many pins 1a ... die pad of board with many pins 1b ... pad of board with many pins 1c ... lead pin of board with many pins 2 ... adhesive layer 3 ... bare chip made into TAB 3a ... TAB-formed bare chip I / O leads 3b TAB-formed bare chip tape body 2 Mechanism for holding IC chip by suction 3 IC chip

Claims (1)

(57) [Claims] 1. A step of applying and forming a curable adhesive layer on a predetermined surface of a substrate with multiple pins, disposing a TAB-formed bare chip on the applied adhesive layer, and temporarily fixing the bare chip with the adhesive layer. A step of sequentially bonding and electrically connecting the I / O leads of the temporarily fixed TAB-formed bare chip to the pads on the substrate surface, and a predetermined electrical connection for the connected component. Curing the adhesive layer after performing the inspection.