JP2001135658A - Method and system for assembling electronic device - Google Patents

Method and system for assembling electronic device

Info

Publication number
JP2001135658A
JP2001135658A JP31620999A JP31620999A JP2001135658A JP 2001135658 A JP2001135658 A JP 2001135658A JP 31620999 A JP31620999 A JP 31620999A JP 31620999 A JP31620999 A JP 31620999A JP 2001135658 A JP2001135658 A JP 2001135658A
Authority
JP
Japan
Prior art keywords
substrate
electronic component
chip
assembling
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31620999A
Other languages
Japanese (ja)
Inventor
Katsunao Takehara
克尚 竹原
Takeru Nakagawa
長 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Towa Corp
Original Assignee
Towa Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Towa Corp filed Critical Towa Corp
Priority to JP31620999A priority Critical patent/JP2001135658A/en
Priority to US09/705,239 priority patent/US6358776B1/en
Priority to KR1020000065501A priority patent/KR20010070191A/en
Priority to TW089123509A priority patent/TW479013B/en
Publication of JP2001135658A publication Critical patent/JP2001135658A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

PROBLEM TO BE SOLVED: To assemble an electronic device efficiently with high dimensional accuracy of sealing resin when it is assembled by mounting a chip on a substrate, and then resin sealing and burn-in of the chip. SOLUTION: A chip 2 is hot pressed onto a substrate 1 by means of a tool 3, a chip side electrode 18 is connected with a substrate side electrode 5 through bumps 4, the substrate 1 is mounted on the spotting face P.L. of upper and lower dies 20, 21, a cavity 24 formed by clamping the upper and lower dies 20, 21 is evacuated through an exhaust pipe 25 and molten resin 26 is injected into the cavity 24 and cured to form sealing resin 8. Subsequently, the substrate 1 is pressed against a test board 10 in an atmosphere of a specified temperature and the operation of an electronic device comprising a unit region 7 of the substrate 1 and the chip 2 is inspected by supplying a predetermined electric signal to the chip 2 from the test board 10 through an outer electrode 19 before the substrate 1 is cut along an imaginary line 9 to complete an electronic device. According to the method, a plurality of chips 2 can be resin sealed accurately can be burnt-in processed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップ等の
チップ状素子（以下、チップという。）を基板に装着し
て電子部品を組み立てる電子部品の組立方法及び組立装
置であり、特に、効率的に電子部品を組み立てる組立方
法及び組立装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an assembling method and an assembling apparatus for an electronic component in which a chip-like element (hereinafter, referred to as a chip) such as a semiconductor chip is mounted on a substrate to assemble the electronic component. The present invention relates to an assembling method and an assembling apparatus for assembling electronic components.

【０００２】[0002]

【従来の技術】従来、複数の領域を有する基板に対し
て、各領域にそれぞれチップを装着して電子部品を製造
する場合には、次のようにして組み立てていた。まず、
各領域にそれぞれチップを装着し、各チップと各領域と
がそれぞれ有する電極同士を電気的に接続する。次に、
ディスペンサを使用して、各領域ごとに液化樹脂を滴下
する。次に、液化樹脂を硬化させて、基板の各領域にお
いてそれぞれチップを樹脂封止する。次に、基板を切断
して、１個の領域に１個のチップが樹脂封止された電子
部品を形成する。最後に、テストボードを使用して、個
々の電子部品に対して、所定の温度雰囲気中に放置した
状態で通電させるバーンインと動作試験とを行って、不
良品をスクリーニングして良品を得ている。2. Description of the Related Art Heretofore, when a chip having a plurality of areas is mounted on each area to manufacture an electronic component, the electronic parts are assembled as follows. First,
A chip is mounted on each area, and electrodes of each chip and each area are electrically connected. next,
Using a dispenser, the liquefied resin is dropped in each area. Next, the liquefied resin is cured, and the chip is resin-sealed in each region of the substrate. Next, the substrate is cut to form an electronic component in which one chip is resin-sealed in one region. Finally, using a test board, a burn-in and an operation test are performed on each of the electronic components while leaving them in a predetermined temperature atmosphere, and defective products are screened to obtain non-defective products. .

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来の電子部品の組立によれば、基板の各領域にチップを
樹脂封止する際に、１個のチップごとに液化樹脂を滴下
して硬化させる。したがって、樹脂封止に時間がかかる
ので、組立の効率が低いという問題があった。また、基
板を切断した後に、個々の電子部品の状態でバーンイン
と動作試験とを行う。したがって、電子部品を搬送して
テストボードのソケットに着脱する工数や、良品の電子
部品を選別しトレイまで搬送して積載する工数等が必要
となるので、これらの点からも組立の効率が低いという
問題があった。更に、滴下した液化樹脂を硬化させるの
で、樹脂の粘度や硬化条件等の管理が不十分な場合に
は、硬化した樹脂の寸法精度が低いという問題があっ
た。However, according to the above-mentioned conventional assembly of electronic components, when chips are resin-sealed in the respective regions of the substrate, a liquefied resin is dropped and hardened for each chip. . Therefore, there is a problem that the efficiency of assembly is low because it takes time to seal the resin. After the substrate is cut, burn-in and an operation test are performed on the individual electronic components. Therefore, man-hours for transporting the electronic components and attaching and detaching them to and from the socket of the test board, and steps for selecting good-quality electronic components, transporting them to the tray, and loading them are required. There was a problem. Further, since the dropped liquefied resin is cured, there is a problem that the dimensional accuracy of the cured resin is low when the viscosity of the resin, the curing conditions, and the like are insufficiently controlled.

【０００４】本発明は、上述の課題を解決するためにな
されたものであり、寸法精度に優れた電子部品を効率よ
く製造することができる電子部品の組立方法及び組立装
置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide an electronic component assembling method and an electronic apparatus which can efficiently manufacture electronic components with excellent dimensional accuracy. And

【０００５】[0005]

【課題を解決するための手段】上述の技術的課題を解決
するために、本発明に係る電子部品の組立方法は、基板
が有する複数の領域に各々チップを装着し、封止樹脂に
よって封止した後に基板を分離して、各々領域とチップ
と封止樹脂とからなる電子部品を組み立てる電子部品の
組立方法であって、各領域に各々チップを載置する工程
と、各領域が有する基板側電極と各チップが有するチッ
プ側電極とを電気的に接続する工程と、封止樹脂によっ
て複数の領域にわたり基板を封止する工程と、電子部品
の外部に対して電気信号を授受する目的で各領域におい
て設けられた外部電極に所定の検査用電気信号を供給し
て各々電子部品の動作を検査する工程と、複数の領域に
わたって封止された基板を分離して電子部品を各々形成
する工程とを備えたことを特徴としている。In order to solve the above-mentioned technical problems, a method of assembling an electronic component according to the present invention comprises mounting a chip on each of a plurality of regions of a substrate and sealing the chip with a sealing resin. A method of assembling an electronic component, comprising separating a substrate after the above and assembling an electronic component including each region, a chip, and a sealing resin, comprising: mounting a chip in each region; A step of electrically connecting the electrodes and the chip-side electrodes of each chip, a step of sealing the substrate over a plurality of regions with a sealing resin, and a step of transmitting and receiving electric signals to the outside of the electronic component. A step of supplying a predetermined test electrical signal to an external electrode provided in the region to inspect the operation of each electronic component, and a step of forming each electronic component by separating a substrate sealed over a plurality of regions. Equipped It is characterized in that.

【０００６】また、本発明に係る電子部品の組立方法
は、上述の組立方法において、検査する工程では、複数
の領域にわたって封止された基板を所定の温度雰囲気中
に配設することを特徴としている。Further, the method for assembling an electronic component according to the present invention is characterized in that in the above-described assembling method, in the inspecting step, a substrate sealed over a plurality of regions is arranged in a predetermined temperature atmosphere. I have.

【０００７】また、本発明に係る電子部品の組立方法
は、上述の組立方法において、複数の領域にわたって封
止された基板における外部電極上に突起状電極を形成す
る工程を更に備えたことを特徴としている。Further, the method of assembling an electronic component according to the present invention is characterized in that, in the above-described assembling method, a step of forming a protruding electrode on an external electrode on a substrate sealed over a plurality of regions is further provided. And

【０００８】また、本発明に係る電子部品の組立方法
は、上述の組立方法において、封止する工程では、互い
に相対向する少なくとも２つの金型からなる金型セット
の型合わせ面に基板を載置し、金型セットを型締めし、
金型セットと基板とからなるキャビティに溶融樹脂を注
入して硬化させることにより封止樹脂を形成することを
特徴としている。In the method for assembling an electronic component according to the present invention, in the above-described assembling method, in the sealing step, the substrate is mounted on a mold-matching surface of a mold set including at least two molds facing each other. Place, clamp the mold set,
It is characterized in that a sealing resin is formed by injecting and curing a molten resin into a cavity formed by a mold set and a substrate.

【０００９】また、本発明に係る電子部品の組立方法
は、上述の組立方法において、キャビティを減圧する工
程を更に備え、減圧されたキャビティに対して溶融樹脂
を注入することを特徴としている。Further, the method of assembling an electronic component according to the present invention is characterized in that, in the above-described assembling method, the method further comprises a step of depressurizing the cavity, and injecting the molten resin into the depressurized cavity.

【００１０】本発明に係る電子部品の組立装置は、基板
が有する複数の領域に各々チップを装着し、封止樹脂に
よって封止した後に基板を分離して、各々領域とチップ
と封止樹脂とからなる電子部品を組み立てる電子部品の
組立装置であって、各領域に各々チップを載置するボン
ディング手段と、各領域が有する基板側電極と各チップ
が有するチップ側電極とを電気的に接続する接続手段
と、複数の領域にわたって封止樹脂を形成する封止手段
と、電子部品の外部に対して電気信号を授受する目的で
各領域において設けられた外部電極に対して、電子部品
の動作を各々検査する目的で検査用電気信号を授受する
検査手段と、複数の領域にわたって封止樹脂が形成され
た基板を電子部品に分離する分離手段とを備えたことを
特徴としている。In an electronic component assembling apparatus according to the present invention, a chip is mounted on each of a plurality of regions of a substrate, and the substrate is separated after sealing with a sealing resin. Device for assembling an electronic component, comprising: bonding means for mounting a chip in each region, and electrically connecting a substrate-side electrode in each region and a chip-side electrode in each chip. Connecting means, sealing means for forming a sealing resin over a plurality of regions, and operation of the electronic component with respect to external electrodes provided in each region for the purpose of transmitting and receiving electric signals to the outside of the electronic component. It is characterized by comprising inspection means for transmitting and receiving an inspection electric signal for the purpose of each inspection, and separation means for separating a substrate on which a sealing resin is formed over a plurality of regions into electronic components.

【００１１】また、本発明に係る電子部品の組立装置
は、上述の組立装置において、検査手段は、複数の領域
にわたって封止樹脂が形成された基板を所定の温度雰囲
気中に配設した状態で外部電極に所定の電気信号を供給
することを特徴としている。[0011] Further, in the electronic component assembling apparatus according to the present invention, in the above assembling apparatus, the inspection means may be a state in which the substrate on which the sealing resin is formed over a plurality of regions is disposed in a predetermined temperature atmosphere. It is characterized in that a predetermined electric signal is supplied to the external electrode.

【００１２】また、本発明に係る電子部品の組立装置
は、上述の組立装置において、複数の領域にわたって封
止樹脂が形成された基板における外部電極上に突起状電
極を形成する電極形成手段を更に備えたことを特徴とし
ている。[0012] Further, in the electronic component assembling apparatus according to the present invention, the above-mentioned assembling apparatus further includes an electrode forming means for forming a protruding electrode on the external electrode on the substrate on which the sealing resin is formed over a plurality of regions. It is characterized by having.

【００１３】また、本発明に係る電子部品の組立装置
は、上述の組立装置において、封止手段は、互いに相対
向する少なくとも２つの金型からなる金型セットと、金
型セットと該金型セットの型合わせ面に載置された基板
とによって構成されるキャビティに溶融樹脂を注入する
注入手段とを備えたことを特徴としている。Further, in the electronic device assembling apparatus according to the present invention, in the above-described assembling apparatus, the sealing means includes a mold set including at least two molds facing each other, a mold set, and the mold set. Injection means for injecting the molten resin into a cavity formed by the substrate placed on the mating surface of the set.

【００１４】また、本発明に係る電子部品の組立装置
は、上述の組立装置において、封止手段は、キャビティ
を減圧する減圧手段を更に備えたことを特徴としてい
る。Further, the assembling apparatus for an electronic component according to the present invention is characterized in that, in the above-mentioned assembling apparatus, the sealing means is further provided with a decompression means for decompressing the cavity.

【００１５】[0015]

【作用】本発明によれば、基板が有する複数の領域の各
々にチップを装着し、基板側電極とチップ側電極とを接
続し、封止樹脂を使用して複数の領域にわたって基板を
封止し、電子部品の動作を通電検査した後に、基板を分
離して電子部品を形成する。これにより、基板の状態で
一括して封止するので、封止の工数を削減することがで
きる。また、基板の状態で個々の電子部品を通電検査す
ることにより、チップごとの検査装置への搬送や着脱が
不要になるので、検査の工数を削減することができる。
したがって、工数を削減して高い効率で電子部品を組み
立てることができる。また、所定の温度雰囲気中で、外
部電極に電気信号を供給することによって、電子部品の
動作を検査する。したがって、基板状態で、効率よく電
子部品のバーンインを行うことができる。また、基板状
態で、電子部品が有する外部電極に一括して突起状電極
を形成するので、電子部品に突起状電極を形成する工数
を削減することができる。また、金型セットの型合わせ
面上に載置された基板と、型締めされた金型セットとに
よって構成されるキャビティに、溶融樹脂を注入して硬
化させ、基板の複数の領域を一括して封止する。これに
より、基板の各領域に各々チップを封止する際に個々の
チップを封止する必要がないので、封止する際の工数を
削減することができる。さらに、閉空間であるキャビテ
ィに注入された溶融樹脂が硬化するので、封止樹脂を寸
法精度よく形成することができる。また、キャビティを
減圧して、減圧されたキャビティに溶融樹脂を注入する
ので、基板の複数の領域を一括して封止する際に、ボイ
ドの発生を抑制しながらキャビティの全領域に安定して
溶融樹脂を注入することができる。According to the present invention, a chip is mounted on each of a plurality of regions of a substrate, a substrate-side electrode and a chip-side electrode are connected, and the substrate is sealed over the plurality of regions using a sealing resin. After the operation of the electronic component is inspected, the board is separated to form an electronic component. Thereby, since the sealing is performed collectively in the state of the substrate, the number of sealing steps can be reduced. In addition, by conducting an electrical test on each electronic component in the state of the substrate, it is not necessary to transport or attach / detach the chip to / from the inspection apparatus, so that the number of inspection steps can be reduced.
Therefore, it is possible to assemble the electronic component with high efficiency while reducing the number of steps. Further, the operation of the electronic component is inspected by supplying an electric signal to the external electrode in a predetermined temperature atmosphere. Therefore, the burn-in of the electronic component can be efficiently performed in the substrate state. Further, since the protruding electrodes are collectively formed on the external electrodes of the electronic component in the substrate state, the number of steps for forming the protruding electrodes on the electronic component can be reduced. In addition, a molten resin is injected into a cavity formed by the substrate placed on the mold mating surface of the mold set and the clamped mold set and cured, so that a plurality of regions of the substrate are collectively formed. And seal. This eliminates the need to seal individual chips when sealing each chip in each region of the substrate, so that the number of steps for sealing can be reduced. Furthermore, since the molten resin injected into the cavity, which is a closed space, is cured, the sealing resin can be formed with high dimensional accuracy. In addition, since the cavity is depressurized and the molten resin is injected into the depressurized cavity, when sealing a plurality of regions of the substrate at once, the generation of voids is suppressed and the entire region of the cavity is stably suppressed. Molten resin can be injected.

【００１６】[0016]

【発明の実施の形態】本発明に係る電子部品の組立方法
及び組立装置について、図１〜図４を参照して説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method and an apparatus for assembling an electronic component according to the present invention will be described with reference to FIGS.

【００１７】以下、電子部品を組み立てる際の各工程に
おける半製品の状態について、図１と図２とを参照して
説明する。図１（１）〜（３）は、本発明に係る電子部
品の組立方法において、基板にチップを装着してから樹
脂封止した後に、バーンインして判定された不良品を覆
う封止樹脂にフェイルマークを付するまでの各工程にお
ける半製品をそれぞれ示す斜視図である。Hereinafter, the state of a semi-finished product in each step of assembling an electronic component will be described with reference to FIGS. FIGS. 1 (1) to 1 (3) show a method of assembling an electronic component according to the present invention. It is a perspective view which shows each semi-finished product in each process until it attaches a fail mark.

【００１８】図１（１）に示すように、まず、基板１に
チップ２をボンディングする。この場合には、ボンディ
ング用のツール３によって、チップ２を加熱しながら保
持して、チップ側電極（図示なし）上に設けられた例え
ば半田からなるバンプ４と基板側電極５とを位置合わせ
する。その後に、ステージ（図示なし）上に基準穴６に
よって位置合わせされ例えば吸着によって固定されてい
る基板１に、ツール３によって、チップ２を圧接すると
ともにバンプ４を溶融後硬化させて、ボンディングを行
う。As shown in FIG. 1A, first, a chip 2 is bonded to a substrate 1. In this case, the bonding tool 3 holds the chip 2 while heating it, and aligns the bump 4 made of, for example, solder provided on the chip-side electrode (not shown) with the board-side electrode 5. . Thereafter, the chip 2 is pressed against the substrate 1 which is positioned on the stage (not shown) by the reference hole 6 and fixed by suction, for example, by suction, and the bump 4 is melted and hardened after bonding, thereby performing bonding. .

【００１９】次に、図１（２）に示すように、１個のチ
ップ２に対応する単位領域７が複数個集合した領域に、
封止樹脂８を形成する。本図においては、９個の単位領
域７を覆って１区画の封止樹脂８が形成されている。こ
こでは、後述するように、型締めされた金型セットと基
板１とによって形成されたキャビティに、溶融樹脂を注
入して硬化させることによって、封止樹脂８を形成す
る。仮想線９は、各単位領域７の外縁からなり、後工程
において切断される位置を示している。Next, as shown in FIG. 1 (2), an area where a plurality of unit areas 7 corresponding to one chip 2 are gathered,
The sealing resin 8 is formed. In the figure, one section of the sealing resin 8 is formed so as to cover the nine unit regions 7. Here, as described later, the sealing resin 8 is formed by injecting and curing a molten resin into a cavity formed by the clamped mold set and the substrate 1. The imaginary line 9 is formed by the outer edge of each unit area 7 and indicates a position to be cut in a subsequent process.

【００２０】次に、図１（３）に示すように、テストボ
ード１０を基板１の下方に対向させて配置し、テストボ
ード１０に基板１を圧接する。この場合には、各単位領
域７において基板１の下面に設けられ、電子部品と外部
との間で電気信号を授受するための外部電極（図示な
し）と、テストボード１０が有するテスト用電極１１と
を位置合わせして、テストボード１０に対して基板１を
圧接する。その後に、テストボード１０の外部に設けら
れたテスト装置（図示なし）から、必要な電気信号を所
定のテスト用電極１１に供給して、順次チップ２を動作
させる。更に、動作しているチップ２から出力される電
気信号を、所定のテスト用電極１１を介してテスト装置
に供給して、テスト装置がチップ２の動作が正常かどう
かを判定して、チップ２の動作を検査する。検査の結
果、動作が正常でなかった場合には、そのチップ２を含
む電子部品が不良であることを示すフェイルマーク１２
を、そのチップ２を覆う封止樹脂８に付する。Next, as shown in FIG. 1 (3), the test board 10 is arranged facing the lower side of the substrate 1, and the substrate 1 is pressed against the test board 10. In this case, an external electrode (not shown) provided on the lower surface of the substrate 1 in each unit area 7 for transmitting and receiving an electric signal between the electronic component and the outside, and a test electrode 11 included in the test board 10 And the substrate 1 is pressed against the test board 10. Thereafter, a necessary electric signal is supplied to a predetermined test electrode 11 from a test device (not shown) provided outside the test board 10, and the chip 2 is sequentially operated. Further, an electric signal output from the operating chip 2 is supplied to a test device via a predetermined test electrode 11, and the test device determines whether or not the operation of the chip 2 is normal. Check the operation of. As a result of the inspection, when the operation is not normal, the fail mark 12 indicating that the electronic component including the chip 2 is defective.
Is applied to the sealing resin 8 covering the chip 2.

【００２１】図２（１），（２）は、本発明に係る電子
部品の組立方法において、製品マークをマーキングして
から個々の電子部品に切断するまでの各工程における半
製品をそれぞれ示す斜視図、（３）は、電子部品の完成
品を示す斜視図である。図２（１）に示すように、封止
樹脂８にフェイルマーク１２をマーキングした後に、封
止樹脂８に、各チップに対応して製品マーク１３をマー
キングする。このマーキングについては、例えばレー
ザ、インクジェット等を使用することができるが、本発
明においては、多数の電子部品に対して一括して同時に
マーキングできる、オフセット印刷、ダイレクト印刷、
スクリーン印刷等を使用することが好ましい。FIGS. 2 (1) and 2 (2) are perspective views respectively showing semi-finished products in each process from marking of a product mark to cutting into individual electronic components in the method of assembling electronic components according to the present invention. FIG. 3C is a perspective view illustrating a completed electronic component. As shown in FIG. 2A, after the fail mark 12 is marked on the sealing resin 8, a product mark 13 is marked on the sealing resin 8 corresponding to each chip. For this marking, for example, a laser, an ink jet or the like can be used, but in the present invention, offset printing, direct printing,
It is preferable to use screen printing or the like.

【００２２】次に、図２（２）に示すように、例えば転
写法によって、基板１が有する外部電極（図示なし）に
半田等からなるバンプ１４を形成し、その後に、封止樹
脂８によってチップが基板１に樹脂封止された成形体
を、切断位置を示す仮想線９において切断する。このこ
とにより、図には示されていないチップと、バンプ１４
を有する個別基板１５と、個別樹脂１６とからなる個々
の電子部品、すなわち図２（３）に示されているパッケ
ージ１７を完成させることができる。Next, as shown in FIG. 2B, a bump 14 made of solder or the like is formed on an external electrode (not shown) of the substrate 1 by, for example, a transfer method. The molded body in which the chip is resin-sealed on the substrate 1 is cut along a virtual line 9 indicating a cutting position. This allows the chip (not shown) and the bump 14
2 can be completed, that is, the package 17 shown in FIG. 2 (3).

【００２３】以下、電子部品を組み立てる際の各工程に
ついて、図３と図４とを参照して説明する。図３（１）
〜（３）は、本発明に係る電子部品の組立方法におい
て、基板にチップを装着してから樹脂封止するまでの各
工程を、図１（１）〜（３）のＡ−Ａ線に沿ってそれぞ
れ示す断面図である。Hereinafter, each step of assembling the electronic component will be described with reference to FIGS. Fig. 3 (1)
FIGS. 1 to 3 show, in the method of assembling an electronic component according to the present invention, the steps from mounting a chip on a substrate to resin sealing, along the line AA in FIGS. It is sectional drawing shown along each.

【００２４】まず、図３（１）に示すように、ツール３
によってチップ２を保持し、チップ２が有するチップ側
電極１８上に設けられたバンプ４と、基板１が有する基
板側電極５とを位置合わせする。そして、ツール３によ
ってチップ２を加熱しながら基板１に圧接する。これに
より、バンプ４を溶融後硬化させて、チップ側電極１８
と基板側電極５とを電気的に接続する。ここまでの工程
を繰り返して、基板１のすべての単位領域７において、
外部電極１９が形成されている面の反対面に、それぞれ
チップ２を装着する。First, as shown in FIG.
The bumps 4 provided on the chip-side electrodes 18 of the chip 2 are aligned with the substrate-side electrodes 5 of the substrate 1. Then, the chip 2 is pressed against the substrate 1 while being heated by the tool 3. As a result, the bump 4 is melted and cured, and the chip-side electrode 18 is cured.
And the substrate-side electrode 5 are electrically connected. By repeating the steps up to this point, in all the unit regions 7 of the substrate 1,
The chip 2 is mounted on the surface opposite to the surface on which the external electrodes 19 are formed.

【００２５】次に、図３（２）に示すように、上型２０
に対向して設けられた下型２１上に基板１を載置した後
に、上型２０と下型２１とを型合わせする。ここで、上
型２０と下型２１とは併せて金型セットを構成し、基板
１の上面が金型セットの型合わせ面P.L.と同一面になる
ように、基板１を載置する。型締めされた金型セットと
基板１とは、それぞれ樹脂通路であるランナ部２２及び
ゲート部２３と、樹脂が注入される空間であるキャビテ
ィ２４とを構成する。上型２０に設けられている排気管
２５は、図示されていない排気ポンプ等からなる減圧機
構に接続されており、破線の矢印で示されているように
キャビティ２４内を排気して減圧状態にする。そして、
プランジャ（図示なし）によって加圧された溶融樹脂２
６が、矢印で示されているようにキャビティ２４内に注
入された後に硬化して、封止樹脂を形成する。Next, as shown in FIG.
After the substrate 1 is placed on the lower mold 21 provided opposite to the above, the upper mold 20 and the lower mold 21 are matched. Here, the upper mold 20 and the lower mold 21 together form a mold set, and the substrate 1 is placed so that the upper surface of the substrate 1 is flush with the mold mating surface PL of the mold set. The clamped mold set and the substrate 1 constitute a runner portion 22 and a gate portion 23, respectively, which are resin passages, and a cavity 24, which is a space into which resin is injected. An exhaust pipe 25 provided in the upper mold 20 is connected to a decompression mechanism including an exhaust pump (not shown), and exhausts the inside of the cavity 24 as shown by a dashed arrow to reduce the pressure. I do. And
Molten resin 2 pressurized by plunger (not shown)
After being injected into the cavity 24 as shown by the arrow, it hardens to form a sealing resin.

【００２６】次に、図３（３）に示すように、外部電極
１９と、テストボード１０上に設けられたテスト用電極
１１とを接触させる。その後に、すでに述べたように、
テスト装置（図示なし）を使用して順次チップ２を動作
させ、動作が正常でなかった場合には、そのチップ２を
含む電子部品が不良であることを示すフェイルマーク１
２を、そのチップ２を覆う封止樹脂８に付する。これに
より、電子部品を検査して、不良品を特定することがで
きる。また、この工程では、各チップ２が樹脂封止され
た基板１を所定の温度雰囲気中に置いた状態で、テスト
装置から所定のテスト用電極１１に必要な電気信号を供
給して各チップ２を連続動作させて、バーンインを行う
ことができる。Next, as shown in FIG. 3C, the external electrode 19 is brought into contact with the test electrode 11 provided on the test board 10. Then, as already mentioned,
A chip 2 is sequentially operated using a test device (not shown). If the operation is not normal, a fail mark 1 indicating that an electronic component including the chip 2 is defective is provided.
2 is applied to a sealing resin 8 covering the chip 2. Thus, the electronic component can be inspected and a defective product can be specified. In this step, while the substrate 1 in which each chip 2 is resin-sealed is placed in a predetermined temperature atmosphere, a necessary electric signal is supplied from a test apparatus to a predetermined test electrode 11 and each chip 2 Can be operated continuously to perform burn-in.

【００２７】図４（１），（２）は、本発明に係る電子
部品の組立方法において、樹脂封止後バーンインしてか
ら個々の電子部品に切断するまでの各工程を、図２
（１），（２）のＡ−Ａ線に沿ってそれぞれ示す断面図
である。図４（１）に示すように、各チップ２に対応す
る封止樹脂８の表面にそれぞれ製品マーク１３をマーキ
ングする。そして、例えば転写装置を使用して、外部電
極１９に半田等からなるバンプ１４を形成した後に、ブ
レード２７を用いて、封止樹脂８に一体化した基板１を
仮想線９において切断する。以上の工程により、図４
（２）に示されているように、チップ２と、バンプ１４
を有する個別基板１５と、個別樹脂１６とからなる個々
の電子部品、すなわちパッケージ１７を完成させる。FIGS. 4 (1) and 4 (2) show steps in the method of assembling electronic components according to the present invention, from burn-in after resin sealing to cutting into individual electronic components.
It is sectional drawing shown along the AA of (1) and (2), respectively. As shown in FIG. 4A, a product mark 13 is marked on the surface of the sealing resin 8 corresponding to each chip 2. Then, after the bumps 14 made of solder or the like are formed on the external electrodes 19 using, for example, a transfer device, the substrate 1 integrated with the sealing resin 8 is cut along the virtual lines 9 using the blade 27. By the above steps, FIG.
As shown in (2), the chip 2 and the bump 14
, An individual electronic component, that is, a package 17, composed of the individual substrate 15 having the above-described structure and the individual resin 16 is completed.

【００２８】更に、完成したパッケージ１７は、全数が
一括してトレイに移載され、プリント基板等に実装する
工程で使用される。この工程で使用されるマウンタは、
画像処理によってフェイルマーク１２を認識して、不良
チップを有する電子部品をプリント基板等に実装しな
い。したがって、良品のパッケージ１７のみを選別して
トレイに移載する工程が不要になる。Further, all of the completed packages 17 are collectively transferred to a tray and used in a process of mounting on a printed circuit board or the like. The mounter used in this process is
An electronic component having a defective chip is not mounted on a printed circuit board or the like by recognizing the fail mark 12 by image processing. Therefore, the step of selecting only non-defective packages 17 and transferring them to the tray becomes unnecessary.

【００２９】以上説明したように、本発明によれば、複
数の単位領域７を有する基板１を一括して封止するとと
もに、基板１の状態で個々の電子部品を通電検査する。
これによって、チップ２ごとの樹脂封止が不要になると
ともに、各電子部品を検査装置に搬送し、かつ着脱する
工数が不要になるので、工数を削減して高い効率で電子
部品を組み立てることができる。また、所定の温度雰囲
気中に基板１を置いた状態で、個々の電子部品を一括し
てバーンインすることができる。これによって、各電子
部品をバーンイン装置に搬送し、かつ着脱する工数が不
要になるので、工数を削減して高い効率で電子部品を組
み立てることができる。また、基板１の状態で、基板１
が有する外部電極１９に一括してバンプ１４を形成する
ので、パッケージ１７、つまり電子部品にバンプ１４を
形成する工数を削減することができる。また、金型セッ
トの型合わせ面P.L.に載置された基板１と、型締めされ
た金型セットとによって構成されるキャビティ２４に、
溶融樹脂２６を注入して硬化させ、基板１が有する複数
の単位領域７を一括して封止する。これにより、個々の
チップ２ごとに封止する必要がないので、封止する際の
工数を削減することができる。加えて、閉空間であるキ
ャビティ２４に注入された溶融樹脂が硬化することによ
り、高い寸法精度で樹脂封止することができる。また、
キャビティ２４を減圧して、減圧されたキャビティ２４
に溶融樹脂２６を注入するので、基板１が有する複数の
単位領域７を一括して封止する際に、ボイドの発生を抑
制しながらキャビティ２４の全領域に安定して溶融樹脂
２６を注入することができる。As described above, according to the present invention, the substrate 1 having the plurality of unit regions 7 is sealed at a time, and the individual electronic components are inspected for current conduction in the state of the substrate 1.
This eliminates the need for resin sealing for each chip 2 and eliminates the need for man-hours for transporting and attaching and detaching each electronic component to an inspection device, thereby reducing man-hours and assembling the electronic component with high efficiency. it can. In addition, individual electronic components can be burned in collectively with the substrate 1 placed in a predetermined temperature atmosphere. This eliminates the need for man-hours for transporting each electronic component to the burn-in device and for attaching and detaching the electronic component, thereby reducing the number of man-hours and assembling the electronic component with high efficiency. In the state of the substrate 1, the substrate 1
Since the bumps 14 are collectively formed on the external electrodes 19 included in the package 17, the number of steps for forming the bumps 14 on the package 17, that is, the electronic component can be reduced. Further, a cavity 24 formed by the substrate 1 placed on the mold mating surface PL of the mold set and the clamped mold set is
The molten resin 26 is injected and cured, and the plurality of unit regions 7 of the substrate 1 are collectively sealed. This eliminates the need to seal each individual chip 2, so that the number of steps for sealing can be reduced. In addition, since the molten resin injected into the cavity 24, which is a closed space, is cured, the resin can be sealed with high dimensional accuracy. Also,
The pressure in the cavity 24 is reduced, and the pressure in the cavity 24 is reduced.
When the plurality of unit regions 7 of the substrate 1 are collectively sealed, the molten resin 26 is stably injected into the entire region of the cavity 24 while suppressing the generation of voids. be able to.

【００３０】なお、本実施形態の説明においては、チッ
プ側電極１８と基板側電極５とを接続するためにチップ
２側に設けられたバンプ４を使用したが、これに代え
て、基板側電極５上にバンプを設けてもよい。In the description of the present embodiment, the bumps 4 provided on the chip 2 side for connecting the chip-side electrode 18 and the substrate-side electrode 5 are used. 5 may be provided with bumps.

【００３１】また、チップ２と基板１とが有する電極同
士をバンプ４によって接続したが、これに代えて、ワイ
ヤボンディングを使用して接続することもできる。Although the electrodes of the chip 2 and the substrate 1 are connected to each other by the bumps 4, the electrodes may be connected by wire bonding instead.

【００３２】また、ブレード２７によって封止樹脂８に
一体化した基板１を切断したが、これに代えて、レーザ
を使用して切断してもよい。Although the substrate 1 integrated with the sealing resin 8 is cut by the blade 27, the cutting may be performed by using a laser instead.

【００３３】また、電子部品を検査した後にバンプ１４
を形成したが、これに代えて、バンプ１４を形成した後
に電子部品を検査してもよい。更に、バンプ１４が設け
られていない構成を有する電子部品に対しても、本発明
を適用することができる。After inspecting the electronic component, the bump 14
However, instead of this, the electronic component may be inspected after the bumps 14 are formed. Further, the present invention can be applied to an electronic component having a configuration in which the bumps 14 are not provided.

【００３４】[0034]

【発明の効果】本発明によれば、チップごとの樹脂封止
が不要になり、各電子部品を検査装置及びバーンイン装
置に搬送し、かつ着脱する工数が不要になる。また、閉
空間であるキャビティに注入された溶融樹脂が硬化する
ことにより、高い寸法精度で樹脂封止することができ
る。加えて、溶融樹脂が注入されるキャビティを減圧す
ることにより、ボイドの発生を抑制しながら、キャビテ
ィの全領域に安定して溶融樹脂を注入することができ
る。これにより、本発明は、工数を削減して高い効率で
電子部品を組み立てるとともに、高い寸法精度及び品質
を有する封止樹脂を備えた電子部品を組み立てる電子部
品の組立方法及び組立装置を提供することができるとい
う、優れた実用的な効果を奏するものである。According to the present invention, resin sealing for each chip is not required, and man-hours for transporting each electronic component to the inspection device and the burn-in device and for attaching and detaching each component are not required. In addition, the molten resin injected into the cavity, which is a closed space, is cured, so that the resin can be sealed with high dimensional accuracy. In addition, by reducing the pressure of the cavity into which the molten resin is injected, it is possible to stably inject the molten resin into the entire region of the cavity while suppressing generation of voids. Accordingly, the present invention provides an assembling method and an assembling apparatus for an electronic component that assembles an electronic component with a sealing resin having high dimensional accuracy and quality while assembling the electronic component with high efficiency while reducing man-hours. It has an excellent practical effect.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（１）〜（３）は、本発明に係る電子部品の組
立方法において、基板にチップを装着してから樹脂封止
した後に、バーンインして判定された不良品を覆う封止
樹脂にフェイルマークを付するまでの各工程における半
製品をそれぞれ示す斜視図である。FIGS. 1 (1) to 1 (3) show a method of assembling an electronic component according to the present invention. It is a perspective view which shows each semi-finished product in each process until a fail mark is attached to resin.

【図２】（１），（２）は、本発明に係る電子部品の組
立方法において、製品マークをマーキングしてから個々
の電子部品に切断するまでの各工程における半製品をそ
れぞれ示す斜視図、（３）は、電子部品の完成品を示す
斜視図である。FIGS. 2A and 2B are perspective views respectively showing semi-finished products in each process from marking a product mark to cutting into individual electronic components in an electronic component assembling method according to the present invention. (3) is a perspective view showing a completed electronic component.

【図３】（１）〜（３）は、本発明に係る電子部品の組
立方法において、基板にチップを装着してから樹脂封止
するまでの各工程を、図１（１）〜（３）のＡ−Ａ線に
沿ってそれぞれ示す断面図である。FIGS. 3 (1) to 3 (3) show steps from mounting a chip on a substrate to resin sealing in an electronic component assembling method according to the present invention. 2) is a cross-sectional view taken along line AA of FIG.

【図４】（１），（２）は、本発明に係る電子部品の組
立方法において、樹脂封止後バーンインしてから個々の
電子部品に切断するまでの各工程を、図２（１），
（２）のＡ−Ａ線に沿ってそれぞれ示す断面図である。FIGS. 4 (1) and (2) show steps in the method of assembling an electronic component according to the present invention from burn-in after resin sealing to cutting into individual electronic components. ,
It is sectional drawing shown along the AA of (2), respectively.

【符号の説明】[Explanation of symbols]

１ 基板 ２ チップ ３ ツール（ボンディング手段，接続手段） ４ バンプ ５ 基板側電極 ６ 基準穴 ７ 単位領域（領域） ８ 封止樹脂 ９ 仮想線 １０ テストボード（検査手段） １１ テスト用電極 １２ フェイルマーク １３ 製品マーク １４ バンプ（突起状電極） １５ 個別基板 １６ 個別樹脂 １７ パッケージ １８ チップ側電極 １９ 外部電極 ２０ 上型 ２１ 下型 ２２ ランナ部 ２３ ゲート部 ２４ キャビティ ２５ 排気管 ２６ 溶融樹脂 ２７ ブレード（分離手段） Reference Signs List 1 substrate 2 chip 3 tool (bonding means, connection means) 4 bump 5 substrate-side electrode 6 reference hole 7 unit area (area) 8 sealing resin 9 virtual line 10 test board (inspection means) 11 test electrode 12 fail mark 13 Product mark 14 Bump (protruding electrode) 15 Individual substrate 16 Individual resin 17 Package 18 Chip-side electrode 19 External electrode 20 Upper die 21 Lower die 22 Runner part 23 Gate part 24 Cavity 25 Exhaust pipe 26 Molten resin 27 Blade (separating means)

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 基板が有する複数の領域に各々チップを
装着し、封止樹脂によって封止した後に前記基板を分離
して、各々前記領域と前記チップと前記封止樹脂とから
なる電子部品を組み立てる電子部品の組立方法であっ
て、 前記各領域に各々前記チップを載置する工程と、 前記各領域が有する基板側電極と前記各チップが有する
チップ側電極とを電気的に接続する工程と、 前記封止樹脂によって前記複数の領域にわたり前記基板
を封止する工程と、 前記電子部品の外部に対して電気信号を授受する目的で
前記各領域において設けられた外部電極に、所定の検査
用電気信号を供給して各々前記電子部品の動作を検査す
る工程と、 前記複数の領域にわたって封止された前記基板を分離し
て前記電子部品を各々形成する工程とを備えたことを特
徴とする電子部品の組立方法。1. A chip is mounted on each of a plurality of regions of a substrate, and after sealing with a sealing resin, the substrate is separated and an electronic component including each of the region, the chip, and the sealing resin is separated. A method of assembling an electronic component to be assembled, wherein: a step of mounting the chip in each of the regions; and a step of electrically connecting a substrate-side electrode of each of the regions and a chip-side electrode of each of the chips. A step of sealing the substrate over the plurality of regions with the sealing resin, and a predetermined test for external electrodes provided in the respective regions for the purpose of transmitting and receiving electric signals to the outside of the electronic component. A step of supplying an electric signal to inspect the operation of each of the electronic components; and a step of separating the substrate sealed over the plurality of regions to form each of the electronic components. Assembly method of the electronic component to be. 【請求項２】 請求項１記載の電子部品の組立方法にお
いて、 前記検査する工程では、前記複数の領域にわたって封止
された前記基板を所定の温度雰囲気中に配設することを
特徴とする電子部品の組立方法。2. The method for assembling an electronic component according to claim 1, wherein in the inspecting step, the substrate sealed over the plurality of regions is disposed in a predetermined temperature atmosphere. How to assemble parts. 【請求項３】 請求項１又は２記載の電子部品の組立方
法において、 前記複数の領域にわたって封止された前記基板における
前記外部電極上に突起状電極を形成する工程を更に備え
たことを特徴とする電子部品の組立方法。3. The method for assembling an electronic component according to claim 1, further comprising a step of forming a protruding electrode on the external electrode on the substrate sealed over the plurality of regions. Method of assembling electronic components. 【請求項４】 請求項１〜３のいずれか１つに記載され
た電子部品の組立方法において、前記封止する工程で
は、 互いに相対向する少なくとも２つの金型からなる金型セ
ットの型合わせ面に前記基板を載置し、 前記金型セットを型締めし、 前記金型セットと前記基板とからなるキャビティに溶融
樹脂を注入して硬化させることにより前記封止樹脂を形
成することを特徴とする電子部品の組立方法。4. The method for assembling an electronic component according to claim 1, wherein, in the sealing step, a mold set including at least two molds facing each other is set. The sealing resin is formed by placing the substrate on a surface, clamping the mold set, injecting and curing a molten resin into a cavity formed by the mold set and the substrate. Method of assembling electronic components. 【請求項５】 請求項４記載の電子部品の組立方法にお
いて、 前記キャビティを減圧する工程を更に備え、 前記減圧されたキャビティに対して前記溶融樹脂を注入
することを特徴とする電子部品の組立方法。5. The electronic component assembling method according to claim 4, further comprising a step of depressurizing the cavity, wherein the molten resin is injected into the depressurized cavity. Method. 【請求項６】 基板が有する複数の領域に各々チップを
装着し、封止樹脂によって封止した後に前記基板を分離
して、各々前記領域と前記チップと前記封止樹脂とから
なる電子部品を組み立てる電子部品の組立装置であっ
て、 前記各領域に各々前記チップを載置するボンディング手
段と、 前記各領域が有する基板側電極と前記各チップが有する
チップ側電極とを電気的に接続する接続手段と、 前記複数の領域にわたって前記封止樹脂を形成する封止
手段と、 前記電子部品の外部に対して電気信号を授受する目的で
前記各領域において設けられた外部電極に対して、前記
電子部品の動作を各々検査する目的で検査用電気信号を
授受する検査手段と、 前記複数の領域にわたって前記封止樹脂が形成された基
板を前記電子部品に分離する分離手段とを備えたことを
特徴とする電子部品の組立装置。6. A chip is mounted on each of a plurality of regions of a substrate, and after sealing with a sealing resin, the substrate is separated, and an electronic component including each of the region, the chip, and the sealing resin is separated. An assembling apparatus for assembling electronic components, comprising: bonding means for placing the chips in the respective regions; and connection for electrically connecting a substrate-side electrode included in the respective regions and a chip-side electrode included in the respective chips. Means, a sealing means for forming the sealing resin over the plurality of areas, and an external electrode provided in each area for the purpose of transmitting and receiving an electric signal to the outside of the electronic component. Inspection means for transmitting and receiving an inspection electric signal for the purpose of inspecting the operation of each component; and separation means for separating the substrate on which the sealing resin is formed over the plurality of regions into the electronic components. Assembly device electronic component comprising the. 【請求項７】 請求項６記載の電子部品の組立装置にお
いて、 前記検査手段は、前記複数の領域にわたって前記封止樹
脂が形成された基板を所定の温度雰囲気中に配設した状
態で前記外部電極に前記所定の電気信号を供給すること
を特徴とする電子部品の組立装置。7. The electronic component assembling apparatus according to claim 6, wherein the inspection unit is configured to dispose the substrate on which the sealing resin is formed over the plurality of regions in an atmosphere at a predetermined temperature. An apparatus for assembling an electronic component, wherein the predetermined electric signal is supplied to an electrode. 【請求項８】 請求項６又は７記載の電子部品の組立装
置において、 前記複数の領域にわたって前記封止樹脂が形成された基
板における前記外部電極上に突起状電極を形成する電極
形成手段を更に備えたことを特徴とする電子部品の組立
装置。8. The electronic component assembling apparatus according to claim 6, further comprising an electrode forming means for forming a protruding electrode on the external electrode on the substrate on which the sealing resin is formed over the plurality of regions. An electronic component assembling apparatus comprising: 【請求項９】 請求項６〜８のいずれか１つに記載され
た電子部品の組立装置において、前記封止手段は、 互いに相対向する少なくとも２つの金型からなる金型セ
ットと、 前記金型セットと該金型セットの型合わせ面に載置され
た前記基板とによって構成されるキャビティに溶融樹脂
を注入する注入手段とを備えたことを特徴とする電子部
品の組立装置。9. The electronic component assembling apparatus according to claim 6, wherein said sealing means includes: a mold set including at least two molds facing each other; An assembling apparatus for an electronic component, comprising: an injecting unit that injects a molten resin into a cavity formed by a mold set and the substrate placed on a mold mating surface of the mold set. 【請求項１０】 請求項９記載の電子部品の組立装置に
おいて、前記封止手段は、前記キャビティを減圧する減
圧手段を更に備えたことを特徴とする電子部品の組立装
置。10. The electronic component assembling apparatus according to claim 9, wherein said sealing means further comprises a pressure reducing means for reducing the pressure in said cavity.
JP31620999A 1999-11-08 1999-11-08 Method and system for assembling electronic device Pending JP2001135658A (en)

Priority Applications (4)

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JP31620999A JP2001135658A (en) 1999-11-08 1999-11-08 Method and system for assembling electronic device
US09/705,239 US6358776B1 (en) 1999-11-08 2000-11-02 Method of fabricating an electronic component and apparatus used therefor
KR1020000065501A KR20010070191A (en) 1999-11-08 2000-11-06 Method of fabricating an electronic component and apparatus
TW089123509A TW479013B (en) 1999-11-08 2000-11-07 Method of fabricating an electronic component and apparatus used therefor

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