JP2737479B2 - Semiconductor stress detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving the characteristics of a semiconductor stress detecting device using a polycrystalline Si piezoresistor.

[0002]

2. Description of the Related Art As a conventional semiconductor stress detecting device, for example, "Micro-Diaphragm Pressure Sensor" Proceedin
gs of the 6th Sensor Symposium, 1986. pp. 23-27 ". FIGS. 5A and 5B are diagrams showing an example of the semiconductor pressure detecting device as described above, wherein FIG. 5A is a plan view and FIG.
FIG. 4A is a cross-sectional view taken along the line BB ′ of FIG. In FIG.
Is a cavity formed by etching in the Si substrate 26, 29
Is a Si ₃ N ₄ film defining the cavity 21. Reference numeral 22 denotes a diaphragm which is hermetically formed so as to cover the cavity 21, and is composed of Si ₃ N ₄ films 27, 28 and ₃₀ . The diaphragm 22 is formed with p-type polycrystalline Si piezoresistors 23 and 24 sandwiched between Si ₃ N ₄ films 27 and 28. The piezoresistor 23 is formed at the periphery of the diaphragm, and the piezoresistor 24 is formed at the center of the diaphragm. Reference numeral 25 denotes an etching hole used for etching the cavity 21, which is sealed with a Si ₃ N ₄ film 30.

Next, a brief description will be given of a manufacturing method. (10
A Si ₃ N ₄ film is deposited on the (0) plane Si substrate by LPCVD, and a window is opened on a portion to be a cavity. Next, a portion to be a cavity is covered with a polycrystalline Si layer (not shown) serving as an etch channel, and a window is formed until the portion reaches the etching hole 25. On this, a Si ₃ N ₄ film 28 and a polycrystalline Si layer constituting the diaphragm 22 are sequentially formed by LPCVD, and boron is ion-implanted into the polycrystalline Si layer, followed by patterning to form piezoresistors 23 and 24. . next,
After covering the piezoresistor with the Si ₃ N ₄ film 27, an etching hole 25 is made, and the etch channel of polycrystalline Si and the Si substrate thereunder are etched with an anisotropic etching solution such as KOH to form a cavity 21. I do. Next, after forming contact etching and wiring electrodes (not shown), PECV
D deposits the Si ₃ N ₄ film 30 and seals the cavity.

When pressure is applied to the diaphragm structure as described above, stresses in opposite directions are generated at the center and the end of the diaphragm, and the resistance values of the piezo resistors 23 and 24 change to opposite polarities. By forming a bridge circuit with the resistors 23 and 24, a voltage corresponding to the pressure can be output. In such a surface type pressure sensor, miniaturization is possible because etching from the back side is not used, and the leak current is small because the piezo resistance of the polycrystalline Si film formed on the insulating film is used. There is an advantage that it can be operated even in a high temperature atmosphere.

[0005]

However, in such a conventional semiconductor stress detecting device, since the bridge is constituted only by the p-type polycrystalline Si piezoresistor, the maximum stress in the peripheral portion of the diaphragm is effectively used. However, since the horizontal gauge factor is a fraction of the vertical gauge factor, there is a problem that the sensitivity is low and non-linearity occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and has as its object to provide a semiconductor stress detecting device which has high sensitivity and less non-linear errors.

[0007]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as described in the claims. That is, in the present invention, a p-type polycrystalline Si piezoresistor is disposed on a structure where a stress is generated in response to the application of an external physical quantity, such that the direction of the current is parallel to the applied stress. A full bridge circuit is formed by forming a plurality of n-type polycrystalline Si piezoresistors, using the p-type polycrystalline Si piezoresistors as a pair of opposite sides, and using the n-type polycrystalline Si piezoresistors as another pair of opposite sides. The p-type polycrystalline Si piezoresistor and the n-type polycrystalline
The impurity concentration of the Si piezoresistors is
The absolute value of the rate of change with respect to the longitudinal stress
Equal values and the length in both piezoresistors
The temperature coefficient of the rate of change for the
The impurity concentration is set at a certain level. The external physical quantity is, for example, acceleration or pressure. In addition, the above-mentioned structural portion has, for example, a cantilever structure or a double-supported beam structure, and is formed of a semiconductor or an insulator. The piezoresistor is generally formed so that a current flows in the longitudinal direction of a rectangle, but is not limited to a rectangle and may be another shape such as a square.
In short, it is only necessary that the direction of current flow is parallel to the stress.

[0008]

According to the experiments of the present inventors, the resistance formed in the direction parallel to the applied stress and the resistance formed in the direction perpendicular to the stress in the p-type polycrystalline Si resistance and the n-type polycrystalline Si resistance. It was found that there was a large difference in the resistance change rate characteristics with respect to stress. FIGS. 3A and 3B are diagrams showing an example of the above-described resistance change rate characteristics. FIG. 3A shows the characteristics of a p-type polycrystalline Si resistor, and FIG. 3B shows the characteristics of an n-type polycrystalline Si resistor. As can be seen from FIG. 3A, in the p-type polycrystalline Si resistor, the resistance change rate with respect to the stress is significantly different between the resistance parallel to the stress and the resistance perpendicular to the stress, and the resistance change with respect to the temperature change. The rate of change of the rate is reversed. That is, the temperature dependency of the sensitivity is the opposite sign and the characteristic of the same polarity (the difference from 0 in the resistance change rate is
Parallel indicates a negative direction, and vertical indicates a positive direction, both of which are larger). Also, in the n-type polycrystalline Si resistor, the resistance change rate with respect to the stress is significantly different between the resistance parallel to the stress and the resistance perpendicular to the stress, and the temperature dependence of the sensitivity has the opposite sign and the opposite polarity characteristic (resistance The difference from 0 in the rate of change indicates that as the temperature decreases, the rate of change increases in the positive direction for parallel and decreases in the negative direction for vertical). The present invention has been made based on the above-described novel findings of the present inventors, and appropriately combines a p-type polycrystalline Si piezoresistance formed in parallel with stress and an n-type polycrystalline Si piezoresistance. A bridge circuit , and the p-type polycrystalline Si piezoresistor and the n-type
The impurity concentration with the polycrystalline Si piezoresistor is determined by
The absolute value of the rate of change of the resistance with respect to the longitudinal stress
Approximately equal value and length at both piezoresistors
Values of the temperature coefficient of change rate with respect to the stress in the vertical direction
By setting the impurity concentration as described above, a semiconductor stress detecting device with high sensitivity and good linearity is realized. That is , in the p-type polycrystalline Si piezoresistor formed at a predetermined impurity concentration and the n-type polycrystalline Si piezoresistor, the change characteristic of the resistivity with respect to the applied stress has the opposite sign (the resistance is changed in the p-type formed in parallel with the stress. The rate changes in the negative direction, and in the n-type, the rate changes in the positive direction), and the values are significantly different. Therefore, a full-bridge circuit is formed by using p-type polycrystalline Si piezoresistors formed in a direction parallel to the stress as a pair of opposite sides and n-type polycrystalline Si piezoresistors formed in a direction parallel to the stress as another pair of opposite sides. By doing so, the sensitivity can be greatly improved as compared with a conventional stress detection device using only a p-type polycrystalline Si piezoresistor.
Also, the rate of change of the p-type and n-type
Greater output (sensitivity) by aligning absolute values
And the stress of p-type and n-type piezoresistors
Temperature coefficient of change rate can be almost the same
When using polycrystalline silicon as the piezoresistor
Over a wide temperature range without adding a temperature compensation circuit
Non-linear errors can be reduced .

[0009]

FIG. 1 is a diagram showing an embodiment of the present invention.
Is a plan view, and (b) is a cross-sectional view taken along the line AA 'of (a). This embodiment illustrates a case where the present invention is applied to an acceleration sensor. In FIG. 1, 1 is a weight portion, and 2 is a thin-walled cantilever portion. The cantilever 2 is fixed to a base 10 via a support 9. Reference numeral 3 denotes a groove formed so as to surround the weight 1 and the cantilever 2. On the cantilever portion 2, p-type polycrystalline Si piezoresistors 4 and 5 and n-type polycrystalline Si piezoresistors 6 and 7 are formed in a direction parallel to the applied stress. The arrow 50 indicates the direction of the applied stress. These polycrystalline Si piezoresistors 4 to 7 are connected by metal wiring 8 to form a full bridge circuit as shown in the equivalent circuit of FIG. 11 and 12 are silicon oxide films.

As a method of forming such a semiconductor acceleration sensor, the following process flow can be considered.
First, an oxide film 11 is formed on a silicon substrate.
Polycrystalline silicon is deposited by CVD, and boron and phosphorus or arsenic are ion-implanted into a p-type or n-type resistance forming region using a photoresist as a mask. After patterning, an oxide film 12 for surface insulation is formed.
To form Next, 900 to 1100 ° C. in a nitrogen atmosphere
Is performed, contact holes (not shown) are etched, and metal electrodes 8 are deposited and patterned. Finally, patterning of the oxide film is performed, and Si etching for forming the groove portion 3 from the front surface side and Si etching for forming the cantilever portion 2 and the weight portion 1 from the back surface side are performed. Here, for the etching of Si, anisotropic etching of ethylene / diamine / pyrocatechol aqueous solution, hydrazine, KOH or the like, or isotropic etching of hydrofluoric / nitric acid may be used. For the groove 3, dry etching can be used. In addition to the oxide film, a silicon nitride film or a resist may be used as the mask material.

Next, the operation will be described. When an acceleration is applied in a direction perpendicular to the main surface of the substrate, a stress in the length direction of the beam as shown by an arrow 50 is generated on the surface of the cantilever 2. When the acceleration is downward, a tensile stress is generated on the beam surface.
When such a stress is applied, the resistance values of the p-type polycrystalline piezo resistors 4 and 5 increase as shown in FIG.
Since the resistance values of the type polycrystalline piezoresistors 6 and 7 decrease, a large voltage output corresponding to the acceleration can be obtained by configuring a bridge circuit as shown in FIG. In addition,
In FIG. 3, since the applied stress on the horizontal axis is indicated by a negative value, the characteristics are opposite to those described above.

The gauge factor of polycrystalline Si greatly depends on the process. For example, a film was deposited by LPCVD of 625 ° C., longitudinal gage factor of boron 5 × 10 ¹⁵ cm ~ ² ion-implanted p-type polycrystalline Si resistor 24, phosphorus was 5 × 10 ¹⁵ cm ~ ² ion implantation Experiments have confirmed that the longitudinal gauge factor of the n-type polycrystalline Si resistor is -24. At this time, the temperature coefficient of the gauge factor is-
It turned out that it is about 1200 ppm / K. Therefore, by forming a full bridge circuit with p-type and n-type polycrystalline Si piezoresistors under such a dose condition, a large output is obtained and the symmetry is good, so that the output distortion at the time of large input is reduced. You can do it. Moreover, transverse gage factor in this case was 0.16 in those 5 × 10 ¹⁵ cm ~ ² ion implanting boron -5.4, in which phosphorus was 5 × 10 ¹⁵ cm ~ ² ion implantation. Therefore, when a bridge is formed with only the p-type or n-type, the sensitivity is about half as compared with the above-described embodiment, and a non-linear error occurs due to the asymmetry of the bridge at a large input.

FIG. 4 is a plan view of another embodiment of the present invention, showing a case where the present invention is applied to a pressure sensor.
The same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 4, p-type polycrystalline Si piezoresistors 4 and 5;
The n-type polycrystalline Si piezoresistors 6 and 7 are formed on the peripheral portion of the diaphragm 13 under pressure, perpendicular to the sides of the diaphragm, that is, parallel to the applied stress.
When pressure is applied to the diaphragm 13, the stress in the direction perpendicular to the side becomes particularly large in the peripheral portion. Therefore, as shown in the figure, p-type and n-type piezoresistors are provided in the stress direction to form a bridge. , A large output can be obtained.
Other operations and effects are the same as those of the embodiment of FIG.

In the above-described embodiments, an example of a stress detecting device having a thin-walled structure has been described. However, the present invention can be applied to a stress detecting device having no thin-walled structure. Effects can be obtained. Further, in the embodiments described above, the example in which the polycrystalline Si piezoresistor is formed on the semiconductor substrate is shown. However, the present invention is not limited to the semiconductor substrate, and the polycrystalline Si piezoresistor may be formed on an insulating substrate. Similar effects can be obtained.

[0015]

As described above, according to the present invention, a bridge circuit is formed by appropriately combining a p-type polycrystalline Si piezoresistor and an n-type polycrystalline Si piezoresistor formed in parallel with a stress. As a result, (1) a large output can be obtained as compared with a p-type or n-type only piezoresistive bridge circuit. (2) a large input can be obtained by making the vertical gauge ratios of the p-type and n-type piezoresistors uniform. (3) p-type polycrystalline Si piezoresistor and n-type polycrystalline Si piezoresistor
Since the temperature coefficient with the resistance can be made almost the same,
The effect is obtained that the temperature characteristics are also improved .

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view of a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the embodiment of FIG.

FIG. 3 is a characteristic diagram showing a relationship between an applied stress and a resistance change rate depending on a direction in which a piezoresistor is formed.

FIG. 4 is a plan view and a cross-sectional view of a second embodiment of the present invention.

FIG. 5 is a plan view and a cross-sectional view of a conventional device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Weight part 2 ... Cantilever part 3 ... Groove part 4, 5 ... p-type polycrystal S formed in the direction parallel to the applied stress
i-resistance 6, 7,... n-type polycrystal S formed in a direction parallel to the applied stress
i resistance 8 ... electrode wiring 9 ... silicon substrate 10 ... base 11, 12 ... silicon oxide film 13 ... diaphragm 21 ... cavity 22 ... diaphragm 23, 24 ... p-type polycrystalline Si resistance 25 ... etching hole 26 ... Si substrate 27- 30: Si ₃ N ₄ film 50: arrow indicating the direction of applied stress

Claims (1)

(57) [Claims] 1. A p-type polycrystal Si disposed on a structure in which a stress is generated in response to the application of an external physical quantity such that the direction of a current flowing through the resistor is parallel to the applied stress.
A plurality of piezoresistors and a plurality of n-type polycrystalline Si piezoresistors are formed, and the above-mentioned p-type polycrystalline Si piezoresistors constitute one pair of opposite sides, and the n-type polycrystalline Si piezoresistors constitute another pair of opposite sides. A circuit , and p
Between the n-type polycrystalline Si piezoresistor and the n-type polycrystalline Si piezoresistor
The impurity concentration is adjusted in the longitudinal direction of the piezoresistors.
Make the absolute value of the rate of change with respect to force approximately equal and
Changes in longitudinal stress in the above piezoresistors
Set the impurity concentration so that the temperature coefficient of
And semiconductor stress detecting device, characterized in that.