JP2734216B2 - Integrated circuit with built-in clock skew adjustment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit with a built-in clock skew adjustment circuit, and more particularly to an integrated circuit with a built-in clock skew adjustment circuit in an information processing apparatus requiring a large number of large-scale integrated circuits.

[0002]

2. Description of the Related Art Generally, an information processing apparatus is composed of a large number of large-scale integrated circuits, and a clock signal is distributed to each large-scale integrated circuit for synchronization. Conventionally, this clock signal is time-adjusted at the entrance of the integrated circuit by a delay element or a cable or the like, and the clock skew is reduced by unifying the clock distribution circuit in each integrated circuit.

[0003]

In the prior art, a clock signal is adjusted at the entrance of an integrated circuit. However, in a large-scale integrated circuit, there are hundreds to thousands of registers, and several stages are required to distribute a clock. Need a gate. For this reason, even if the clock distribution circuits (the number of gate stages) are unified, there is a disadvantage that skew occurs even in the same integrated circuit due to manufacturing variations of the integrated circuit. In particular, the clock cycle is becoming smaller at present, and the integrated circuit is highly integrated, so that the manufacturing variability becomes large and the skew of the clock cycle occupies a large problem.

[0004]

According to the present invention, there is provided an integrated circuit with built-in clock skew adjustment, comprising a plurality of delay circuits capable of varying a delay time of a clock signal by an external terminal and a plurality of registers for controlling the delay-controlled clock signal. A clock skew adjustment built-in integrated circuit including a plurality of distribution circuits configured by a plurality of gates for distribution to the
A register having one of an output of any one of the plurality of distribution circuits as a clock input and the other as a data input ;
A plurality of output signals corresponding to the data input of the register;
Signal level is LOW → HIGH (or HIGH → LO
W) so that the timing of change to
By adjusting the delay time of the delay circuit,
Set the menu to zero .

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Now, the clock distribution circuit in the integrated circuit is divided into four blocks, each comprising delay circuits D1 to D4, clock distribution circuits B1 to B4, and load register groups L1 to L4. One output of the clock distribution circuits B1 to B3 is connected to data inputs d1 to d3 of the register RC, respectively, and one output of the distribution circuit B4 is connected to the clock input of the register RC. The delay amounts of the delay circuits D1 to D4 can be varied by external control terminals S1 to S4.

FIG. 2 is a circuit diagram showing details of the delay circuit shown in FIG. When a clock signal is input to the external terminal CLK, it is input to the register RC. Although the data input and the clock signal have the same cycle, skew occurs due to the variation in the delay amount of the delay circuit and the gate delay. Assuming that the register clock is valid at the time of rising, the external control terminal S1
To S3, the delay amounts of the delay circuits D1 to D3 change, and the outputs Q1 to Q3 of the register RC are Low.
→ When changing to the High level, the distribution circuits B1 to B1 correspond to the delay time from the clock terminal of the distribution circuit B4 to the register.
This means that the delay time from the clock terminal No. 3 to the register matches. (However, at this time, initially, the delay amount of the delay circuit D4 is intermediate, and the delay circuits D1 to D3 are minimized.) Variation in gate delay in the integrated circuit occurs due to a difference in the physical position of the gate in the chip. I do. In this description, the in-chip register is divided into four blocks, but the skew is further reduced by increasing the number of divisions.

[0008]

As described above, according to the present invention, a plurality of delay circuits capable of varying the delay of a clock signal by an external terminal, a plurality of distribution circuits for distributing a clock signal whose delay is controlled, By using a register in which one of the outputs of each of the plurality of distribution circuits is a clock input and the other is a data input, clock skew due to variation in gate delay in the integrated circuit can be easily controlled by controlling the delay amount of the delay circuit. Has the effect of being able to be zero.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a delay circuit shown in FIG. 1;

[Explanation of symbols]

 B1 to B4 Clock distribution circuit D1 to D4 Delay circuit S1 to S4 External control terminal RC register

Claims (1)

(57) [Claims] 1. A plurality of distribution circuits each comprising a plurality of delay circuits capable of varying a delay time of a clock signal by an external terminal, and a plurality of gates for distributing the delay-controlled clock signal to a plurality of registers. Circuit and including
A clock skew adjustment built-in integrated circuit , comprising: a register for inputting one of an arbitrary output of each of the plurality of distribution circuits as a clock input and the other as a data input;
A plurality of output signal levels corresponding to the data input of the star
Changes from LOW to HIGH (or HIGH to LOW)
Of the plurality of delay circuits so that
Clock skew to zero by adjusting delay time
An integrated circuit with built-in clock skew adjustment.