JP2002232286A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a programmable impedance control circuit capable of simple impedance updating control. SOLUTION: The programmable impedance control circuit is provided with a clock frequency dividing signal line 61, which is the signal line of a clock frequency dividing signal dividing the frequency of a system clock CK in the same cycle as the updating cycle of the impedance of an output buffer, and a voltage comparator circuit 51 compares a current VZQ flowing in an external resistor RQ with a current DBUF flowing in a dummy buffer by the clock frequency dividing signal 32 CK. Then, an up/down counter circuit 52 controls an output buffer size on the basis of the compared result of the voltage comparator circuit 51 synchronously with the system clock CK and in a specified operating state such as read, write or Nop activating an OE signal, an updating control register circuit 53 updates output buffer size data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a programmable impedance control circuit having a function of adjusting the impedance of an output buffer circuit in accordance with an external resistance. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art Due to variations in manufacturing processes such as process variations and deviations, as well as operating conditions (operating temperature, operating voltage, etc.), characteristics relating to an effective driving force of an output circuit transistor such as a memory chip are changed. Change. To solve this problem, there is a circuit shown in FIG. 8 as an example that realizes a function of correcting the driving force to a desired value by changing the transistor size in a circuit.

FIG. 7 is a block diagram showing a conventional programmable impedance control circuit.

This programmable impedance control circuit is constituted by circuits 112 to 120 for adjusting the output impedance of the output buffer circuit 111. For example, by externally connecting the impedance of a bus that the user wants to match as a resistor RQ to the ZQ terminal, control is performed so as to change the transistor size of the output buffer circuit 111 so that the impedance of the output buffer circuit 111 matches the resistor RQ. .

[0005] The programmable impedance control circuit of this embodiment comprises an evaluation circuit 112, a voltage comparison circuit 113,
It comprises an up / down (U / D) counter 114, registers 115, 116, 117, a selector 118, a data update controller 119, and a sampling clock generation circuit 120.

The evaluation circuit 112 includes a reference current source circuit including an NMOS transistor 112a and resistors R0 and R1,
A dummy buffer circuit (1X, 2) having the same circuit type (or a size as a constant multiple) as the output buffer circuit 111
X, 3X, 4X), and applies the voltage VZQ of the ZQ terminal generated by the reference current source circuit and the voltage (drain voltage) DBUF applied to the dummy buffer circuit to the voltage comparison circuit 113.

An up / down counter 1 that counts up / down according to the output of the voltage comparison circuit 113
14 switches on / off the NMOS transistors 1X to 4X of the dummy buffer circuit so that the voltage VZQ and the voltage DBUF match. In this way, control is performed so that the impedance of the dummy buffer circuit matches the external resistance RQ.

Then, data corresponding to the matching impedance of the dummy buffer circuit is sent to the output buffer circuit 111 via the data update controller 119, and based on the data, an external driving circuit constituting the output buffer circuit 111 is used. Transistors 1Y to 8Y, 1Z to 8
Z is selectively turned on / off. As a result, the output buffer circuit 111 is set to an impedance determined by the external resistance RQ.

As described above, in the programmable impedance control circuit, since the set output impedance changes due to the temperature change of the operating chip and the fluctuation of the power supply voltage, it is necessary to periodically update the output impedance. Usually, in order to prevent the output buffer impedance from being updated frequently, the output impedance update interval is set to a predetermined interval according to specifications. There is also a restriction that the update of the output impedance must be in a specific operating state such as read, write, or nop (Nop) in the case of a memory, for example.

In the programmable impedance control circuit, in order to satisfy these conditions, as shown in FIG. 8, a counter circuit 20 for counting the number of cycles (update cycle) corresponding to the update interval for counting the update interval.
2 and a control signal generation circuit 203 for generating and outputting a CKHz signal for detecting an update permission state to the update control register circuit 201 is required.

More specifically, the programmable impedance control circuit 200 shown in FIG. 8 sets the update interval to an interval of 32 system clocks CK.
The case where the voltage comparison circuit 113 and the up / down (U / D) counter circuit 114 are operated by a clock 4CK obtained by dividing the system clock CK by 4 is shown.

In this circuit 200, in order to recognize an update cycle of 32 clocks, the counter circuit 20
A 32CK counter 202 that counts 32 clocks as 2 and a control signal generation circuit 203 that outputs a CKHz signal when the counter 202 counts 32 clocks are required. Then, the update control register circuit 201 updates data when the CKHz signal is input.

The update control register circuit 201 shown in FIG. 8 corresponds to the registers 115, 116, and 117 shown in FIG.
It comprises a selector 118 and a data update controller 119.

[0014]

As described above, the conventional programmable impedance control circuit not only requires the counter circuit 202 and the control circuit 203, but also integrates these circuits to integrate the entire programmable impedance control circuit. Therefore, there has been a problem that the entire control becomes very complicated because the matching must be performed. In addition, this complexity has the disadvantage that circuit verification and the like are troublesome and time-consuming.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device having a programmable impedance control circuit capable of performing simple impedance update control. is there.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein a connection terminal for connecting an external resistor and an external transistor having a different transistor size and connected in parallel are provided. A semiconductor device comprising: an output buffer having a driving transistor group; and output impedance control means for automatically adjusting the impedance of the output buffer according to a value of the external resistance based on a system clock. A dummy buffer having the same format as the output buffer, a clock divided signal line that is a signal line of a clock divided signal obtained by dividing the system clock in the same cycle as the update cycle of the impedance of the output buffer, A current flowing through the connection terminal and the dummy buffer, A comparison unit that compares the flowing current; and an output control unit that controls the size of the output buffer according to output data of the comparison unit and stores information on the output buffer size. .

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the output control means converts the output data of the comparison means by a clock signal having the same cycle as the system clock signal. Counting means for incrementing / decrementing data accordingly;
Data storage means for storing / outputting output data of the counting means in response to the clock signal.

In the semiconductor device according to a third aspect of the present invention, in the semiconductor device according to the first aspect, the output control means increments / decrements data in accordance with output data of the comparison means by the clock divided signal. A counting means for decrementing, and a data storage means for storing / outputting output data of the counting means in response to the clock signal.

According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the output control means increments / decrements the data in accordance with the output data of the comparison means by the clock signal. A counting means; and a data storage means for storing / outputting output data of the counting means in accordance with the clock frequency-divided signal.

According to a fifth aspect of the present invention, in the semiconductor device according to the first aspect, the output control means increments / decrements data in accordance with output data of the comparison means by the clock divided signal. It is characterized by comprising a counting means for decrementing, and a data storage means for storing / outputting output data of the counting means in accordance with the clock divided signal.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a circuit diagram showing a programmable semiconductor device mounted on a semiconductor device according to a first embodiment of the present invention.
FIG. 3 is a block diagram of a main part of the impedance control circuit. FIG.
FIG. 2 is a block diagram of a main configuration of a memory chip constituting a semiconductor device including the programmable impedance control circuit of FIG.

First, referring to FIG.
Is configured such that address data input from an address pad 36 via an address buffer 37 is supplied to a row selector 32 and a column selector 33, and a desired write cell or read cell in the memory array 31 is selected. Have been.

Although the address buffer 37 is shown as a single unit in FIG. 2 for simplicity of description, the address data is actually composed of n-bit row address data and m-bit column address data. Correspondingly, the address pads 36 are arranged in a plurality of n + m pieces, and the address buffer 37 is composed of n row address buffers and m column address buffers. Then, n row address buffers are connected to the row selector 32, and m column address buffers are connected to the column selector 33. Similarly, when the data bus 63 has k bits, the I / O pads 20 are correspondingly arranged in a plurality of k pieces, and the input buffer circuit 38 and the output buffer circuit 1 each have k bits.
It will be composed of a plurality of pieces.

At the time of writing, write data input from the I / O pad 20 is applied to the write buffer 35 via the input buffer circuit 38, and is written to a desired write cell in the memory array 31. On the other hand, at the time of reading, the read data read from the selected read cell is supplied to the output buffer circuit 1 via the sense amplifier 34, and from the output buffer circuit 1 to the outside of the chip via the I / O pad 20. It is designed to be driven. The timing control signal from the timing control circuit 39 via the buffer 40 is supplied to the row selector 3.
2. The operation timing is supplied to the column selector 33, the sense amplifier 34, and the write buffer 35 to control the operation timing at the time of writing or reading.

A programmable impedance control circuit (output impedance control circuit) 10 for automatically adjusting the impedance of the output buffer circuit 1 is provided inside the memory chip 30.

Specifically, as in the conventional case, the external resistance RQ for designating the impedance to be matched is set to Z
Connected to the Q terminal, inside the memory chip 30, the transistor size of the output buffer circuit 1 is adjusted such that the impedance of the output buffer circuit 1 becomes the value of the external resistor RQ (or a constant multiple thereof). That is, the dummy buffer circuit (1X, 2X, 3X, 4X) having the same circuit format as the output buffer circuit 1 (or the size is a constant multiple)
X) while changing the transistor size, search for a size such that the impedance of the dummy buffer circuit (1X, 2X, 3X, 4X) becomes equal to the external resistance RQ.
The result is reflected in the output buffer circuit 1.

The programmable impedance control circuit 10 according to the present embodiment shown in FIG. 2 has a configuration corresponding to the conventional circuit shown in FIG. 8 in the overall configuration shown in FIG. It has a voltage comparison circuit 51, an up / down (U / D) counter 52, and an update control register circuit 53, and the output side of the update control register circuit 53 is connected to the output buffer circuit 111 shown in FIG. It has a configuration.

As described above, the voltage comparison circuit 51 includes a current path (VZQ) flowing through an external resistor RQ for programming a desired output impedance and a path (DBU) flowing through a dummy buffer (1X, 2X, 3X, 4X).
One of the features of the present embodiment is that the clock signal for synchronizing this operation uses a clock signal having the same cycle as the output impedance update cycle described above. is there. That is, when the update cycle of the output impedance is set to, for example, 32 clocks of the system clock CK, the system clock C
The clock division signal 32CK obtained by dividing K by 32 is used.

Up / down (U / D) counter circuit 52
Is synchronized with the system clock CK,
This is a circuit for controlling the output buffer size based on the comparison result of 1. More specifically, an up / down count is performed according to the output of the voltage comparison circuit 51, and the voltage VZQ and the voltage DBUF are compared with each other. Are turned on / off so that the NMOS transistors 1X to 4X of the dummy buffer circuit match. Thus, the output buffer size is controlled so that the impedance of the dummy buffer circuit matches the external resistance RQ.

Then, the update control register circuit 53 operates in synchronization with the system clock CK, holds the value of the output buffer size, and enters an update-permitted operating state in which the output enable OE signal is activated ( For example, read operation), data update, that is, the output buffer size is updated.

Here, a voltage comparison circuit 51, an up / down (U / D) counter 52, and an update control register circuit 5
3, clock signals 32CK, CK, C
K is generated by, for example, the timing control circuit 39 in the memory chip 30, and each of the clock signal lines 61,
The power is supplied through the respective channels 62 and 63.

As described above, the voltage comparison circuit 51 operates in synchronization with the clock signal. However, as shown in the timing chart of FIG. 3, the cycle of this clock signal has the same cycle as the update cycle, for example, the system clock CK. Is updated to a clock frequency-divided signal 32CK obtained by dividing the frequency by 32, and the update control register circuit 53 updates the data when a specific operating state such as a read or the like (which may be a write or a nop) activated by the OE signal is obtained.

As a result, the data in the programmable impedance control circuit 10 becomes one in the update cycle.
Therefore, the number of update cycles does not need to be counted as in the related art. Therefore, a counter circuit for counting an update cycle and a control signal generation circuit for generating a control signal for update are not required, and the update control can be performed with a simple system.

[Second Embodiment] FIG. 4 is a circuit diagram showing a programmable semiconductor device mounted on a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a block diagram of a main part of the impedance control circuit.

The programmable impedance control circuit according to this embodiment differs from the circuit configuration of the first embodiment in that the up / down counter circuit 52 that operates in synchronization with the system clock CK is replaced by a signal line 62a. An up / down counter circuit 52a that operates in synchronization with the supplied clock divided signal 32CK is provided. The clock divided signal 32CK is a clock signal obtained by dividing the system clock CK by 32 in the same manner as described above.

Even with such a configuration, the same effect as in the first embodiment can be obtained.

[Third Embodiment] FIG. 5 shows a programmable semiconductor device mounted on a semiconductor device according to a third embodiment of the present invention.
FIG. 3 is a block diagram of a main part of the impedance control circuit.

The programmable impedance control circuit according to the present embodiment is supplied via a signal line 63a instead of the update control register circuit 53 operating in synchronization with the system clock CK in the circuit configuration of the first embodiment. And an update control register circuit 53a that operates in synchronization with the clock frequency division signal 32CK.

With this configuration, the same effects as those of the first embodiment can be obtained.

[Fourth Embodiment] FIG. 6 is a diagram showing a programmable semiconductor device mounted on a semiconductor device according to a fourth embodiment of the present invention.
FIG. 3 is a block diagram of a main part of the impedance control circuit.

The programmable impedance control circuit according to the present embodiment is different from the circuit configuration of the first embodiment in that the up / down counter circuit 52 and the update control register circuit 5 which operate in synchronization with the system clock CK.
Instead of 3, an up / down counter circuit 52a and an update control register circuit 53a that operate in synchronization with the clock frequency division signal 32CK supplied via signal lines 62a and 63a, respectively, are provided.

Even with such a configuration, the same effect as that of the first embodiment can be obtained.

[0044]

As described above in detail, according to the present invention, the output impedance control means is a signal line of a clock divided signal obtained by dividing the system clock in the same cycle as the output buffer impedance update cycle. A clock frequency dividing signal line is provided, and the comparing means compares the current flowing through the external resistor with the current flowing through the dummy buffer according to the clock frequency dividing signal. Since it changes only at intervals, there is no need for a counter circuit for counting update cycles or a control signal generation circuit for generating a control signal for updating as in the conventional technology, and simple impedance update control is possible. Become.

As a result, the layout area can be reduced, the operation speed can be increased at a high frequency, and the control of the entire circuit can be simplified, so that the circuit can be easily verified.

[Brief description of the drawings]

FIG. 1 is a main block diagram of a programmable impedance control circuit mounted on a semiconductor device according to a first embodiment of the present invention.

2 is a main configuration block diagram of a memory chip included in a semiconductor device including the programmable impedance control circuit of FIG. 1;

FIG. 3 is a timing chart showing the operation of the embodiment.

FIG. 4 is a main block diagram of a programmable impedance control circuit mounted on a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a main part block diagram of a programmable impedance control circuit mounted on a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a main block diagram of a programmable impedance control circuit mounted on a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is an overall block diagram showing a conventional programmable impedance control circuit.

FIG. 8 is a main block diagram showing a conventional programmable impedance control circuit.

[Explanation of symbols]

 Reference Signs List 10 Programmable impedance control circuit 51 Voltage comparison circuit 52, 52a Up / down (U / D) counter 53, 53a Update control register circuit 61, 62, 63 Clock signal line 111 Output buffer circuit RQ External resistance

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/00 101S F-term (Reference) 5B015 HH01 JJ24 JJ37 KB33 KB82 KB84 NN03 5J056 AA04 BB01 BB02 BB51 BB54 BB57 CC00 CC09 CC17 DD13 DD28 EE11 EE15 FF01 FF07 FF08 GG13 KK01 5M024 AA44 AA49 AA55 BB04 BB33 DD52 DD60 JJ02 JJ32 PP01 PP02 PP03

Claims (5)

[Claims] 1. A connection terminal for connecting an external resistor, an output buffer having a different transistor size and having a group of transistors for external driving connected in parallel, and a system clock, in accordance with a value of the external resistor. In a semiconductor device having output impedance control means for automatically adjusting the impedance of the output buffer, the output impedance control means includes: a dummy buffer having a format similar to that of the output buffer; and an update cycle of the impedance of the output buffer. A clock divided signal line which is a signal line of a clock divided signal obtained by dividing the system clock in the same cycle, and a current flowing through the connection terminal and a current flowing through the dummy buffer are compared by the clock divided signal. Comparing means, and the output buffer according to output data of the comparing means. Controls the size of the file, a semiconductor device characterized by comprising an output control means for storing information of the output buffer size. 2. The output control means includes: a counting means for incrementing / decrementing data in accordance with output data of the comparing means with a clock signal having the same cycle as the system clock signal; 2. The semiconductor device according to claim 1, further comprising data storage means for storing / outputting output data of said means. 3. The output control means includes: a counting means for incrementing / decrementing data in accordance with output data of the comparing means in accordance with the clock frequency division signal; and an output data of the counting means in accordance with the clock signal. 2. The semiconductor device according to claim 1, further comprising: a data storage unit for outputting / outputting data. 4. The output control means includes: a counting means for incrementing / decrementing data in accordance with output data of the comparing means in accordance with the clock signal; and an output data of the counting means in accordance with the clock frequency dividing signal. 2. The semiconductor device according to claim 1, further comprising: a data storage unit for outputting / outputting data. 5. The output control means includes: a counting means for incrementing / decrementing data in accordance with output data of the comparing means in accordance with the clock frequency dividing signal; and an output data of the counting means in accordance with the clock frequency dividing signal. 2. The semiconductor device according to claim 1, further comprising data storage means for storing / outputting the data.