JPH05241679A - Integrated circuit incorporating clock skew adjustment circuit - Google Patents

Abstract

PURPOSE:To set a skew zero by varying the delay of clock signal by means of the external control terminal. CONSTITUTION:When a selection circuit 1 selects the output of clock distribution circuit by means of an external terminal SLA, loop is formed from a selection circuit 1, delay circuit 2, clock distribution circuit 3, and to the selection circuit 1. The loop comprises a ring oscillator, and whose oscillation frequency is observed by an external terminal OUT. By controlling the delay amount of the delay circuit 2 by means of an external control terminal SLB, the oscillation frequency can be adjusted to the specific value. Thus, as the delay time from the clock terminal to register of each integrated circuit can be set to the constant value and the clock skew is determined by the setting accuracy of the delay circuit, the skew becomes zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having a clock skew adjusting circuit.

[0002]

2. Description of the Related Art Generally, an information processing apparatus is composed of a large number of large scale integrated circuits, and a clock signal is distributed to each large scale integrated circuit for synchronization. In the prior art,
This clock signal is time-adjusted at the entrance of the integrated circuit by a delay element or a cable, and the clock distribution circuit in each integrated circuit is unified to reduce the clock skew.

[0003]

In the above-mentioned technique, the clock signal is adjusted at the entrance of the integrated circuit, but in a large scale integrated circuit, the number of registers is several hundreds to several thousands, and several stages are required to distribute the clock. Need a gate. For this reason, even if the clock distribution circuits are unified, there is a drawback that skew occurs between the integrated circuits due to manufacturing variations of the integrated circuits. Particularly, at present, the clock cycle becomes smaller, and the integrated circuit is highly integrated, so that the manufacturing variation thereof becomes large, and the skew of the clock cycle becomes large, which is a problem.

[0004]

SUMMARY OF THE INVENTION An integrated circuit with a clock skew adjusting circuit according to the present invention includes a delay circuit capable of varying a delay time of a clock signal by an external control terminal, and a plurality of the delay-controlled clock signals. And a selection circuit for outputting either of the distributed clock signal or a clock signal supplied from the outside to the delay circuit. is doing.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. If the selection circuit 1 is now selecting the output of the clock distribution circuit by the external terminal SLA, the selection circuit →
A loop is formed like a delay circuit → clock distribution circuit → selection circuit. This loop constitutes a ring oscillator, and its oscillation frequency is observed by the external terminal OUT. The oscillation frequency can be adjusted to a specific value by controlling the delay amount of the delay circuit with the external control terminal SLB. The oscillation frequency of the ring oscillator is determined by the delay times of the selection circuit 1, the delay circuit 2 and the clock distribution circuit 3. Further, in general, the variations in the rise time and the fall time of the integrated circuit are in the same direction. (That is, the slower the rising edge is, the slower the falling edge is). Therefore, the variation in the delay time from the external clock terminal CLK to the register can be known from the oscillation frequency.

That is, by adjusting the oscillation frequency to a certain value, the delay time from the clock terminal of each integrated circuit to the register is set to a certain value in an information processing device composed of a large number of large scale integrated circuits. Therefore, the clock skew is determined by the setting accuracy of the delay circuit, and the skew becomes substantially zero. Further, the conventional adjustment of the clock skew has been performed on a board or device basis, but according to the present invention, it is possible to perform adjustment on an integrated circuit unit basis, which has the effect of reducing the adjustment time and cost.

FIG. 2 is a circuit diagram showing the details of FIG. The gates G to G7 and the selection circuits S2 to S4 form a delay circuit, and the delay amount can be changed by the external control terminals SL2 to SL4. The gates G8 to G13 form a two-stage clock distribution circuit, and outputs are output from the registers R11 to R11.
It is connected to R13, R21 to R23, R31 to R33, and R41. Selection circuit S1 by external selection signal SL1
Selects the output of the clock distribution circuit, the ring oscillator is configured as described above, and the oscillation frequency is adjusted by the external control terminals SL2 to SL4. Then external selection signal SL
The normal operation becomes possible by selecting the external clock terminal CLK by 1.

[0009]

As described above, according to the present invention, the delay circuit capable of varying the delay of the clock signal by the external control terminal, the distribution circuit for distributing the delay-controlled clock signal, and the distributed clock signal. The delay time from the clock terminal in the integrated circuit to the register or the register can be easily adjusted by the selection circuit for outputting either the clock signal supplied from the external circuit or the clock signal supplied from the outside, and the skew can be substantially zero. There is an effect that can be. In addition, skew adjustment can be performed by the integrated circuit alone, which has the effect of reducing adjustment time and cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of FIG.

[Explanation of symbols]

 1 selection circuit 2 delay circuit 3 clock distribution circuit

Claims (1)

[Claims] 1. A delay circuit for delaying a clock signal, and a control terminal for controlling a delay amount of the delay circuit,
A clock distribution circuit composed of a plurality of gates for distributing the delay-controlled clock signal to a plurality of registers, and one of the distributed clock signal and a clock signal supplied from the outside to the delay circuit. An integrated circuit with a built-in clock skew adjustment circuit, comprising: a selection circuit for outputting.