JP2728774B2 - Speed control device for rotating body - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a speed control device for a rotating body, particularly to a speed control device with simplification and high accuracy.

2. Description of the Related Art In speed control of a rotating body that requires precise constant-speed rotation, for example, speed control of a drum, a capstan or the like of a video tape recorder, an AC signal having a frequency proportional to the rotating speed of the rotating body is applied. 2. Description of the Related Art A frequency generator (hereinafter, referred to as FG) that generates a signal and a speed detector that generates a control output corresponding to the frequency of an FG signal as an output thereof are widely used.

FIG. 3 is a block diagram showing the basic structure of the motor, (1) is a motor, (2) is an FG, (3) is an FG signal,
(4) is a speed detector, (5) is a waveform shaper for generating a speed proportional signal (6) having a leading edge and a trailing edge from the FG signal (3), and (7) is a period of the speed proportional signal (6). , And a cycle detector that generates a control output (8) according to the
(9) is a filter for smoothing or phase compensating the control output (8), and (10) is a motor drive circuit. This conventional example shows a so-called direct drive system in which a rotating body and a rotor of a motor (1) are directly connected.

Now, in such a speed control system, it is generally well known that the FG frequency should be set high in order to increase the stability of the system and improve the rotational performance. This is because, as will be described later, as the FG frequency is higher, the phase delay of the speed detector (4) is reduced, and the ripple frequency of the output is higher, so that when the filter (9) in the subsequent stage is used. This is because the constant can be small and the phase margin of the control system is increased.

However, in an actual system, FG
The frequency cannot be set too high. Accordingly, various devices have been devised so as to obtain sufficient performance even at a low FG frequency, and the most typical method is phase compensation using a filter. However, this method stabilizes a system that is originally unstable or close to it by deforming a part of the gain or phase frequency characteristics of the system. Such a fundamental performance improvement cannot be expected.

Since the operation of such a speed control device as a whole is already widely known, the following description will focus on the speed detector according to the present invention.

First, the operation of the conventional speed detector (4) shown in FIG. 3 will be described.

If the rotation speed of the motor is Nmo and the FG frequency is fc, they are in a proportional relationship. It is expressed as Here, KG is a speed-frequency conversion constant.

Now, consider a case where the rotation speed changes with time. That is, Nm (t) = Nmo + ΔNm (t) (2) FIG. 4 shows the operation of the speed detector (4) at this time.

When the rotation speed of the motor (1) changes with time,
The FG signal (3) is frequency modulated (FM), so that the time length between adjacent leading edges of the velocity proportional signal (6) changes.
The cycle detector (7) outputs a control voltage corresponding to the amount of change in the time length.

That is, according to FIG. 4, the control output V _F (t) is expressed as V V at T _n <t ≦ T _{n + 1} (n = 0, ± 1, ± 2...).
_F (t) = V _F0 + ΔV _F (t) = V _F0 + Kv · ΔT _n = V _F0 + Kv ·
{(T _n −T _n−1 ) −Tc} (3) Here, V _F0 is the rotational speed of the motor is controlled output voltage when the constant Nmo. Kv is a period-voltage conversion constant, and here the polarity is negative. this is,
Since the polarity of ΔT is opposite to that of ΔNm, it is merely intended to simplify the description with Kv as a negative polarity, and this is the same in the embodiments of the present invention described later. In addition,
Here, the leading edge of the speed proportional signal (6) is used to detect the time length, but the same applies when the trailing edge is used.

Now, as is apparent from FIG.
The demodulation process of the FM signal itself, that is, the detection of the so-called "zero-crossing time" of the FM-modulated carrier, the change in the period of the carrier is obtained, and the conversion to a voltage restores the original modulation signal. Therefore, it is easily imagined that the higher the modulation frequency, the larger the phase delay.

In fact, in equation (2), ΔNm (t) is a single sine wave,
That is, ΔNm (t) = ΔNmocos (2πfmt + θm) (4) where, fm: rotational speed fluctuation frequency θm: initial phase ΔNmo: rotational speed fluctuation amplitude (peak / zero value), and FG signal, ie, carrier wave , Vc (t) = sin (2πfct) (5) where fm, θm, ΔNmo are variously changed, the demodulated output at that time is subjected to Fourier series expansion to extract a fundamental wave component, and the phase delay θv is calculated. When I look up, It becomes clear that θv is proportional to fm and inversely proportional to fc.

Here, the expression “approximately equal” in the equation (6) means that this speed detection method detects not the frequency itself but the reciprocal of the frequency, that is, a change in the period, and is proportional to the change amount. This is because, because the voltage is output, a slight error occurs when the variation rate (ΔNmo / Nmo) is large. However, estimates show that the volatility peaks
Even if it is set to a value of 10% at zero, which is so large that it is hardly applicable in an actual system, the error of θv is 1
Less than%. Note that this phase delay has also been confirmed by experiments using an actual motor control system.

FIG. 5 shows that in equation (4), And ΔVm (t) and ΔV _F (t). Here, the number in parentheses indicates the detection time. In this case, the phase delay θv is obtained from the equation (6). However, this can be easily confirmed from the waveform of FIG.

By the way, it is immediately apparent from such a calculation that if the time length of a half cycle of the FG signal (3) is detected and converted to a voltage, the phase delay θv becomes half of the equation (6). It is to become. This is because this is equivalent to the case where the FG frequency is doubled in the demodulation process described above.

However, in this case, unlike the case where one cycle is detected, if the FG signal (3) is distorted or an offset occurs in the waveform shaper (5) as shown in FIG.
Even if the rotation speed does not fluctuate, the output (b, c in FIG. 6) of the speed detector (5) generates ripples and also changes the DC component, so that the rotation increases uneven rotation due to ripples,
A deviation in the set speed will occur.

Also, since the frequency of the fundamental component of the ripple is the FG frequency, if a filter is added to avoid an increase in rotation unevenness, the time constant must be sufficiently large with respect to the ripple frequency. As a result, there are many drawbacks, such as the above-described effect of improving the phase delay due to the speed detection is canceled out, and further measures are required.

Therefore, in an actual speed control system, the method of detecting speed from a half cycle of the FG signal (3) has little merit in terms of performance and cost and is hardly used.

On the other hand, in the case of the method of detecting one cycle, as is clear from FIG. 6, even if an offset occurs in the waveform shaper (5), no ripple occurs and no fluctuation of the DC component occurs. However, even with such a one-cycle detection method,
As shown in FIG. 5, when there is a speed fluctuation, a ripple of the FG frequency occurs. Naturally, the magnitude is larger than the half-period detection method and the ripple frequency is lower. , The time constant of the subsequent filter (9) must be set large. Therefore, the performance of the control system is greatly restricted by the synergistic effect of the aforementioned θv and the phase delay due to the time constant element of the filter (9).

As described above, in the conventional speed detection, the method of detecting one cycle of the FG signal is generally used.
If the FG frequency cannot be set to the desired height due to system limitations, it was necessary to reduce the specifications in preparation for imperfect performance.

On the other hand, as described above, the applicant of the present invention has found that even if the FG frequency cannot be set to a sufficient height in light of the performance standard based on the assumption of the conventional system, the deterioration of the performance is suppressed. We have proposed a speed control device for a rotating body that can be reduced, in other words, can achieve higher performance than the conventional system even at the same FG frequency (Japanese Patent Publication No.
19712).

 Hereinafter, this proposal will be described with reference to FIG.

In FIG. 7, (1) is a motor, (2) is FG,
(3) is an FG signal, (4) is a speed detector, (5) is a speed proportional signal having a leading edge and a trailing edge from the FG signal (3) (6)
Waveform shaper to create (7a) is a speed proportional signal (6)
The first period detector (7b) which detects the time length or period between adjacent leading edges of the speed proportional signal (6) generates a control output (8a) according to the time length or period. Detects the time length, that is, the period, and outputs the corresponding control output (8b)
(11) alternately selects the output (8a) of the first cycle detector (7a) and the output (8b) of the second cycle detector (7b) Output selector to output
(8c) is the output of the output selector (11), that is, the output of the speed detector (4), (9) is a filter for the purpose of smoothing the output (8c) or compensating for the phase of the control system, and (10) is It is a motor drive circuit.

In the above configuration, similarly to the above-described conventional example,
Consider a case where the rotation speed fluctuates with time as in equation (2). The operation of the speed detector (4) at this time is described in the eighth.
Shown in the figure.

When the rotation speed of the motor (1) changes with time,
The FG signal (3) is frequency-modulated. Therefore, the time length between the adjacent leading edges and the time length between the adjacent trailing edges of the waveform-shaped speed proportional signal (6) change. The first cycle detector (7a) outputs a control output in response to a change in time length between adjacent leading edges, and the second cycle detector (7b) outputs a control output in response to a change in time length between adjacent trailing edges. (8a) and (8b) are output. The first and second cycle detectors (7a) and (7b) constitute the same detection scheme as the above-described conventional one-cycle detection scheme.

Therefore, the control output (8a) is V _F1 and the control output (8b) is V _F2
From FIG. 8, it can be seen from FIG. 8 that at T _2k <t ≦ T _{2k + 2} (k = 0, ± 1, ± 2,...), V _F1 (t) = V _F0 + ΔV _F1 (t) = V _F0 + Kv · ΔT _2k = V _F0 +
Kv {(T _2k −T _2k−2 ) −Tc} (9) where T _{2k + 1} <t ≦ T _{2k + 3} (k = 0, ± 1, ± 2,...) V _F2 (t) = V _F0 + ΔV _F2 (t) = V _F0 + Kv · ΔT _{2k + 1} = V _F0
+ Kv {(T _{2k + 1} −T _2k-1 ) −Tc} (10)

Now, the output selector (11) is a first period detector (7a)
From the time T _2k when the output (8a) of the second cycle detector changes to the time T _{2k + 1} when the output (8b) of the second cycle detector (7b) changes.
From the time T _{2k + 1 at} which the output (8a) of the period detector (7a) changes and the output (8b) of the second period detector (7b) changes.
_{T2k + 2 at which} the output (8a) of the period detector (7a) changes
Until then, the output (8b) of the second cycle detector (7b) is selected as the output (8c) of the speed detector (4). Thus, put the output of the speed detector (4) to (8c) and V _F, VF
(T) = V _F1 (t) (T _2k <t ≦ T _{2k + 1} ) V _F2 (t) (T
_{2k + 1} <t ≦ T _{2k + 2} ) (k = 0, ± 1, ± 2,...) (11)

Here, similarly to the conventional example, fm,
θm and ΔNmo are variously changed, and the demodulated output V _{F at} that time is changed.
Is Fourier series expanded to extract the fundamental wave component, and the phase delay θ _V is examined. It became clear that it becomes. The approximate codes in the above equation are for the same reason as in the conventional example. From this, it can be seen that the speed detector (4) in FIG. 7 reduces the phase delay by about 25% as compared with the conventional one-cycle detection system.

FIG. 9 shows ΔNm (t) and ΔV _F (t) at the set values shown in equation (7), similarly to the conventional example. The number in parentheses indicates the detection time. In this case, the phase delay θ _V is given by the following equation (12). Becomes

As is clear from FIG. 9, the ripple is reduced and the ripple frequency is doubled, and in this respect, it has the advantage of the half-period detection described above. Moreover, since the time constant of the subsequent filter (9) can be reduced by increasing the ripple frequency, it goes without saying that the phase delay of the control loop is synergistically reduced. Furthermore, according to this method, the detection of the time length is the same as the conventional one-period detection, so that the control is performed by the defect in the half-period detection, namely, the distortion of the FG signal (3) and the offset of the waveform shaper (5). Problems such as generation of ripples in the output and deviation of the DC potential do not occur.

[Problem to be Solved by the Invention] As described above, the system proposed by the present applicant has many excellent features as compared with the conventional system, but requires two period detectors due to its configuration. Therefore, if the circuit scale becomes relatively large, and if there is a characteristic difference between the two period detectors, there will be a difference between the respective detection outputs. There were two problems that appeared.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a speed detector which can be constituted by one half-period detector.

[Means for Solving the Problems] A speed control device for a rotating body according to the present invention sequentially detects half periods of a rotation speed proportional signal, and obtains a half cycle detection output of a level corresponding to the length of the half period. Means for transferring the detected output with a half-cycle delay, and adding means for adding the detected output and the transfer output from the transferring means.

[Operation] The speed detector according to the present invention sequentially detects the half cycle of the rotational speed proportional signal by the half cycle detecting means, delays the detected output by a half cycle by the transfer means, and outputs the delayed output.
The control output is obtained by adding the detection output and the delay output.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the same members as those shown in FIGS. 3 and 7 are denoted by the same reference numerals and the description thereof will be omitted.

In FIG. 1, (7c) is a half-period detector for detecting a half-period time length of the speed proportional signal (6) and obtaining a detection output (8d) corresponding thereto, and (12) is a time lapse of a subsequent half-period. A transmitter that transfers the detection output in synchronization with the edge of the incoming speed proportional signal and obtains the transfer output (8e). (13) Controls by adding the detection output (8d) and the transfer output (8e). This is an adder for obtaining an output, that is, a speed detector output (8f).

In the above configuration, as in the conventional example, as in equation (2),
Consider the case where the rotation speed varies with time. The operation of the speed detector (4) at this time is shown in FIG.

When the rotation speed of the motor (1) changes with time,
The FG signal (3) is frequency-modulated. Therefore, the time length of the adjacent leading edge and trailing edge of the waveform-shaped speed proportional signal, that is, the time length of a half cycle changes. The half cycle detector (7c) outputs a detection output (8d) corresponding to the time length of this half cycle. The transfer unit (12) transfers the detection output (8d) immediately after the next half cycle has elapsed to obtain a transfer output (8e).

Therefore, the detection output (8d) is V _F3 and the transfer output (8e) is V _F4
From FIG. 2, it can be seen that T _j <t ≦ T _{j + 1} (j = 0, ± 1, ± 2,...) It is expressed as Here T _j, as is clear from FIG. 2 and FIG. 8, the rotational speed Nm and the FG signal (3) is understood to be the same as T _2k given the same as the conventional example. The V _'F0 is the detection output when the rotational speed of the motor is constant in Nmo. Kv is set the same as in the conventional example.

On the other hand, the output (8e) of the transfer unit (12) is T _j <t ≦ T _{j + 1} (j = 0, ± 1, ± 2,...) It is expressed as

Now, the adder (13) outputs the detection output (8d) and the transfer output (8
e) is added to the control output, that is, the speed detector output (8f)
, T _j <t ≦ T _{j + 1} (j = 0, ± 1, ± 2,...) Becomes

As described above, since T _j = T _2k and T _j-2 = T _2k-2 , when T _j <t ≦ T _{j + 1} (j = 0, ± 1, ± 2,...), V ′ _F (T) = _2V'F0 + Kv {( _T2k - _T2k-2 ) -Tc} = V
_F1 (t) (17), which is consistent with the equations (9) and (11). But 2
V ′ _F0 = V _F0 .

Similarly, when T _{j + 1} <t ≦ T _{j + 2} (j = 0, ± 1, ± 2,...), V ′ _F (t) = 2V ′ _F0 + Kv ｛(T _{j + 1} −T _{j -1} ) -Tc｝ = V _F2 (t) (18), which is consistent with the equations (10) and (11).

In Equations (17) and (18), _V'F0 is a set value when there is no speed fluctuation. It means that the configuration shown in FIG. 7 and the configuration shown in FIG. 1 have completely equivalent performance. It becomes clear.

Therefore, the various characteristics of the speed detector according to the present invention, that is, the effects such as the reduction of the phase lag, the improvement of the ripple, and the fact that the DC potential does not change, are all equivalent to the invention previously proposed by the present applicant. Was proved. In addition, since one half-period detector can be realized, the circuit can be simplified, and the cost of the apparatus can be reduced.

Further, the configuration proposed by the applicant of the present invention has a problem that a ripple of the fundamental frequency fc is generated in the output when there is a characteristic difference between the two period detectors. However, according to the configuration of the present invention,
Since there is only one half-period detector, such a problem does not occur, and an extremely accurate device can be realized.

The configuration including the transfer unit (12) and the adder (13) is very similar to a transversal type non-recursive filter. In fact, if the speed fluctuation is reduced to infinity, the transfer interval asymptotically approaches Tc / 2, and in the extreme, the delay is Tc / 2 and the coefficient is 1
It can be easily understood that the transversal filter becomes a transversal filter.

In the above embodiment, the waveform shaper (5) is provided at the first stage of the speed detector (4). However, if the FG signal (3) has a waveform like the speed proportional signal (6), If the waveform has a trailing edge, the waveform shaper (5) can be omitted.

Further, as a method of detecting a half cycle, the conversion operation is achieved by a method of using charging and discharging of a CR circuit generally used in the related art, or a method of counting the length of a cycle with a clock signal obtained separately. Any means may be used.

Although the detection output (8d) is shown in the sample-and-hold type, it may be a count value (count value) obtained by counting the length of a half cycle with a clock signal as described above. (12) transfers this count value and outputs it (8
It is clear that e) should be used. Of course, the adder (13) may also perform the operation of adding these two count values.

Although the output (8f) of the speed detector (4) is shown in a sample-and-hold type, the same effect can be obtained by a so-called pulse width modulation (PWM) system in which the duty of the output is changed according to a change in the period. Obviously,

Further, in the above embodiment, the rotating body is driven directly, but it is needless to say that the same effect can be obtained by another driving method such as belt driving.

[Effects of the Invention] As described above, according to the present invention, the time length between adjacent edges of a rotational speed proportional signal, that is, a half cycle is detected, and this is transferred at a timing of every half cycle, and the detection output is output. And the control output is obtained by adding the above, so that the same effect as the method proposed by the applicant of the present invention can be obtained, and the apparatus can be inexpensive and a high-precision one can be obtained. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a speed control device for a rotating body according to the present invention, FIG. 2 is a timing chart for explaining the operation of a speed detector in FIG. 1, and FIG. FIG. 4 is a timing chart for explaining the operation of the speed detector in FIG. 3, and FIG.
FIG. 6 is a control output waveform diagram calculated using specific numerical values based on the speed detector shown in FIG. 6, FIG. 6 is a waveform diagram showing the influence of offset in a method for detecting a half-circulator, and FIG. FIG. 8 is a block diagram showing an embodiment of the invention proposed in FIG. 8, FIG. 8 is a timing chart for explaining the operation of the speed detector in FIG. 7, and FIG. 9 is a concrete diagram based on the speed detector in FIG. FIG. 9 is a control output waveform diagram calculated using numerical values. In the figure, (1) is a motor, (2) is a frequency generator,
(4) is a speed detector, (7c) is a half cycle detector, (12) is a transmitter, (13) is an adder, and (10) is a motor drive circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A speed detecting means for generating a control output according to a rotation speed proportional signal having a frequency proportional to a rotation speed of the rotating body; a driving means for driving the rotating body in accordance with an output of the speed detecting means; A speed control device for a rotating body, comprising: a half-cycle detection unit that sequentially detects half-cycles of the rotation speed proportional signal and obtains a detection output at a level corresponding to the length of the half-cycle. And a transfer unit for transferring the detection output with a half-cycle delay, and an adding unit for adding the detection output and the transfer output from the transfer unit.