JP2725033B2 - Quantum wire transistor - Google Patents
Quantum wire transistorInfo
- Publication number
- JP2725033B2 JP2725033B2 JP27573488A JP27573488A JP2725033B2 JP 2725033 B2 JP2725033 B2 JP 2725033B2 JP 27573488 A JP27573488 A JP 27573488A JP 27573488 A JP27573488 A JP 27573488A JP 2725033 B2 JP2725033 B2 JP 2725033B2
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- Prior art keywords
- doped
- layer
- quantum wire
- semiconductor layer
- transistor
- Prior art date
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- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 28
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 18
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000037230 mobility Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 230000005476 size effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、超高速の一次元電子トランジスタ、或いは
高変換効率の非線形素子等に利用される量子細線トラン
ジスタに関し、特に一次元量子細線素子の構造に特徴を
有する量子細線トランジスタに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrahigh-speed one-dimensional electron transistor or a quantum wire transistor used for a non-linear element with high conversion efficiency, and more particularly to a one-dimensional quantum wire element. The present invention relates to a quantum wire transistor having a structure.
材料としてAlGaAs/GaAsを例にとって、従来提案され
ている類似のトランジスタの構造を第５図に示す。即ち
第５図は、従来例としての電子干渉トランジスタの模式
的断面構造図であり、AlGaAs/GaAsの多層膜に三つの電
極ソースS,ゲートG,ドレインＤをつけた素子構造を有す
る。（例えば、文献1:S.Datta,etal,Physical Review L
etters,Vol.55,No.21,pp.2344−2347,1985.文献2:S.Dat
ta.Extended Abstract of the 20th Conference on Sol
id State Devices and Meterials,Tokyo.1988 pp491−4
94）。上下二つのGaAs層を流れる電子の干渉を利用して
素子化を図る提案である。チャネル1,2の内、片側のチ
ャンネルのみに電圧を加え、電子の波数を変えることに
より干渉条件を変え、ソースＳ、ドレインＤ間の電流を
制御する素子である。FIG. 5 shows a structure of a similar transistor which has been conventionally proposed, using AlGaAs / GaAs as an example. That is, FIG. 5 is a schematic cross-sectional structure diagram of an electron interference transistor as a conventional example, and has an element structure in which an AlGaAs / GaAs multilayer film is provided with three electrode sources S, a gate G, and a drain D. (For example, Reference 1: S. Datta, et al, Physical Review L
etters, Vol. 55, No. 21, pp. 2344-2347, 1985.Reference 2: S. Dat
ta.Extended Abstract of the 20th Conference on Sol
id State Devices and Meterials, Tokyo. 1988 pp491-4
94). This is a proposal to make a device by using the interference of electrons flowing in the upper and lower GaAs layers. This element controls the current between the source S and the drain D by applying a voltage to only one of the channels 1 and 2 and changing the wave number of electrons to change the interference condition.
上記で説明した従来例としての電子干渉トランジスタ
には、次のような問題点がある。その第１点は、電子の
干渉を利用するため、素子寸法は電子の干渉長（位相緩
和長Ｌφで表わされる）より小さくなければならないと
いう点である。Ｌφは極低温（4.2K）においても、せい
ぜい１ミクロンと小さいため素子寸法はサブミクロンに
なる。第２点は、電子の干渉を利用しているため波数が
一定値を持ち波数分散が小さくなければならない（コヒ
レントな波）、という点である。従って、フェルミ面上
の電子のみが動く極低温でなければ動作しない。The conventional electron interference transistor described above has the following problems. The first point is that in order to utilize the interference of electrons, the element size must be smaller than the interference length of electrons (expressed by the phase relaxation length Lφ). Even at a very low temperature (4.2K), Lφ is as small as 1 micron at most, so that the element size becomes submicron. The second point is that since the interference of electrons is used, the wave number must have a constant value and the wave number dispersion must be small (coherent wave). Therefore, unless the electrons on the Fermi surface move only at a very low temperature, they do not operate.
本発明は上記の問題点を解決し、動作温度、素子寸法
に厳しい制限がなく、超高速の一次元電子トランジス
タ、或いは高変換効率の非原形素子等に利用される量子
細線トランジスタを提供することを目的とする。The present invention solves the above problems, and provides an ultra-high-speed one-dimensional electron transistor or a quantum wire transistor used for a non-original device with high conversion efficiency without strict restrictions on the operating temperature and device dimensions. With the goal.
本発明の構成は以下に示す通りである。即ち、（00
1）化合物半導体基板（１）面上に絶縁膜（９）を堆積
した前記化合物半導体基板（１）面に〔110〕方向のス
トライプ状に形成した開口部を備え、 前記開口部を形成した化合物半導体基板（１）上に順
次成長させ台形状に形成した少なくとも二種類以上の組
成を有する複数のノンドープ半導体層からなるチャネル
層（3,10）を前記チャネル層（3,10）よりもバンドギャ
ップエネルギの大きいノンドープ半導体層（2,7,8）で
挟んだ半導体層構造と、 前記台形状に形成した半導体層構造の側面に成長させ
た50nm以下の厚さの前記チャネル層（3,10）よりもバン
ドギャップエネルギの大きいノンドープ半導体層からな
るスペーサ層（４）と、 前記台形状に形成した半導体層構造の側面に引き続き
成長させた高濃度の不純物濃度の半導体層（５）とを備
え、かつ 前記台形状に形成した半導体層構造の前記高濃度の不
純物濃度の半導体層（５）上に、ストライプ方向に順に
ソース、ゲート、ドレインの三つの電極を設けた構造を
有してなる ことを特徴とする量子細線トランジスタとしての構成を
有する。The configuration of the present invention is as described below. That is, (00
1) A compound having an opening formed in the form of a stripe in the [110] direction on the surface of the compound semiconductor substrate (1) in which an insulating film (9) is deposited on the surface of the compound semiconductor substrate (1); A channel layer (3, 10) composed of a plurality of non-doped semiconductor layers having at least two or more compositions and sequentially grown on the semiconductor substrate (1) and formed in a trapezoidal shape has a band gap larger than that of the channel layer (3, 10). A semiconductor layer structure sandwiched between non-doped semiconductor layers (2, 7, 8) having high energy; and the channel layer (3, 10) having a thickness of 50 nm or less grown on a side surface of the trapezoidal semiconductor layer structure. A spacer layer (4) made of a non-doped semiconductor layer having a larger band gap energy than that of the semiconductor layer (5) having a high impurity concentration continuously grown on the side surface of the trapezoidal semiconductor layer structure; And a structure in which three electrodes of a source, a gate, and a drain are sequentially provided in the stripe direction on the high-concentration semiconductor layer (5) of the trapezoidal semiconductor layer structure. It has a configuration as a characteristic quantum wire transistor.
本発明の量子細線トランジスタは二つのチャネルを有
する３端子素子として、前記の電子干渉トランジスタと
は原理的に異なる、トンネル結合形の新しい動作原理に
基づく素子であることから、電子の干渉を利用した電子
干渉トランジスタと違い温度、素子寸法に厳しい制限は
ない。The quantum wire transistor of the present invention is a three-terminal device having two channels, which is a device based on a new operation principle of a tunnel coupling type, which is fundamentally different from the above-mentioned electron interference transistor. Unlike electron interference transistors, there are no strict restrictions on temperature and device dimensions.
本発明の量子細線トランジスタは、一次元電子構造に
おいて電子の状態密度が発散する特徴を利用している。
移動度の異なる近接した２本の量子細線間の電子分布
が、ゲート電圧（即ちフェルミエネルギー）のわずかな
違いにより大きく変化して、コンダクタンスが変化す
る。The quantum wire transistor of the present invention utilizes the feature that the density of states of electrons diverges in a one-dimensional electronic structure.
The electron distribution between two adjacent quantum wires having different mobilities greatly changes due to a slight difference in gate voltage (ie, Fermi energy), and the conductance changes.
材料としてAlGaAs/GaAsを例にとって、本発明の量子
細線トランジスタの実施例を詳細に説明する。An embodiment of the quantum wire transistor according to the present invention will be described in detail, taking AlGaAs / GaAs as an example.
第１図は、本発明の実施例としての量子細線トランジ
スタの量子細線の基本構造を示す図である。量子細線は
第１図中の線で囲まれた界面の部分に存在する。第１図
において、１は半絶縁性GaAs基板、2,7,8はノンドープA
lGaAs成長層（Al 30％）、３はノンドープGaAs成長層チ
ャネル層、４はノンドープAlGaAsスペーサ層（Al 30
％）、５はSiドープAlGaAs成長層（Al 30％）、９は選
択成長マスク（SiO2）、10はノンドープAlGaAs（Al 5
％）チェネル層、100は一次元電子を示す。FIG. 1 is a diagram showing a basic structure of a quantum wire of a quantum wire transistor according to an embodiment of the present invention. The quantum wire exists at the interface portion surrounded by the line in FIG. In FIG. 1, 1 is a semi-insulating GaAs substrate, and 2, 7, and 8 are non-doped A
lGaAs growth layer (Al 30%), 3 is a non-doped GaAs growth layer channel layer, 4 is a non-doped AlGaAs spacer layer (Al 30
%, 5 is a Si-doped AlGaAs growth layer (Al 30%), 9 is a selective growth mask (SiO 2 ), 10 is non-doped AlGaAs (Al 5
%) Channel layer, 100 indicates one-dimensional electrons.
第２図（ａ）〜（ｃ）は、本発明の実施例としての量
子細線トランジスタの要部作製方法を示す製造工程図で
ある。以下順次説明する。まず、（001）面の半絶縁性G
aAs基板１上に９の選択成長マスクとしてSiO2をスパッ
タ法かCVD法で堆積させ、〔110〕方向に長いストライプ
状の開口部を作る（第２図（ａ））。この半絶縁性GaAs
基板１上に有機金属気相成長法を使って、650℃の成長
温度で７のノンドープAlGaAs成長層（本実施例ではAl 3
0％）を厚さ100nm成長させた後、３のノンドープGaAs成
長層チャネル層、バリア層としての２のノンドープAlGa
As成長層（Al 30％）、10のノンドープAlGaAs成長層（A
l 5％）チャネル層を順次6nm,5nm,10nmの厚さで成長さ
せて多層構造を作製し、最後に８のノンドープAlGaAs成
長層（Al 30％）を100nm成長させる。この時、第２図
（ｂ）に示すように成長層は台形状になり、その台形の
側壁にはいっさい成長しない。次に、第２図（ｃ）に示
すように、800℃の成長温度でこの台形状の多層構造の
上に４のノンドープAlGaAs成長層（Al 30％）を10nm成
長させ、続いて５のSiドープAlGaAs成長層（Al 30％）
を成長させる。かかる構造によって台形の側面は有効に
変調ドープされるが、台形状多層膜の上面には厚さ100n
mのノンドープAlGaAs成長層（Al 30％）８が形成される
ため、上側界面に電子は存在しない。従って、台形側面
に２本の近接した一次元電子100が実現できる。本発明
の実施例では、高周波加熱の横型炉を用い、減圧下で成
長を行なった。原料としてトリメチルガリウム、トリメ
チルアルミニウム、アルシンを用いて、第２図（ａ）で
示した半絶縁性GaAs基板１上に選択成長させた（第２図
（ｃ））。第３図には、このようにして作製した、本発
明の実施例としての量子細線トランジスタの模式的構造
概要図を示す。斜め界面に一次元電子100が存在するこ
とは磁気抵抗の磁場方位依存性から確認している。2 (a) to 2 (c) are manufacturing process diagrams showing a method for manufacturing a main part of a quantum wire transistor as an example of the present invention. This will be described sequentially below. First, the semi-insulating G on the (001) plane
SiO 2 is deposited on the aAs substrate 1 as a 9 selective growth mask by sputtering or CVD to form a long striped opening in the [110] direction (FIG. 2 (a)). This semi-insulating GaAs
A non-doped AlGaAs growth layer (Al 3 in this embodiment) is formed on a substrate 1 at a growth temperature of 650 ° C. by using a metal organic chemical vapor deposition method.
0%) is grown to a thickness of 100 nm, 3 non-doped GaAs growth layers, a channel layer, and 2 non-doped AlGa as a barrier layer.
As growth layer (Al 30%), 10 non-doped AlGaAs growth layers (A
(5%) Channel layers are sequentially grown to a thickness of 6 nm, 5 nm, and 10 nm to form a multilayer structure, and finally, a non-doped AlGaAs growth layer of 8 (Al 30%) is grown to 100 nm. At this time, as shown in FIG. 2 (b), the growth layer has a trapezoidal shape, and does not grow on the trapezoidal sidewall at all. Next, as shown in FIG. 2 (c), a 4 nm non-doped AlGaAs growth layer (Al 30%) is grown to a thickness of 10 nm on the trapezoidal multilayer structure at a growth temperature of 800.degree. Doped AlGaAs growth layer (Al 30%)
Grow. With such a structure, the trapezoidal side surface is effectively modulated and doped, but the upper surface of the trapezoidal multilayer film has a thickness of 100 n.
Since an m-type non-doped AlGaAs growth layer (Al 30%) 8 is formed, no electrons exist at the upper interface. Therefore, two one-dimensional electrons 100 close to the trapezoidal side surface can be realized. In the examples of the present invention, the growth was performed under reduced pressure using a high frequency heating horizontal furnace. Using trimethylgallium, trimethylaluminum, and arsine as raw materials, selective growth was performed on the semi-insulating GaAs substrate 1 shown in FIG. 2A (FIG. 2C). FIG. 3 shows a schematic structural schematic diagram of a quantum wire transistor as an embodiment of the present invention manufactured as described above. The existence of the one-dimensional electron 100 at the oblique interface has been confirmed from the magnetic field direction dependence of the magnetoresistance.
第４図は本発明の量子細線トランジスタの量子細線の
（ａ）バンド構造と（ｂ）電子の状態密度の説明図を示
す。ノンドープGaAs成長層チャネル層３とノンドープAl
GaAs成長層（Al 5％）チェネル層10の２本の量子細線の
コンダクションバンドのエネルギー差は50meVである。G
aAs細線（幅6nm）では量子サイズ効果により基底サブバ
ンドの位置がコンダクションバンドから70meV上がり、
一方AlGaAs細線（幅10nm）では34meV上がる。従って、
両者のエネルギー差は14meVとなる。このエネルギー差
の値は線幅により任意に設計できる。また第４図（ｂ）
に示すように、一次元電子の状態密度はサブバンド端で
大きくなることから、ゲート電圧によりフェルミレベル
が上がり、一旦サブバンドを横切ると大部分の電子は上
のサブバンドに入り始める。GaAs細線の移動度は室温で
8,000cm2/Vs、4.2Kで1,000,000cm2/Vsである。AlGaAs層
は合金散乱により移動度が低く、室温で800cm2/Vs、4.2
Kで10,000cm2/Vsである。従って、ゲート電圧によって
フェルミレベルを変えることにより、トランスコンダク
タンスが大きく変わる。同様な効果は、３のノンドープ
GaAs成長層チェネル層、バリア層としての２のノンドー
プAlGaAs成長層（Al 30％）、10のノンドープAlGaAs層
（Al 5％）チェネル層の厚さがそれぞれ２−50nmの範囲
で観測された。またゲート電極を二つのチェネル層（3,
10）の上下の層（第４図（ａ）のノンドープAlGaAs層
（Al 30％）7,8）に付けた４端子素子では、外部から電
子を供給することなしに、二つのチャネル（3,10）間を
電子が移動するため、高速性が達成された。FIG. 4 shows (a) band structure and (b) electron density of states of a quantum wire of a quantum wire transistor of the present invention. Non-doped GaAs growth layer channel layer 3 and non-doped Al
The energy difference between the conduction bands of the two quantum wires in the GaAs growth layer (Al 5%) channel layer 10 is 50 meV. G
In the aAs thin line (6 nm width), the position of the base sub-band rises by 70 meV from the conduction band due to the quantum size effect.
On the other hand, it rises by 34 meV for AlGaAs thin wires (10 nm width). Therefore,
The energy difference between the two is 14meV. The value of this energy difference can be arbitrarily designed according to the line width. FIG. 4 (b)
As shown in (1), since the state density of one-dimensional electrons increases at the sub-band edge, the Fermi level rises due to the gate voltage, and once crossing the sub-band, most of the electrons begin to enter the upper sub-band. Mobility of GaAs wire at room temperature
Is a 1,000,000cm 2 / Vs in 8,000cm 2 /Vs,4.2K. The AlGaAs layer has a low mobility due to alloy scattering, 800 cm 2 / Vs at room temperature, 4.2
It is 10,000 cm 2 / Vs in K. Therefore, changing the Fermi level according to the gate voltage greatly changes the transconductance. A similar effect is the non-doped
The thicknesses of the GaAs growth layer channel layer, the two non-doped AlGaAs growth layers (Al 30%) as barrier layers, and the ten non-doped AlGaAs layer (Al 5%) channel layers were observed in the range of 2 to 50 nm. The gate electrode is connected to two channel layers (3,
In the four-terminal element attached to the upper and lower layers of (10) (non-doped AlGaAs layers (Al 30%) 7, 8 in FIG. 4 (a)), two channels (3, 10) Since electrons move between them, high speed was achieved.
上述の本発明の実施例は台形の側面にノンドープAlGa
Asスペーサ層（Al 30％）４に続いて、SiドープAlGaAs
成長層（Al 30％）５を形成した例について説明した
が、ノンドープAlGaAsスペーサ層、（Al 30％）４を成
長することなく、SiドープAlGaAs成長層（Al 30％）５
を直接台形の側面に形成した構造としてもよい。ノンド
ープAlGaAsスペーサ層（Al 30％）４を形成せず、先の
実施例と同じ工程で作製した量子細線構造においても、
先の実施例と同じ効果が確認された。The above-described embodiment of the present invention employs a non-doped AlGa
As spacer layer (Al 30%) 4 followed by Si-doped AlGaAs
Although the example in which the growth layer (Al 30%) 5 is formed has been described, the Si-doped AlGaAs growth layer (Al 30%) 5 is formed without growing the non-doped AlGaAs spacer layer (Al 30%) 4.
May be directly formed on the side surface of the trapezoid. Even in a quantum wire structure manufactured in the same process as the previous embodiment without forming the non-doped AlGaAs spacer layer (Al 30%) 4,
The same effect as in the previous example was confirmed.
なおノンドープAlGaAsスペーサ層（Al 30％）４の厚
さが50nm以上になると、SiドープAlGaAs成長層（Al 30
％）５からの変調ドーピング効果がなくなるため、ヘテ
ロ接合界面への一次元電子の蓄積効果はなくなる。When the thickness of the non-doped AlGaAs spacer layer (Al 30%) 4 becomes 50 nm or more, the Si-doped AlGaAs growth layer (Al 30
%), The effect of accumulating one-dimensional electrons at the heterojunction interface is lost.
本発明の実施例では、AlGaAs/GaAs系材料で説明した
が、本発明の量子細線トランジスタはGaInP/GaAs,GaInA
s/InP等のIII−Ｖ族半導体及びその混晶系、ZnSe/GaAs
等のII−VI族半導体とその混晶系材料でも実現できる。Although the embodiments of the present invention have been described with reference to AlGaAs / GaAs-based materials, the quantum wire transistor of the present invention is GaInP / GaAs, GaInA.
III-V group semiconductors such as s / InP and mixed crystal systems, ZnSe / GaAs
And the like, and a mixed crystal material thereof.
以上説明したように、本発明の量子細線トランジスタ
は外部電位（ゲート電圧）によって主に電子の空間分布
を変えるものであるから、動作温度、素子寸法に大きな
制限はない。本発明の量子細線トランジスタを用いるこ
とにより、従来のプレーナ型FETと比較して高いトラン
スコンダクタンスをもつ一次元FETが得られた。As described above, since the quantum wire transistor of the present invention mainly changes the spatial distribution of electrons depending on the external potential (gate voltage), there is no great limitation on the operating temperature and the element size. By using the quantum wire transistor of the present invention, a one-dimensional FET having higher transconductance than that of a conventional planar FET was obtained.
第１図は本発明の実施例としての量子細線トランジスタ
の量子細線の基本構造を示す図、 第２図（ａ）乃至（ｃ）は本発明の実施例としての量子
細線トランジスタの要部作製方法を示す製造工程図、 第３図は本発明の実施例としての量子細線トランジスタ
の模式的構造概要図、 第４図（ａ），（ｂ）は本発明の量子細線トランジスタ
の量子細線のバンド構造と電子の状態密度の説明図、 第５図は従来例としての電子干渉トランジスタの模式的
断面構造図である。 １…半絶縁性GaAs基板 2,7,8…ノンドープAlGaAs成長層（Al 30％） ３…ノンドープGaAs成長層チャネル層 ４…ノンドープAlGaAsスペーサ層（Al 30％） ５…SiドープAlGaAs成長層（Al 30％） ９…選択成長マスク（SiO2） 10…ノンドープAlGaAs（Al 5％）チャネル層 100…一次元電子FIG. 1 is a view showing a basic structure of a quantum wire of a quantum wire transistor according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (c) show a method of manufacturing a main part of the quantum wire transistor as an embodiment of the present invention. FIG. 3 is a schematic structural diagram of a quantum wire transistor as an embodiment of the present invention, and FIGS. 4 (a) and 4 (b) are band structures of the quantum wire of the quantum wire transistor of the present invention. And FIG. 5 is a schematic cross-sectional view of a conventional example of an electron interference transistor. DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate 2,7,8 ... Non-doped AlGaAs growth layer (Al 30%) 3 ... Non-doped GaAs growth layer channel layer 4 ... Non-doped AlGaAs spacer layer (Al 30%) 5 ... Si-doped AlGaAs growth layer (Al 9: Selective growth mask (SiO 2 ) 10: Non-doped AlGaAs (Al 5%) channel layer 100: One-dimensional electron
Claims (1)
堆積した前記化合物半導体基板面に〔110〕方向のスト
ライプ状に形成した開口部を備え、 前記開口部を形成した化合物半導体基板上に順次成長さ
せ台形状に形成した少なくとも二種類以上の組成を有す
る複数のノンドープ半導体層からなるチャネル層を前記
チャネル層よりもバンドギャップエネルギの大きいノン
ドープ半導体層で挟んだ半導体層構造と、 前記台形状に形成した半導体層構造の側面に成長させた
50nm以下の厚さの前記チャネル層よりもバンドギャップ
エネルギの大きいノンドープ半導体層からなるスペーサ
層と、 前記台形状に形成した半導体層構造の側面に引き続き成
長させた高濃度の不純物濃度の半導体層とを備え、かつ 前記台形状に形成した半導体層構造の前記高濃度の不純
物濃度の半導体層上に、ストライプ方向に順にソース、
ゲート、ドレインの三つの電極を設けた構造を有してな
る ことを特徴とする量子細線トランジスタ。An insulating film is deposited on a surface of a (001) compound semiconductor substrate. The compound semiconductor substrate has an opening formed in a stripe shape in a [110] direction on the surface of the compound semiconductor substrate. A semiconductor layer structure in which a channel layer composed of a plurality of non-doped semiconductor layers having at least two or more types of compositions and formed in a trapezoidal shape and sequentially grown is sandwiched between non-doped semiconductor layers having a band gap energy larger than that of the channel layer; Grown on the side of the semiconductor layer structure formed in the shape
A spacer layer comprising a non-doped semiconductor layer having a band gap energy larger than that of the channel layer having a thickness of 50 nm or less; and a semiconductor layer having a high impurity concentration continuously grown on the side surface of the trapezoidal semiconductor layer structure. And, on the high-concentration impurity concentration semiconductor layer of the semiconductor layer structure formed in the trapezoidal shape, the source in the stripe direction in order,
A quantum wire transistor having a structure in which three electrodes, a gate and a drain, are provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27573488A JP2725033B2 (en) | 1988-10-31 | 1988-10-31 | Quantum wire transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27573488A JP2725033B2 (en) | 1988-10-31 | 1988-10-31 | Quantum wire transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02122571A JPH02122571A (en) | 1990-05-10 |
| JP2725033B2 true JP2725033B2 (en) | 1998-03-09 |
Family
ID=17559644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27573488A Expired - Fee Related JP2725033B2 (en) | 1988-10-31 | 1988-10-31 | Quantum wire transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2725033B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244211A (en) * | 1993-02-12 | 1994-09-02 | Nec Corp | Semiconductor device |
| JP4528398B2 (en) * | 1999-12-27 | 2010-08-18 | 独立行政法人産業技術総合研究所 | Negative resistance field effect transistor |
-
1988
- 1988-10-31 JP JP27573488A patent/JP2725033B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02122571A (en) | 1990-05-10 |
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