JP2723885B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to security of EEPROM data in a microcomputer having a read-only memory (EEPROM) that can be electrically written and erased. The present invention relates to a suitable semiconductor integrated circuit. (EEPROM: Elextrically Erasable and Programmable Re
ad Only Memory) [Background of the Invention] Conventional microcomputers with built-in EEPROM are, for example, 19
In a microcomputer announced by Seeq at ISSCC '83 in 1983, EEPROM for security was assigned as a register.
Storing programs by operation from outside the semiconductor integrated circuit
There is known a method capable of executing security protection and cancellation of EEPROM. This method can be executed with simple operation, but it is not
There was no consideration to keep the OM data forever. [Object of the Invention] An object of the present invention is to provide a semiconductor integrated circuit such as a microcomputer having an EEPROM formed on the same semiconductor substrate.
Easy test of built-in EEPROM and EEPROM after test
In providing confidentiality. Another purpose is EE
An object of the present invention is to provide an extension of a PROM writing function. [Summary of the Invention] In order to achieve the above object, in the present invention, for ease of test and security protection, a pad and an input / output circuit for providing an address, data and control signal required for a test are provided on a semiconductor substrate. After the test is completed, a two-level test input / output cutoff circuit including an EEPROM element for inhibiting the test input / output circuit is provided. In addition, with respect to the extension of the writing function of the EEPROM, it is characterized in that a control register for controlling the EEPROM is provided. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a microcomputer according to an embodiment of the present invention. All circuits shown in FIG. 1 are integrated on the same semiconductor substrate 1. The CPU 2, the RAM 3, the ROM 4, and the EEPROM 5 are connected by a common bus 6 that transmits addresses, data, control signals, and the like. Data communication with the outside of the semiconductor integrated circuit is performed through an I / O circuit 7.
Also, a test circuit 8 for testing the EEPROM is added. At the time of the EEPROM test, only the EEPROM module 9 becomes operable, and an independent test separated from the CPU, RAM, and ROM can be performed. FIG. 2 shows the configuration of the EEPROM module 9. Memory matrix 10 containing 16384 bit EEPROM memory elements is 32
It has a configuration of bytes (256 bits) x 64 pages.
Each page is selected by the output of the X decoder 11, and each byte in the page is selected by the Y selector 12. That is, an arbitrary one byte (8 bits) is selected by a combination of the X decoder 11 and the Y selector 12. Each of the above-mentioned decoders is coupled to an address latch 13 for latching address information. An input to the address latch 13 is provided from outside the semiconductor integrated circuit through an address buffer 14 in a test mode, and is input to a microcontroller in other than the test mode. It is coupled to the address bus 15 of the computer and provided from the CPU. Reading and writing of data from the EEPROM matrix 10 in the test mode are performed by control signals ▲ ▼, ▲ ▼, ▲ applied from outside the semiconductor integrated circuit.
Perform by ▼. At this time, the data path is such that, for reading, the data of the memory matrix 10 is input to the sense amplifier 16 via the Y selector 12, and the detected and amplified data is supplied to the data bus 17 and the data buffer controlled in the output direction. The signal is output to the outside of the semiconductor integrated circuit through the signal 18. The data to be written to the EEPROM is latched by the data latch 19 via the data buffer 18 and the data bus 17 which are controlled in the input direction, and is written to the EEPROM memory according to the control timing generated by the EEPROM control circuit 20. The control signals 書 込 み, ▼, and ▼ are latched by the control latch 22 via the control buffer 21 at the time of writing, and the output thereof provides control information to the EEPROM control circuit 20. On the other hand, excluding the test mode, data exchange is performed directly with the CPU via the data bus 17 of the microcomputer, and control is also performed in synchronization with a control signal 23 generated by the CPU. As described above, in the test mode, writing / reading to / from the EEPROM directly from outside the semiconductor integrated circuit, that is,
The EEPROM test can be easily performed via the test port 24. Further, the EEPROM module 9 has the following configuration in order to prohibit external output of the EEPROM data after the test, that is, to realize a security function. EE that stores data
32 bytes for security separately from PROM10
Place the EEPROM25. The EEPROM 25 is selected by the output of the decoder 26, and one byte of the 32 bytes is selected by the Y selector 12. The information in the security EEPROM is read by a Y-selector 12, a sense amplifier 16, and a data bus 17 by a read operation.
Is input to the security circuit 27, the security circuit 27 decodes the data written in the EEPROM 25, and when the information requiring security is written, the security circuit 27 outputs a security lock signal, The data input / output buffer 18 in the test mode is disabled. That is, direct data input / output from external terminals is prohibited. Another feature of this EEPROM module is the EEPROM control register (EC
R) 28. Next, the details of the CER 28 and the mode of the EEPROM will be described with reference to FIGS. FIG. 3 is a diagram showing the configuration of the EEPROM control register (ECR) 28. The ECR is a 3-bit register arranged in the address space of the microcomputer, and can be directly accessed from the CPU via the data bus. Each bit has the following function. EI: Erase Inhibit An EEPROM control flag assigned to bit 0 (b0) of the ECR, which gives information to the EEPROM control circuit 20 to inhibit the EEPROM erase sequence. (Prohibited when "1")
This flag is readable / writable from the CPU. WI: Write Inhibit This is an EEPROM control flag assigned to bit 1 (b1) of the ECR, and gives information to the EEPROM control circuit 20 to inhibit the write sequence to the EEPROM. (Prohibited when "1") This flag can be read / written by the CPU. ▲ ▼: EEPROM module busy Flag assigned to bit (b7) of ECR.
Indicates that the ROM module is executing an erase or write sequence. When ▲ ▼ = “0”, read / write to EEPROM module is invalid. The EEPROM control circuit 20 performs timing control by a self-oscillator irrespective of the microcomputer clock. To synchronize with the basic clock S of the microcomputer, the EEPROM control circuit 20
▼ Connect to register. When ▲ ▼ = “0”
A write inhibit signal 30 is given to the WI and EI registers to inhibit writing to WI and EI. Next, the write sequence of the EEPROM will be described with reference to FIG. The start of the write sequence is performed by the write control signals ▲ ▼ (or ▲ ▼), ▲ ▼ described in FIG.
(Or ▲ ▼), ▲ ▼ (or ▲ ▼)
The writing sequence is started by setting ▼▼ to “0” under ▲ = “0” and ▲ = “1”. (A) One word (256 bits) of data of the EEPROM selected by the X decoder 11 or the decoder 26 shown in FIG. 2 is saved in the column latch 31 shown in FIG. (B) In order to notify the outside that the EEPROM module has entered the write sequence, the EEPROM control register ECR
Set the flag to "0". (C) Write data input from the data bus is transferred to the column latch 31 selected by the Y selector 12 via the data latch 19 shown in FIG. This action first ▲
Any number of bytes can be input within 500 μs after ▼ is asserted, so up to 32 bytes of data can be input to the column latch within 500 μs in synchronization with ▲ ▼, and 1 to 32 bytes Can be simultaneously written in one write cycle. Also in this case, the data is transferred to the column latch 31 (1 byte out of 32 bytes) selected by the Y selector, and is temporarily latched as write data. (D) EI flag of EEPROM control register ECR (bit 0)
When EI = 0, the erase sequence (E) is executed. Erase is the page selected by the X decoder (32 bytes)
Performed in units. Erasing is to set the data of the EEPROM memory element to "1". Therefore, the entire page (32 bytes) of the EEPROM after erasing becomes "1" data. Meanwhile, EC
When the EI of R is EI = 1, the process proceeds to the next sequence without controlling the erasure. (F) WI flag of EEPROM control register ECR (bit 1)
When WI = 0, the contents of the column latch 31 are written to the page selected in (A) (G). Writing is to hold the state of the EEPROM element before writing "1" data, and to change the state of the EEPROM element to "0" data to write "0" data. When WI = "1", the process proceeds to the next sequence without controlling writing. (H) The シ ー ケ ン ス flag of the ECR is set to “1”, and the write sequence ends. The security of the EEPROM data will be described with reference to FIGS. Fig. 5 shows the principle of security.
Elements SE1 and SE2 (included in the security EEPROM of FIG. 2) is coupled to the circuit SA0 and SA1 detects amplify the respective data via an Y selector, the output d ₀ and d ₁ is input to the ENOR circuit Is done. Ie security
When the EEPROM SE1 and SE2 are selected by the select line SEL and the data output control signal DOC is asserted, SE0 and SE1
ENOR only when d ₀ = d ₁ depending on the state of outputs d ₀ and d ₁
Output becomes “1” level. On the other hand, the output of ENOR is input to the AND circuit 51. AND circuit
The other input to 51 is the output signal DOCd of the delay circuit 53 that delays only the rise of DOC that has SEL and DOC as inputs. The output of AND circuit 51 is coupled to set input S of set / reset flip-flop SRFF. The reset input R of the SRFF is coupled to the output of the power-on reset circuit 52 that generates a reset signal after the power is turned on, and the output Q of the SRFF always outputs the "0" level immediately after the power is turned on. This state is defined as security signal ▼ = “0”, and is assumed to be a security lock state. Next, the set timing of the flip-flop SRFF will be described with reference to FIG. Selection signal SEL is asserted, the data d ₀ and d ₁ of the further data output control signal DOC is in synchronism with the rising of the asserted DOC EEPROM (SE0 and SE1)
Is determined. Then in synchronization with the output DOCd of the delay circuit 53 of the DOC, if d ₀ = d ₁ if the output SS of the AND circuit is "1" level output Q of the SRFF becomes (actual Figure 7 SS) is "0 The level changes from “level” to “1” level (solid line in FIG. 7Q). In the case of d ₀ ≠ d ₁ , the “1” level is not output to the output SS of the AND circuit 51 regardless of how the SEL and DOC are controlled.
Does not become the "1" level. That is, the security lock is not released. FIG. 7 shows a detailed circuit diagram of the present embodiment. The embodiment of the principle described in FIG. 5 and FIG. 6 is a block 57 in FIG. 7, which is a set / reset flip-flop 61 which is always reset when the power is turned on, a delay circuit 53 for the output control signal DOC. Having. The security EEPROM (SE0, SE1) described in FIG. 5 is expanded to 4 bits (SE0 to S0) to increase the reliability of the security function.
E3), all “1”, all “0” for judging match of d _{0 to} d ₃
A determination circuit 54, and a power supply voltage VCC of, for example, 3 to 6 V
In this configuration, a detection circuit 55 detects the power supply for detecting that the power supply is within a certain range, and a power-on detection circuit 56 configured to generate a reset pulse only for a predetermined period when the power is turned on. The condition that the flip-flop 61 is set by the above configuration is that d ₀ to d ₃ are all “1” or all “0”. The power supply voltage must be within the range of 3 to 6V. A pulse whose DOC pulse width is longer than the delay time determined by the delay circuit 53. And is set and held only when the above conditions are simultaneously satisfied. The reset condition is when the power is turned on. When VCC deviates from 3 to 6V. When either of the conditions is satisfied. This embodiment constitutes another security circuit shown in the block in FIG. EEPROM matrix 10 and security EEPROM in FIG.
EEPROM element 70 and MOSFET 7 for isolation provided separately from OM25
The four sets of circuits consisting of a security bit composed of 1,72, a load transistor 73 paired with a security bit for reading the information, and an inverter 74 for amplifying the information, It is composed of a NAND circuit 75 as an input. The gate electrode of the EEPROM element 70 is connected to the write power supply VP via an input protection circuit 60 comprising an N ⁺ diffusion layer resistance on a P well and a diode. Further, the gate electrode 70 is connected to the MOSFET 76 for fixing to the ground potential when the VP is in the open state. Isolation MOSFET
The gate electrodes 71 and 72 are connected to the same wiring as the gate electrode of the EEPROM element 70 via the inverter 77 and the high voltage limit MOSFET 78. The threshold value _Vth of the EEPROM element as manufactured by the semiconductor manufacturing process is about -0.5 V (this is referred to as _VthL ). Therefore, when the VP electrode is opened or set to the ground potential, the EEPROM is in a normal state. At this time, the isolation _{MOSFETs 71 and 72} are on, and the state of _VthL can be detected by appropriately designing the load transistor 73 and the inverter 74. EEPR
_Set the threshold V _{th of the} OM element to a high level (this is set to V _thH )
In order to shift to, the potential of the well including the EEPROM element 70 is set to the ground level, and a voltage of about +150 is applied to VP for 1 to 10 ms.
It is done by adding between. V _{thH at} this time is, for example, about + 3V. The voltage applied to VP is the threshold voltage V of inverter 77
_{When th (INV)} is exceeded, the inverter is inverted, and the isolation transistors 71 and 72 are turned off. If VP is opened or the ground level is set while the threshold voltage of _VthH is 70, the EEPROM element 70
Is off, the isolation transistors 71 and 72 are on, and the load transistor 73 and the inverter 74 detect V _thH . The pair of 70, 71, 72, 73, 74 may be one or more pairs,
Further, only one of the separation transistors 71 and 72 may be used. The protection circuit 60 prevents the application of a positive high voltage equal to or higher than the write voltage to the gate of the EEPROM element 70 and the application of a negative voltage. As described above, the first security circuit 57 and the second security circuit 58 are provided, and the security function can be enhanced by taking the OR of each output. An embodiment for realizing the easiness of the EEPROM test and the security protection of the EEPROM after the test using the security circuit described above will be described with reference to FIG. EEPROM 100 is connected to C via data bus DB and address bus AB.
Combined with PU101. AB and DB are also coupled to an address report 102 and a data port 103 for providing an address and data from outside the semiconductor integrated circuit during an EEPROM test. EEPROM writing and reading are controlled by control signals CS and R
It is controlled by D and WR. The test mode is determined by the EEPROM test signal ET. When ET = "0", the CPU mode is set. Address input from the address port 102 and data input / output from the data port 103 are prohibited. CPU1
01 is output only from EEPROM10 via the address bus AB.
Given to 0. Data is also input to and output from the CPU 101 via the data bus DB. Control signal is external terminal ▲
Input from ▼, ▲ ▼, ▲ ▼ is prohibited, and control signals ▲ ▼, ▲ ▼, ▲ ▼ from the CPU are input. When ET = "1", the mode is the EEPROM test mode. In this case, the output from the CPU to the data bus DB and the address bus AB is prohibited, and the input to the address bus AB is external to the semiconductor integrated circuit via the address port 102. From address A _{0 to} A ₁₁
EEP, and が, ▼, and ▼ from the outside of the semiconductor integrated circuit. The interface between the data bus DB and the outside of the semi-conductor circuit is performed through the data port 103. In order for the data port to be operable, the output ▲ ▼ of the security circuit 104 described in FIG. Only in the case of. In this embodiment, the microcomputer reset terminal ▲
▼ is switched by the EEPROM test signal ET, and is used to control all-bit erase and all-bit write in the EEPROM test mode. At this time, the CPU is forcibly reset (RESET =
0). When ET = “1” and ▲ ▼ = “1”, all bit mode is selected. ▲ ▼ = “1” when ▲
When all “1” s are given to D _{0 to} D ₇ under ▼ = “0” and ▲ ▼ = “1” and ▲ ▼ = “0”, the all-bit erase sequence is started and the EEPROM data is All bits become "1". When all “0” s are given to D _{0 to} D ₇ under ▲ ▼ = “0” and ▲ ▼ = “1” and ▲ ▼ = “0”, the all bit write sequence is started and the EEPROM data is All bits become "0". If ▲ ▼ = “0”, ▲ ▼ = “0”, ▲
When ▼ = “0” under ▼ = “1”, the all-bit erase sequence is started, and the EEPROM data is all bits “1”.
become. The EEPROM mentioned here is the EEPROM explained in Fig. 2.
16384 bits of memory matrix 10 and security E
This is 256 bits (including SE0 to SE3) of the EPROM 20 and does not include the EEPROM element 70 shown in FIG. When all the bits are erased or all the bits are written, the data in the security EEPROM becomes all “0” or all “1”, and d ₀ to d ₃ explained in FIG. 8 are all “0” and all “1”. The security release condition is satisfied, and the EEPROM test can be performed from outside the semiconductor integrated circuit. Next, an operation procedure from the state where the semiconductor integrated circuit of this embodiment is manufactured and writing or erasing is not performed once to the EEPROM test and security for security protection will be described. 8 Under A ₀ of the EEPROM test signal ET = "1" shown in FIG.
Giving an address for selecting a security EEPROM (25 of FIG. 2) from _{~A 11, ▲ ▼ = "0} ", ▲ ▼ = "1" at ▲ ▼ = "0" to the eighth Figure ▲ ▼ is " 1 "and the data port 103 is enabled. It becomes “1” and the data port 103 is enabled. In this state, the EEPROM can be directly accessed from the external terminal, and the test can be performed. After the test, write data other than all “0” or all “1” to the security bits (SE _{0 to} SE ₃ ). It is not enabled, direct access from outside the semiconductor integrated circuit is prohibited, and the confidentiality of the EEPROM is maintained. To return to the state where the EEPROM test is possible, that is, to return to the above state, ET = "1" ▲ ▼ = "1", ▲ =
When ▲ = “0” under “0”, ▲ ▼ “1”, the security bit (25 in FIG. 2) is erased together with the erasure of the data in the memory matrix (10 in FIG. 2). Testing is possible after the operation. Applying a high voltage to VP in Fig. 8 and thresholding the EEPROM element 70
When V _{th is set} to a high level, it is impossible to return to the test mode forever. The mode and mode selection of the EEPROM will be described with reference to FIG. Here, the CM signal is an input signal from the outside of the semiconductor integrated circuit and used for the EEPROM test.
This is a control signal for determining whether to select an element or a page unit (corresponding to the signal in the EEPROM test mode in FIG. 8). Standby: At ＝= “H”, the EEPROM module is in standby. Read: Reads 1 byte of EEPROM according to the input address information. Write1: (A) (B) (C) of the sequence in FIG.
(E) Perform (G) (H). Write2: (A) (B) (C) of the sequence of FIG.
(G) Perform (H). Page Erage: (A) (B) (C) of the sequence of FIG.
(E) Execute (H). Erase / Write Inhibit: Sequence (A) (B) in FIG.
(C) Execute (H). If the EEPROM is read while Data Polling: ▼ = “0”, the inverted data of the most significant bit of the last written data is read. "0" is output to the lower 6 bits. SEEP Read: Security EE that stores security information
The PROM is selected by the address information, and the data is read. SEEP Write: The security EEPROM is selected based on the address information, and the security information is written. Chip Erase: EEPRO in data area and security area
Set all bits of M to “1”. Chip Write: EEPRO in data area and security area
Set all bits of M to “0”. In the EEPROM test mode, all of the above modes can be selected.
EEP Read / Write and Chip Erase / Write are prohibited. As described above, according to the present embodiment, the EEPROM test can be performed without using the CPU function of the microcomputer, and the efficiency of the semiconductor integrated circuit test can be improved. Direct EEPR
By prohibiting OM access and allowing access only from the CPU, the confidentiality of EEPROM data can be protected. Also, by providing a register to control the EEPROM,
It is possible to realize an extended operation mode of the OM, that is, a function of writing in units of pages in which erasing is prohibited, and a function of inhibiting erasing, erasing, and writing in units of pages. [Effects of the Invention] As described above, according to the present invention, in a semiconductor integrated circuit such as a microcomputer having a built-in EEPROM, a test of the built-in EEPROM can be easily performed, and after the test,
A semiconductor integrated circuit having a confidentiality protection function in which EEPROM data is not directly output to the outside of the semiconductor integrated circuit can be provided. Further, by enhancing the write function of the built-in EEPROM, there are effects such as improvement of microcomputer program efficiency and improvement of write protection.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram of a microcomputer, and FIG.
FIG. 3 is a configuration diagram of an EEPROM control register, FIG. 4 is a control sequence diagram of the EEPROM, FIG. 5 is a principle diagram of security, FIG. 6 is a timing diagram of FIG. 5, FIG. Is a security circuit diagram, FIG. 8 is an overall view of security, and FIG. 9 is an explanatory diagram of an EEPROM mode. 1: Semiconductor board, 2: CPU, 3: RAM, 4: ROM, 5: EEPROM, 6: Bus, 7: I / 0, 8: Test circuit, 9: EEPROM module, 10: EE
PROM memory matrix, 11: X decoder, 12: Y selector,
13: address latch, 14: address buffer, 15: address bus, 16: sense amplifier, 17: data bus, 18: data buffer, 19: data latch, 20: EEPROM control circuit, 21:
Control buffer, 22: Control latch, 23: Control signal generated by CPU, 24: Test port, 25: Security EEPROM, 2
6: Decoder, 27: Security circuit, 28: ECR, 29: Synchronous circuit, 30: Write inhibit signal, 31: Column latch, 50: ENOR
Circuit, 51: AND circuit, 52: Power-on reset circuit, 53: Delay circuit, 54: Judgment circuit, 55: Power supply voltage detection circuit, 56: Power-on detection circuit, 57, 58: Security circuit, 59: Security bit, 70: EEPROM, 71, 72: MOSFET for isolation, 73: Load transistor (MOSFET), 74: Inverter, 75: NAND circuit,
76: MOSFET, 77: Inverter, 78: MOSFET, 101: EEPROM, 1
01: CPU, 102: Address port, 103: Data port, 104:
Security circuit, AB: address bus, DB: data bus.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Yoshimune Hagiwara               1-280 Higashi Koigabo, Kokubunji-shi               Central Research Laboratory, Hitachi, Ltd. (72) Inventor Toshimasa Kihara               1450 Kosui Honcho, Kodaira City Hitachi, Ltd.               Inside the Musashi Factory (72) Inventor Kiyoshi Matsubara               1450 Kosui Honcho, Kodaira City Hitachi, Ltd.               Inside the Musashi Factory (72) Inventor Tadashi Yamaura               1450 Kosui Honcho, Kodaira City Hitachi, Ltd.               Inside the Musashi Factory                (56) References JP-A-59-77699 (JP, A)                 JP-A-58-208999 (JP, A)                 JP-A-59-140695 (JP, A)                 JP-A-59-135698 (JP, A)                 JP-A-58-208994 (JP, A)

Claims (1)

(57) [Claims] A CPU for performing data processing, a memory for storing data, and electrically writable and erasable; a common bus including at least a data bus, connected to the CPU and the memory; and disposed in an address space of the CPU. A semiconductor integrated circuit having a control register writable from the CPU via the data bus, and a control circuit for controlling writing and erasing to and from the memory based on the content of the control register, wherein the control register Wherein information indicating whether or not data writing to the memory is prohibited and information indicating whether or not data erasing of the memory is prohibited can be stored. 2. 2. The semiconductor integrated circuit according to claim 1, wherein said semiconductor integrated circuit is configured as a microcomputer. 3. 3. The semiconductor integrated circuit according to claim 1, wherein said memory is an EEPROM. 4. A CPU that performs data processing; a memory that stores data and is electrically writable and erasable in units of one word selected by a decoder; a column latch that holds the data in units of one word; and at least a data bus A common bus connected to the CPU and the memory, a control register writable from the CPU via the data bus, and a control circuit for controlling writing and erasing to and from the memory based on the contents of the control register. The control register stores information indicating whether to prohibit data writing to the memory and information indicating whether to prohibit data erasing of the memory.When a writing sequence starts, The data for one word selected by the decoder is saved in the column latch, and the write data is A semiconductor integrated circuit for writing data into at least a part of the column latch, erasing the one word according to the content of the control register, and then writing the content of the column latch without writing or erasing the content of the column latch.