JP2506420B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology (Fig. 10) Problems to be solved by the invention Means for solving the problem Action Example (1) First example of the present invention Embodiment (Figs. 1 to 8) (2) Second embodiment of the present invention (Fig. 9) Effect of the invention [Outline] Regarding a semiconductor memory device, a parity error output is promptly output after the output of the parity check circuit is determined. A parity check circuit for performing a parity check to determine whether or not there is an error in read data from a memory is provided for the purpose of providing a semiconductor memory device that can be confirmed and speed up the memory system. At least the output of the circuit is received by the open-drain MOS transistor, and the result of the parity check is extracted from the drain side of the MOS transistor to the outside. In the body the storage device, corresponding to a predetermined period of time the output is uncertain of the parity check circuit,
A signal adjusting means for prohibiting the output of the parity check circuit is provided, and the drain side of the MOS transistor is kept in a high impedance state until the output of the parity check circuit is determined by the signal adjusting means.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a parity check circuit.

In recent years, along with the demand for higher speed computer systems, it is required to check the output result of the semiconductor memory at high speed. Therefore, a parity check circuit is mounted on a semiconductor memory.

[Conventional technology]

As a conventional memory with a parity check circuit,
For example, there is one as shown in FIG. In the figure,
Address data AD0 to A when reading data from memory 1
When Dm is given, data OUT1 to OUTn appear on the output side, and the read data OUT1 to OUTn are taken into the parity check circuit 2 to check whether or not a parity error has occurred. IN1 to INn are input data. When there is a parity error, the output of the parity check circuit 2 becomes "H" level, which is the N-type MOS transistor 3
The MOS transistor 3 is turned on by being added to the gate of the parity error terminal and the parity error terminal (hereinafter, referred to as PE terminal) becomes "L" level. This L signal is used, for example, to set a parity error flag, whereby it is recognized that there is an error in the read data, and the CPU that uses the read data eliminates the data.

On the other hand, when the output data of the memory 1 is normal, the output of the parity check circuit 2 becomes "L" level, the MOS transistor 3 is turned off, and the PE terminal 4 is in a high impedance state. Through the power supply Vcc, the PE terminal 4 is charged up and the PE terminal 4 becomes "H" level. In FIG. 10, the left side portion of the PE terminal 4 in the figure is made into a chip as an internal configuration of one IC, and the pull-up resistor 5 is provided outside the IC. In practice, a plurality of semiconductor memories such as the memory 1 are often used. In this case, the parity error output of each memory is taken out by wired OR and connected to the pull-up resistor 5.

[Problems to be Solved by the Invention] However, in such a conventional memory with a parity check circuit, since there is an indeterminate period in the read data of the memory, the output of the parity check circuit also has an indeterminate period. However, there is a problem in that the parity error output that conveys the reliability of the data to the outside is affected by the delay and is displayed slowly, which impedes the speedup of the memory system.

That is, since the output of the parity check circuit is directly output to the open-drain MOS transistor, if there is an indetermination period in the output of the parity check circuit, the parity error output is also not immediately fixed, but there is a particular problem. The above MOS transistor is ON
When returning to OFF from and pulling up the PE terminal through an external pull-up resistor, a large current cannot be passed to the internal circuit of the memory that is the IC chip for reliability reasons, but this Therefore, the pull-up time becomes long.

This is because the value of the pull-up resistor cannot be made too small for the above reason, and therefore it takes a lot of time to drive the capacitance of the parity error output connected by the wired OR. If the pull-up time becomes long, it is necessary to wait until the level of the PE pin (parity error output) becomes "H" even if the output of the parity error circuit is confirmed, and then the output data of the memory is used. External processing can be performed. As a result, the time from the confirmation of the output of the parity check circuit to the confirmation of the output of the parity error causes a decrease in the speedup of the memory system.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor memory device in which a parity error output can be promptly fixed after the output of a parity check circuit is fixed, and the speed of a memory system can be increased.

[Means for solving the problem]

The semiconductor memory device according to the present invention achieves the above object,
Has a parity check circuit that checks whether or not there is an error in the read data from the memory.
In a semiconductor memory device in which the output of the parity check circuit is received by at least an open-drain MOS transistor and the result of the parity check is externally output from the drain side of the MOS transistor, during a predetermined period when the output of the parity check circuit is uncertain. Correspondingly, signal adjusting means for inhibiting the output of the parity check circuit is provided, and the drain side of the MOS transistor is kept in a high impedance state until the output of the parity check circuit is determined by the signal adjusting means.

[Action]

In the present invention, the signal adjusting means is provided on the output side of the parity check circuit, and the signal adjusting means corresponds to a predetermined period during which the output of the parity check circuit is indefinite,
The output of the parity check circuit is prohibited. And
As a result, the drain side of the MOS transistor is kept in a high impedance state until the output of the parity check circuit is determined.

Therefore, when the output of the parity check circuit is fixed, the parity error output is fixed immediately, and the speed of the memory system is increased.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 to 8 are views showing an embodiment of a semiconductor memory device according to the present invention. FIG. 1 is a block diagram showing the configuration of a memory system. First, the configuration will be described. In FIG. 1, 11 is an asynchronous memory and 12 is a parity check circuit. These are the same as those shown in the conventional example, but the internal configuration will be described in detail. Further, since the MOS transistor 3, the PE terminal 4 and the pull-up resistor 5 are the same as those in the conventional example, the same reference numerals are given and the duplicate description will be omitted.

First, the internal structure of the memory 11 is shown in FIG.
Memory 11 has word lines WDO, WD1, bit line BL0, ▲
The cells 13a to 13f are provided at matrix points defined by ▼, BL1, ▲ ▼, BL2, and ▲ ▼. Note that FIG. 2 shows a partial configuration of the memory 11. As shown in FIG. 3, one cell 13a is typically called a resistance load type memory cell, and is composed of drive MOS transistors 14a, 14b, resistors 15a, 15b and transfer MOS transistors 16a, 16b. It is a memory cell that is composed of a circuit and is a so-called static RAM.

Returning to FIG. 2 again, in the figure, 20a to 20c are bit line pairs (BL
0, ▲ ▼), (BL1, ▲ ▼), (BL2, ▲
▼) is a shorted MOS transistor, 21a to 21f are column selection MOS transistors, 22 is a data bus line DB, ▲
MOS transistor for shorting ▼, 23 is sense up. MOS transistors 20a to 20c, MOS transistors
22 and sense-up 23 are operated by a clock φ generated by the ATD circuit 24 shown in FIG. 1, and bit line pairs (BL0, ▲ ▼), (BL1, ▲ ▼) (BL2, ▲).
▼) and the data bus line DB, ▲ ▼ are short-circuited or precharged to speed up data reading. Also, the MOS transistors 21a to 21
f selects a column at the time of reading data based on the column decode outputs CD0 to CD2.

Returning to FIG. 1 again, the above-mentioned ATD circuit (addr-ess tran
The sition detector 24 is a circuit that detects a change in the address signals AD0 to ADm and generates a pulse, and is for internally generating a clock in an asynchronous SRAM to which a clock is not applied from the outside as in the present embodiment. Is. Specifically, as shown in FIG. 4, external address signals AD0 to ADm are used.
Address signal change detection circuits 25a0 to 25am corresponding to
And the NOR gate 26, the address signal AD0
~ If any one of ADm changes state, clock L1 (φ in Fig. 2) is generated, and even if there is a variation between address signals, it can be absorbed and normal operation can be performed. It has become. This is because asynchronous SRAMs are easy to use because they can be accessed at any time without the need for an external clock, but on the other hand, the circuits are always in operation, so they consume a lot of power and use a clock for high-speed operation. This is because the ATD circuit 24 is used to generate a clock and this clock is used to reduce the power consumption and increase the speed because it cannot be devised.

The output L1 of the ATD circuit 24 is input to the memory 11 as the clock φ and also to the signal adjusting means 27. The signal adjusting means 27 is composed of a delay circuit 28 and an AND gate 29, and the output L3 of the parity check circuit 12 and the output L2 of the delay circuit 28 are input to the AND gate 29. The parity check circuit 12 has the same function as that of the conventional example, but the detailed configuration is, for example, as shown in FIG. 5, seven exclusive OR gates (hereinafter, EX-O).
R gate) 30-36. The parity check circuit 12 shown in FIG. 5 is an example of 8 bits,
EX-OR gates 30 to 33 have read data OUT1 to OUT8 for each 2
Input one by one. If there is no error in the parity of the read data OUT1 to OUT8, the output L3 of the EX-OR gate 36 becomes "L" level, and if there is even one error, L3 becomes "H" level.

The detailed circuit of the signal adjusting means 27 is shown in FIG. 6, and the delay circuit 28 includes a delay element 37 and a NAND gate 38.
And an inverter 39, and the AND gate 29 comprises a NAND gate 40 and an inverter 41. The function of the signal adjusting means 27 will be described with reference to the timing chart of FIG. 7. Now, the output of the ATD circuit 24, in other words, the clock L1.
L1 is "H" in the section "a" in which the signal is not generated, the signal L1 'that has passed through the delay element 37 and is delayed is "H", and the output L2 of the delay circuit 28 is "H". Here, the delay element 37
The delay time in is set corresponding to the period in which the output of the parity check circuit 12 is indeterminate. When the address signal changes and the clock L1 becomes "L" in section b, the signal L2
Becomes "L" with a slight delay by the through time of the NAND gate 38 and the inversion time of the inverter 39. At this time, the delay time of the delay element 37 is irrelevant. When the section b ends and the clock L1 returns to "H", the signal L1 'becomes "H" after a delay time of the delay element 37, while the NAND gate 38 makes the clock L1 and the signal L1' both "H". Since "L" is sometimes output, the operation of the delay element 37 delays the return of the signal L2 to "H" by the section (time) c. In this way, the delay circuit 28 delays the rise when the output signal L2 changes from "L" to "H" by the delay time.

On the other hand, the AND gate 29 outputs to the MOS transistor 3 the signal L4 which becomes "H" when the output L3 of the parity check circuit 12 and the output L2 of the delay circuit 28 are both "H". MOS
The configuration after the transistor 3 is the same as that of the conventional example.
The left side portion of the PE terminal 4 in FIG. 1 is included in the chip as one IC.

Next, the operation of the embodiment will be described with reference to the timing chart of FIG. When the address to be read is specified by the external address signals AD0 to ADm when reading the data, and this change occurs when the address signals AD0 to ADm change.
The clock L1 (= φ) is generated by being detected by the ATD circuit 24 and is supplied to the memory 11 and the delay circuit 28. While the clock L1 is "L", the memory 11 is inactive,
Return to "H" and activate. Then, reading of data corresponding to the address is started from here, and the data output OUT1 to OUTn is determined after a certain time has elapsed. Data output
The interval (a) is represented until OUT1 to OUTn become valid data. Since this interval (a) contains uncertain data, the parity check circuit naturally receives this.
Indeterminate data is also present on the 12th output L3.

On the other hand, the output L3 of the parity check circuit 12 also has an uncertain period, and the output L3 becomes valid data in the clock.
It will be after a lapse of time x since L1 returned to "H". Therefore, the uncertain period of the output L3 of the parity check circuit 12 is represented by the section (b). Therefore, the output L2 of the delay circuit 28 changes (in this case, changes from “L” to “H”) in response to the change of the clock L1 is set in a section (C) that can sufficiently cover the time x, When this section (C) elapses, the signal L2 rises to "H", so that the output L3 of the parity check circuit 12 is supplied to the MOS transistor 3 through the AND gate 29 as the signal L4. As an example, when there is a parity error in the read data OUT1 to OUTn, the output L3 of the parity check circuit 12 becomes "H".

FIG. 8 shows an example in which there is a parity error. Even in such a case, the signal L2 is "L" until the uncertain period of the parity check circuit 12 ends and valid data appears.
Have been dropped. Therefore, the signal L4 is also "L" during this period.
At the level, the MOS transistor 3 is in the OFF state
The PE terminal 4 is fixed in a high impedance state. However, the pull-up resistor 5
Is connected, the signal L4 is gradually changed to "H" level from the time when the signal L4 falls to "L", and when the section (C) ends, it is almost at "H" level. It is in a state. Therefore, when the section (c) has passed after the output L3 of the parity check circuit 12 has been determined, that is, when the signal L4 rises, the PE terminal 4 can immediately shift to the “H” level when the MOS transistor 3 is turned on. Unlike the prior art, when the output L3 of the parity check circuit 12 is fixed, the parity error output can be used immediately. As a result, the output data of the memory can be used at the same time as the parity error output, and the speed of the memory system can be increased.

Further, such an effect is particularly effectively exhibited when a large number of SRAMs as shown in FIG. 1 are connected in parallel to the PE terminal 4 and the capacity is large.

There is a concept that the above effect can be obtained by the clock L1 generated by the ATD circuit 24, but this is not practically possible. That is, the clock L1 is “L”
It is a clock for deactivating the memory 11 in the section,
Memory 11 is activated and output of parity check circuit 12
Since L3 becomes valid data after the clock L1 returns to "H" and the time x has passed, the effect of this embodiment cannot be achieved only by the clock L1. Therefore, it is necessary to have a configuration as in this embodiment.

Next, FIG. 9 is a diagram showing a second embodiment of the semiconductor memory device according to the present invention, and this embodiment is an application example to a synchronous SRAM. In FIG. 9, 45 is an internal clock generator that generates an internal clock by using an external clock CLK. The generated clock (internal clock) of the internal clock generator 45 is an address side register 46, an output data side register 47, and It is supplied to the signal adjusting means 27.
The register 46 and the register 47 hold the address and the data respectively according to the internal clock, and the memory 11 also reads the data according to the internal clock. Other configurations are the same as those in the first embodiment, and are designated by the same reference numerals.

Therefore, the second embodiment can obtain the same effect as that of the first embodiment, although there is a difference in how to take the clock.

Although the above embodiment is an example using SRAM, the application of the present invention is not limited to this, and other types can be applied to a semiconductor memory with a parity check circuit.

〔effect〕

According to the present invention, the parity error output can be promptly fixed after the output of the parity check circuit is uncertain, and the speed of the memory system can be increased.

[Brief description of drawings]

1 to 8 are diagrams showing a first embodiment of a semiconductor memory device according to the present invention, FIG. 1 is an overall configuration diagram thereof, FIG. 2 is a diagram showing a detailed configuration of the memory thereof, and FIG. Is a circuit diagram of the one memory cell, FIG. 4 is a circuit diagram of the ATD circuit, FIG. 5 is a circuit diagram of the parity check circuit, FIG. 6 is a circuit diagram of the signal adjusting means, and FIG. 8 is a timing chart for explaining the operation of the signal adjusting means, FIG. 8 is a timing chart for explaining the overall operation thereof, and FIG. 9 is an overall configuration diagram showing a second embodiment of the semiconductor memory device according to the present invention. FIG. 10 is an overall configuration diagram showing a conventional semiconductor memory device. 3 ... MOS transistor 3 (open drain MOS transistor), 4 ... PE terminal, 5 ... pull-up resistor, 11
...... Memory, 12 ...... Parity check circuit, 13a to 13f
...... Cell, 14a, 14b …… Driving MOS transistor, 15a, 15
b …… resistor, 16a, 16b …… transfer MOS transistor, 20-22
…… MOS transistor, 23 …… Sense up, 24 …… ATD
Circuit, 26 ... NOR gate, 27 ... Signal adjusting means, 28 ...
Delay circuit, 29 …… and gate, 30-36 …… EX-OR
Gate, 37 ... Delay element, 38, 40 ... NAND gate, 39, 41 ... Inverter, 45 ... Clock generator, 46, 47 ... Register.

Claims (1)

(57) [Claims] 1. A parity check circuit for checking whether or not there is an error in read data of a memory, wherein an output of the parity check circuit is received by at least an open drain MOS transistor, and a drain side of the MOS transistor. In a semiconductor memory device for externally outputting the result of the parity check from the parity check circuit, there is provided signal adjusting means for inhibiting the output of the parity check circuit corresponding to a predetermined period in which the output of the parity check circuit is uncertain. The semiconductor memory device is characterized in that the drain side of the MOS transistor is kept in a high impedance state until the output of the parity check circuit is determined by.