JP2813229B2 - Semiconductor storage device with data protection function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION 【Overview】

A semiconductor memory device with a data protection function for preventing erroneous writing due to noise or malfunctioning is intended to facilitate a writing operation and to provide a single write control terminal. A write enable decoding circuit that receives a serial write enable signal as a signal, decodes the signal, generates and outputs a write enable signal, and an input / output control signal including the write enable signal. An input / output control circuit for controlling input / output.

[Industrial applications]

The present invention relates to a semiconductor memory device with a data protection function for preventing erroneous writing due to noise or malfunction.

[Prior art]

In a semiconductor memory device, for example, during data reading, if a write enable signal ▲ ▼ is generated due to noise or malfunction and erroneous writing is performed, the data is destroyed, especially when data is held for a long time and used. It can cause major problems. In order to prevent such erroneous writing, the following semiconductor memory device has taken the following erroneous writing prevention measures. (1) A word for prohibiting / permitting a write operation is secured at a specific address of the semiconductor memory device. Normally, write prohibition is set for this word, and a write enable signal ▲ ▼ is inadvertently sent to the semiconductor memory device. Do not supply. (2) The write enable terminal is directly connected to the power supply terminal, fixed at a high level, and put in a write-protected state. (3) A plurality of write control signals are supplied to the semiconductor memory device, and writing permission / inhibition is determined in the semiconductor memory device based on a logical value combination of the control signals.

[Problems to be solved by the invention]

However, in the above method (1), every time data is written, the write-protection state must be released before writing, and the setting to prohibit the write operation after writing must be performed, so that the write operation is complicated. Rewriting cannot be performed by the method (2). In the method (3), the number of external terminals of the semiconductor memory device increases. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device with a data protection function in which a write operation is easy and a single write control terminal is sufficient in view of such problems.

[Means for Solving the Problems]

The principle configuration of the present invention will be described with reference to FIG. In the figure, reference numeral 12 denotes a memory cell array, which is readable and writable. 16 is a write enable decoding circuit, which receives a serial write enable signal ▲ ▼ which is a serial signal,
This signal is decoded to generate and output a write enable signal ▲ ▼. An input / output control circuit 14 receives an input / output control signal including the write enable signal ラ イ ト, and controls input and output of data to and from the memory cell array 12.

[Action]

Even if the level of the serial write enable signal ▲ ▼ changes due to noise or malfunction, the write enable decoding circuit 16 outputs this signal unless the serial write enable signal ▲ ▼ has a predetermined waveform. Do not decode. Therefore, erroneous writing to the semiconductor memory device due to noise or malfunction is prevented. Further, since the serial write enable signal ▼ has a predetermined fixed waveform, it is not necessary to set a serial write enable signal generation code by a program every time writing is performed, and the writing operation is easy. Further, since the serial write enable signal ▼ is a serial signal, one write control terminal is sufficient.

【Example】

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. (1) First Embodiment FIG. 1 shows a schematic configuration of a RAM 10. The RAM 10 includes a memory cell array 12, an input / output control circuit 14, and a write enable decoding circuit 16. The write enable decoding circuit 16 receives the serial write enable signal ▼ and the chip enable signal ▼ shown in FIGS. 3A and 3B, and generates the write enable signal ▲ shown in FIG. Then, the data is supplied to the input / output control circuit 14. The input / output control circuit 14 includes a chip enable signal ▲ ▼, a write enable signal ▲ ▼,
The data input / output between the outside and the memory cell array 12 is controlled using the clock CK and the address. As shown in FIG. 2, the write enable decoding circuit 16 is asynchronous and includes a quaternary counter 18 and a NAND gate 20. A serial write enable signal の is supplied to a clock input terminal CK of the quaternary counter 18, and a chip enable signal ▲ is supplied to an input terminal of the NAND gate 20.
▼ The 0th bit Q ₀ and the 1st bit of the calculated value of the quaternary counter 18
Bit Q ₁ is supplied. From the NAND gate 20, a write enable signal ▼ is extracted. Next, the operation of the present embodiment configured as described above will be described in the third.
This will be described with reference to the drawings. When a microprocessor (not shown) starts executing a write command to the RAM 10, a chip enable signal ▲
Is set to a low level (FIG. 3B), an address is supplied to the input / output control circuit 14 (FIG. 3E), and a serial write enable signal イ ネ ー ブ ル is supplied to the write enable decoding circuit 16 (FIG. 3B). (FIG. 3A), write data is supplied to the input / output control circuit 14 (FIG. 3D). The quaternary counter 18 outputs the serial write enable signal ▲
The rising edge of ▼ is counted, and when the count value is 3, that is, when the output bits Q ₀ and Q ₁ become high level, the write enable signal ▼ changes from high level to low level (FIG. 3 (C)). As a result, the memory cell array 12 enters a data write state, and data is written to the designated address of the memory cell array 12 via the input / output control circuit 14. Next, when the serial write enable signal ▲ ▼ goes high, the output bits Q ₀ and
Q ₁ is becomes low level, the write enable signal ▲ ▼ goes high. Even if the level of the serial write enable signal ▼ changes due to noise or malfunction, the serial write enable signal ▼ is determined in advance in FIG.
Unless the waveform shown in the figure is reached, the write enable decoding circuit
16 does not decode this as a write enable signal ▼, so that erroneous writing to the RAM 10 due to noise or malfunction is prevented. Further, since the serial write enable signal ▼ has a predetermined fixed waveform, it is not necessary to set a serial write enable signal generation code by a program every time writing is performed, and the writing operation is easy. Further, since the serial write enable signal ▼ is a serial signal, one write control terminal is sufficient. (2) Second Embodiment FIG. 4 shows a write enable decoding circuit 26 of a second embodiment. The write enable decoding circuit 26 is of a synchronous type that operates based on a clock CK, and has a mode setting flag 28 that is fixedly set in a manufacturing stage. When the mode setting flag 28 is set to 0 (normal mode), the AND gate 30 is opened, and the serial write enable signal ▼ passes through the AND gate 30 and the OR gate 32 as it is, and the write enable signal ▲
Output as ▼. When the mode setting flag 28 is set to 1 (data protection mode), the AND gate 30 is closed and the AND gate 34 is opened. A write enable code, for example, 10110, is fixedly set in the code setting unit 36 at the manufacturing stage, and is supplied to one input terminal of the coincidence determination circuit 38. The content of the shift register 40 is supplied to the other input terminal of the match determination circuit 38. To the shift register 40, the serial write enable signal ▼ is supplied to the most significant bit, and the clock CK is supplied to all bits. In synchronization with the rise of the clock CK, the serial write enable signal ▲ is taken into the most significant bit of the shift register 40, and the content of the shift register 40 is shifted by one bit lower. The match determination circuit 38
When the content of the shift register 40 matches the content of the code setting device 36, the output is set to a high level and the RS flip-flop 42
To the set state. The RS flip-flop 42 is reset at the rise of the serial write enable signal ▼. Inverted output Q of RS flip-flop 42
Is passed through an AND gate 34 and an OR gate 32 and is taken out as a write enable signal ▼. Next, the operation of the present embodiment configured as described above will be described in the fifth.
This will be described with reference to the drawings. The clock CK and the serial write enable signal ▼ shown in FIGS. 5A and 5B are supplied to the shift register 40, and when the content of the shift register 40 becomes 01101, the coincidence determination circuit 38 outputs the signal (C). ) Is output, the RS flip-flop 42 is set, and the write enable signal ▼ becomes low as shown in FIG. Next, when the serial write enable signal ▼ changes to low level and then changes to high level, the rising edge thereof resets the RS flip-flop 42, and the write enable signal ▼ changes to high level. Other points are the same as the first embodiment. It should be noted that the code set in the code setting unit 36 is kept secret, and when a write instruction is executed, the code set in a register (not shown) is converted into serial data to generate a serial write enable signal ▲ ▼. For example, the code may be set only once after the power is turned on. In this case, since only a specific user can write, the data protection function is enhanced.

【The invention's effect】

As described above, in the semiconductor memory device with the data protection function according to the present invention, the write operation is easy because the serial write enable signal generation code does not need to be set by the program for each write. Is a serial signal, which has an excellent effect that only one write control terminal is required, which greatly contributes to improvement in reliability and simplification of the configuration using the semiconductor memory device.

[Brief description of the drawings]

1 to 3 relate to a first embodiment of a semiconductor memory device with a data protection function according to the present invention. FIG. 1 is a schematic configuration diagram of a RAM, FIG. 2 is a write enable decoding circuit diagram, FIG. 3 is a timing chart of the circuits shown in FIGS. 1 and 2. 4 and 5 relate to a second embodiment of the present invention, FIG. 4 is a write enable decoding circuit diagram, and FIG. 5 is a timing chart of the circuit of FIG. In the figure, 10 is a RAM 12 is a memory cell array 14 is an input / output control circuit 16, 26 is a write enable decoding circuit 18 is a quaternary counter 28 is a mode setting flag 36 is a code setter 38 is a match determination circuit 40 is a shift register

Claims (1)

(57) [Claims] A readable and writable memory cell array (12)
And a serial write enable signal (▲
▼) is input, a write enable decoding circuit (16, 26) for decoding the signal to generate and output a write enable signal (▲ ▼), and an input / output control signal including the write enable signal are input. An input / output control circuit (14) for controlling input / output of data to / from the memory cell array. A semiconductor memory device with a data protection function, comprising: