JP2712410B2 - Method for manufacturing capacitor - Google Patents
Method for manufacturing capacitorInfo
- Publication number
- JP2712410B2 JP2712410B2 JP63276802A JP27680288A JP2712410B2 JP 2712410 B2 JP2712410 B2 JP 2712410B2 JP 63276802 A JP63276802 A JP 63276802A JP 27680288 A JP27680288 A JP 27680288A JP 2712410 B2 JP2712410 B2 JP 2712410B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- wiring
- manufacturing
- electrode
- base electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、マイクロ波集積回路のMIM（Metal−Insu
lator−Metal）構造のキャパシタの製造方法に関するも
のである。The present invention relates to a MIM (Metal-Insu) for a microwave integrated circuit.
The present invention relates to a method for manufacturing a capacitor having a lator-metal structure.
第２図（ａ）〜（ｃ）は従来のMIM構造のキャパシタ
の製造工程を説明する断面図である。2 (a) to 2 (c) are cross-sectional views illustrating a process for manufacturing a conventional capacitor having a MIM structure.
この図において、１はサファイヤ等の絶縁体基板、２
は下地電極、３は誘電体膜、４は上地電極で、これらで
MIM構造のキャパシタが構成されている。また、４′は
前記下地電極２に接続されて形成された上地電極であ
り、Ｘは前記誘電体膜３の絶縁破壊箇所を示すものであ
る。In this figure, 1 is an insulating substrate such as sapphire, 2
Is a base electrode, 3 is a dielectric film, and 4 is an upper electrode.
A capacitor having a MIM structure is configured. Reference numeral 4 'denotes an upper electrode formed by being connected to the base electrode 2, and X denotes a dielectric breakdown portion of the dielectric film 3.
次に従来の製造工程について説明する。 Next, a conventional manufacturing process will be described.
まず、第２図（ａ）のように、下地電極２をサファイ
ヤ等の絶縁体基板１上にリフトオフ法等により形成す
る。次に第２図（ｂ）のように、誘電体膜３としてシリ
コン窒化膜を全面に堆積した後、余分な部分をエッチン
グ除去する。最後に上地電極４をリフトオフ法等により
形成し、第２図（ｃ）に示すMIM構造のキャパシタを構
成する。First, as shown in FIG. 2A, a base electrode 2 is formed on an insulating substrate 1 such as sapphire by a lift-off method or the like. Next, as shown in FIG. 2 (b), after depositing a silicon nitride film as the dielectric film 3 on the entire surface, an unnecessary portion is removed by etching. Finally, the upper electrode 4 is formed by a lift-off method or the like, thereby forming a capacitor having the MIM structure shown in FIG. 2 (c).
上記のような従来のMIM構造のキャパシタは、MIM構造
のキャパシタを構成する下地電極２と上地電極４は完全
に絶縁されているために、それぞれの電極が帯電した場
合、両電極2,4間に電位差が生じ、誘電体膜３部分で絶
縁破壊しやすいという欠点があった。In the conventional capacitor having the MIM structure as described above, the base electrode 2 and the upper electrode 4 constituting the capacitor having the MIM structure are completely insulated. There is a drawback that a potential difference occurs between the dielectric films 3 and dielectric breakdown easily occurs at the dielectric film 3 portion.
この発明は、上記のような問題点を解消するためにな
されたもので、絶縁破壊を生じないキャパシタの製造方
法を得ることを目的とする。The present invention has been made to solve the above problems, and has as its object to obtain a method of manufacturing a capacitor that does not cause dielectric breakdown.
この発明に係るキャパシタの製造方法は、プロセス中
はMIM構造のキャパシタを構成する上地電極と、下地電
極とを導電性物質からなる配線によって接続しておき、
最終工程において化学処理を用いない手段で前記配線を
切断するものである。In the method for manufacturing a capacitor according to the present invention, the upper electrode and the lower electrode constituting the capacitor having the MIM structure are connected to each other by a wiring made of a conductive material during the process,
In the final step, the wiring is cut by means not using a chemical treatment.
この発明におけるMIMキャパシタの製造方法におい
て、下地電極と上地電極が同電位であるので、誘電体膜
がプロセス途中で絶縁破壊することがない。In the method of manufacturing a MIM capacitor according to the present invention, the base electrode and the upper electrode have the same potential, so that the dielectric film does not break down during the process.
以下、この発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（ｆ）はこの発明の一実施例を示すMI
M構造のキャパシタの製造工程を示す図で、第１図
（ａ）〜（ｃ）は断面図を示し、第１図（ｄ）〜（ｆ）
は絶縁体基板を除いた平面図を示すものである。第１図
において、第２図と同一符号は同一構成部分を示し、５
は前記上地電極４と４′とを接続する導電性物質からな
る配線である。FIGS. 1 (a) to 1 (f) show an MI according to an embodiment of the present invention.
FIGS. 1 (a) to 1 (c) are cross-sectional views showing a process for manufacturing an M-structure capacitor, and FIGS. 1 (d) to 1 (f) are cross-sectional views.
Is a plan view excluding the insulator substrate. In FIG. 1, the same reference numerals as those in FIG.
Is a wiring made of a conductive material for connecting the upper electrodes 4 and 4 '.
次に製造工程について説明する。 Next, the manufacturing process will be described.
まず、第１図（ａ），（ｄ）のように、下地電極２を
サファイヤ等の絶縁体基板１上にリフトオフ法等により
形成する。次に、第１図（ｂ），（ｅ）のように、誘電
体膜３としてシリコン窒化膜を、例えば厚み1000Åで全
面に堆積した後、余分な部分をエッチング除去する。次
に、第１図（ｃ），（ｆ）のように、上地電極４と４′
とを接続する導電性部材からなる配線５とをともに有す
るパターンをリフトオフ法により形成する。最後に、配
線５を例えばレーザで切断する。First, as shown in FIGS. 1A and 1D, a base electrode 2 is formed on an insulating substrate 1 such as sapphire by a lift-off method or the like. Next, as shown in FIGS. 1 (b) and 1 (e), a silicon nitride film as a dielectric film 3 is deposited on the entire surface at a thickness of, for example, 1000.degree. Next, as shown in FIGS. 1 (c) and 1 (f), the upper electrodes 4 and 4 '
Are formed by a lift-off method, together with a wiring 5 made of a conductive member for connecting to the wiring. Finally, the wiring 5 is cut by, for example, a laser.
なお、上記実施例では上地電極４と４′とを接続する
導電性物質からなる配線５は、上地電極４と同一の金属
でできているが、下地電極２と同一の金属等で形成して
もよく、また、その他の導電性を有する物質ならば何で
も良い。また、配線５を切断するためにレーザを使用し
たが、その他の方法で、例えば針で引っ掻く、またはカ
ッターで切断する等の方法をとっても良い。In the above embodiment, the wiring 5 made of a conductive material for connecting the upper electrodes 4 and 4 'is made of the same metal as the upper electrode 4, but is formed of the same metal as the lower electrode 2. Or any other conductive material. Although the laser is used to cut the wiring 5, other methods such as scratching with a needle or cutting with a cutter may be used.
以上説明したようにこの発明は、プロセス中はMIM構
造のキャパシタを構成する上地電極と下地電極とを導電
性物質からなる配線により接続しておき、最終工程にお
いて化学処理を用いない手段で前記配線を切断するよう
にしたので、プロセスの途中では上地電極と下地電極が
同電位に保たれるため、誘電体膜が絶縁破壊することが
ないMIM構造のキャパシタが得られ、かつアセンブリ後
に切断することもできるので、アセンブリ途中での絶縁
破壊を十分に防止できる利点がある。As described above, according to the present invention, during the process, the upper electrode and the lower electrode constituting the capacitor of the MIM structure are connected by a wiring made of a conductive substance, and the final step is performed by a means not using a chemical treatment. Since the wiring is cut, the upper electrode and the lower electrode are kept at the same potential during the process, so that a capacitor with a MIM structure that does not cause dielectric breakdown in the dielectric film can be obtained and cut after assembly. Therefore, there is an advantage that dielectric breakdown during the assembly can be sufficiently prevented.
第１図（ａ）〜（ｆ）はこの発明の一実施例を示すキャ
パシタの製造工程を説明する図であり、第１図（ａ）〜
（ｃ）は断面図、第１図（ｄ）〜（ｆ）は絶縁体基板を
除いた平面図、第２図（ａ）〜（ｃ）は従来のキャパシ
タの製造工程を説明する断面図である。 図において、１は絶縁体基板、２は下地電極、３は誘電
体膜、4,4′は上地電極、５は配線である。 なお、各図中の同一符号は同一または相当部分を示す。1 (a) to 1 (f) are views for explaining a manufacturing process of a capacitor according to an embodiment of the present invention.
1C is a cross-sectional view, FIGS. 1D to 1F are plan views excluding an insulating substrate, and FIGS. 2A to 2C are cross-sectional views illustrating a conventional capacitor manufacturing process. is there. In the figure, 1 is an insulator substrate, 2 is a base electrode, 3 is a dielectric film, 4, 4 'are upper electrodes, and 5 is a wiring. The same reference numerals in each drawing indicate the same or corresponding parts.
Claims (1)
体膜，および上地電極からなるMIM構造のキャパシタの
製造方法において、前記MIM構造のキャパシタを構成し
ている上地電極と下地電極とを導電性物質からなる配線
によって電気的に接続しておき、最終工程において、化
学処理を用いない手段にて前記配線を切断する工程を含
むことを特徴とするキャパシタの製造方法。1. A method of manufacturing a capacitor having a MIM structure comprising a base electrode, a dielectric film, and a base electrode formed on an insulator substrate, wherein the base electrode and the base which constitute the capacitor having the MIM structure are provided. A method for manufacturing a capacitor, comprising: a step of electrically connecting an electrode with a wiring made of a conductive substance; and a step of cutting the wiring by means not using a chemical treatment in a final step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276802A JP2712410B2 (en) | 1988-10-31 | 1988-10-31 | Method for manufacturing capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276802A JP2712410B2 (en) | 1988-10-31 | 1988-10-31 | Method for manufacturing capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02122561A JPH02122561A (en) | 1990-05-10 |
| JP2712410B2 true JP2712410B2 (en) | 1998-02-10 |
Family
ID=17574587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63276802A Expired - Fee Related JP2712410B2 (en) | 1988-10-31 | 1988-10-31 | Method for manufacturing capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2712410B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007149857A (en) * | 2005-11-25 | 2007-06-14 | Nec Electronics Corp | Semiconductor device, and designing method therefor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6381842A (en) * | 1986-09-25 | 1988-04-12 | Toshiba Corp | Manufature of semiconductor device |
-
1988
- 1988-10-31 JP JP63276802A patent/JP2712410B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02122561A (en) | 1990-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4337115A (en) | Method of forming electrodes on the surface of a semiconductor substrate | |
| JPS5873166A (en) | Capacitive pressure transducer and method of producing same | |
| US3939047A (en) | Method for fabricating electrode structure for a semiconductor device having a shallow junction | |
| JPH0574940B2 (en) | ||
| JP2712410B2 (en) | Method for manufacturing capacitor | |
| JPH1154706A (en) | Mim capacitor and its manufacture | |
| KR890011035A (en) | Integrated circuit manufacturing method and electrical connection forming method | |
| JPS587862A (en) | Bipolar transistor structure and method of producing same | |
| JPS5890755A (en) | Semiconductor device | |
| JPS6125221B2 (en) | ||
| JPH0247862A (en) | Semiconductor integrated circuit device | |
| JPH0122989B2 (en) | ||
| JPH01186657A (en) | Manufacture of semiconductor device | |
| JPS59208750A (en) | Wiring structure of semiconductor device | |
| JPH09283617A (en) | Semiconductor device and manufacture thereof | |
| JPS62281356A (en) | Manufacture of semiconductor device | |
| JPS5841775B2 (en) | hand tai souchi no seizou houhou | |
| JPH03248445A (en) | Manufacture of semiconductor device | |
| JPH05326313A (en) | Capacitor and manufacture thereof | |
| JPH06325969A (en) | Thin film capacitor and manufacture thereof | |
| JPH0454975B2 (en) | ||
| JPS61198660A (en) | Mim capacitor of semiconductor ic | |
| JPS62122277A (en) | Space wiring method of semiconductor element | |
| JPS6278853A (en) | Manufacture of semiconductor device | |
| JPS61194852A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |