JP2708455C - - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a solid-state imaging device suitable for a high-quality camera, in which the optical signal accumulation time of each pixel is exactly the same. [Prior Art] A pixel amplifier type solid-state imaging device that amplifies a signal charge generated in a photodiode and outputs the amplified signal charge on a light receiving surface in the vicinity of the photodiode has been disclosed in 1982 by the IEICE General Conference 1241. Are discussed in The conventional example will be described below with reference to FIG. FIG. 3 is a circuit configuration diagram of a conventional solid-state imaging device. Each pixel arranged two-dimensionally on the light receiving surface includes a photodiode 1 for performing photoelectric conversion, a pixel amplifier transistor 2 for amplifying the voltage of the photodiode 1, a vertical connection for connecting the pixel amplifier transistor 2 and the vertical drain line 5, It has a switch transistor 3 and a reset transistor 4 for resetting the photodiode 1. The gate of the pixel amplifier transistor 2 and the source of the reset transistor 4 are connected to the photodiode 1, and the drain of the reset transistor 4 and the drain of the vertical switch transistor 3 are connected to the vertical drain line 5, respectively. The drain of the pixel amplifier transistor 2 is connected to the source of the vertical switch transistor, and the source of the pixel amplifier transistor 2 is connected to the vertical signal line 7.
The source of the horizontal switch transistor 8 is connected to a horizontal signal line 9, and one end of the horizontal signal line 9 is an output terminal. The vertical gate line 6 and the vertical drain line 5 connected to the gates of the vertical switch transistor 3 and the reset transistor 4 are connected to the vertical shift register 10.
Accordingly, the gate of the horizontal switch transistor 8 is selectively scanned by the horizontal shift register 11. Next, the operation of this conventional example will be described. Signal charges are generated and stored in the photodiode 1 by photoelectric conversion in the silicon of light incident on the light receiving surface. When one set of the vertical gate line 6 and the vertical drain line 5 is set to the high level by the vertical shift register 10 during the horizontal blanking period, the vertical switch transistors 3 of the pixels are turned on in a row connected to these two lines. Then, the drain of the pixel amplifier transistor 2 connected to the source is made conductive to the vertical drain line 5. Next, when the horizontal shift register 11 sequentially turns on the horizontal switch transistors 8 within the horizontal scanning period, the sources of the pixel amplifier transistors 2 are sequentially turned on with the horizontal signal lines 9, and as a result, the selected pixels in one horizontal row are The amplifier transistors 2 operate sequentially. The voltage of the photodiode 1 is determined by the amount of electric charge stored in the photodiode 1. Since the voltage of the photodiode 1 is applied to the gate of the pixel amplifier transistor 2, the pixel amplifier transistor 2 corresponding to the amount of signal charge of the photodiode 1 is eventually turned on. Is output from the horizontal signal line 9. The above is the readout operation of this conventional example. The reset operation between the gate of the pixel amplifier transistor 2 and the photodiode 1 is performed after the horizontal scanning output of the pixel in the nth column is completed and the pixel in the (n + 1) th column is completed. By resetting the reset transistor 4 of the pixel in the n-th column by setting the vertical gate line 6 corresponding to the high level to high level, all the photodiodes 1 in the n-th column are reset collectively. [Problems to be Solved by the Invention] In the above-mentioned conventional technology, after resetting the gate of the pixel amplifier transistor 2, the signal charge is stored in the photodiode 1, and the pixel amplifier transistor 2 corresponding to the signal charge amount stored in the photodiode 1 is stored. Is read out through the horizontal switching transistor 8. As a result, the output voltage of the pixel amplifier transistor 2 is read out with the reset noise voltage superimposed on the signal charge voltage. in this way,
In the above prior art, no consideration is given to the elimination of reset noise, and there is a problem that image quality deteriorates. An object of the present invention is to provide a solid-state imaging device in which the image quality is not degraded due to the above reasons. [Means for Solving the Problems] The above object is achieved by a photoelectric conversion means for converting an optical signal into a signal charge and storing the signal charge; a reading means for reading the signal charge stored in the photoelectric conversion means; Amplifying means for amplifying the amplified signal charge, and reset means for resetting the signal charge in the amplifying means as constituent elements of the pixel, and when the amplifying means is reset and its output is connected to a plurality of pixels connected to each other. This is achieved by a solid-state imaging device having a unit for obtaining a difference between two outputs of the amplifying unit when a signal charge is input to the amplifying unit by selecting one pixel readout unit. [Operation] In the present invention, the reset noise output, which is the output of the amplifying means when the amplifying means is reset, and the sum of the reset noise output, which is the output of the amplifying means when the signal charge is input to the amplifying means, and the signal charge output. Can be separately taken out, and by obtaining these differences, reset noise can be removed and deterioration of image quality can be prevented. Embodiment An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a circuit diagram of one embodiment of the present invention. Each pixel arranged two-dimensionally on the light receiving surface has a photodiode 1 for performing photoelectric conversion and a vertical drain line for amplifying a voltage of the photodiode 1.
A reset transistor 4 for resetting the pixel amplifier transistor 2 and the photodiode 1 connected to 12 is provided. Pixel amplifier transistor 2
The gate of the reset transistor 4 and the source of the reset transistor 4 are connected to the photodiode 1, and the drain of the reset transistor 4 and the drain and gate of the vertical switch transistor 3 are connected to the vertical drain line 12, respectively. The drain of the pixel amplifier transistor 2 is connected to the source of the vertical switch transistor 3, and the source of the pixel amplifier transistor 2 is connected to the vertical signal line 14. Here, the vertical gate line 13 and the vertical drain line 12 connected to the gate of the reset transistor 4 are both selected and scanned by the vertical shift register 10. One end of the vertical signal line 14 is connected to a signal reset line 14 'via a signal reset switch transistor 15 whose gate is controlled by a signal reset gate line 16, and a storage capacitor gate line 18 controls the gate. Connected to a storage capacitor 19 via a storage capacitor switch transistor 17. The storage capacitor 19 is connected to a horizontal signal line 23 by a horizontal switch transistor 20 selected and scanned by a horizontal shift register 22 via a horizontal gate line 21, and an output amplifier 24 is connected to an end of the horizontal signal line 23. Is connected. Further, a photogate transistor 26 scanned by the vertical shift register 10 via the photogate line 25 is provided between the photodiode 1 and the gate of the pixel amplifier transistor 2. Next, the operation of this embodiment will be described. Signal charges are generated and stored in the photodiode 1 by photoelectric conversion in the semiconductor of light incident on the light receiving surface. At the beginning of the horizontal retrace period, the vertical shift register 10 sets a set of the vertical drain line 12 and the vertical gate line 13 corresponding to the pixels in the horizontal row of the n-th column in the vertical direction to a high level, and simultaneously sets the signal. By setting the reset gate line 16 and the signal reset line 14 'to a high level, the gate of the pixel amplifier transistor 2 in the nth column in the vertical direction is reset. The reason why the vertical drain line 12 and the vertical gate line 13 are set to the high level is to operate the reset transistor 4, and the signal reset gate line 16 and the signal reset line 14 'are set to the high level because the signal reset switch transistor is used. This is to prevent the operation of the pixel amplifier transistor 2 by setting the vertical signal line 14 to a high level via the line 15. This is because, when the pixel amplifier transistor 2 operates, a relatively large instantaneous current flows through the vertical drain line 12 so that the voltage drop cannot be ignored, which hinders resetting of the gate of the pixel amplifier transistor 2. Thereafter, the vertical drain line 12, the vertical gate line 13, the signal reset gate line 16 and the signal reset line 14 'are lowered to a low level, and the output of the pixel amplifier transistor 2 whose gate is reset is read into the storage capacitor 19. Do it. That is, when one vertical drain line 12 becomes high level by the vertical shift register 10, the pixel amplifier transistor 2 connected to this vertical drain line 12
Works. At this time, when the storage capacitor gate line 18 in the first column is set to a high level and the storage capacitor switch transistor 17 is turned on, the amplified signal charge from the pixel amplifier transistor 2 is stored in the storage capacitor 19 in the first column. Is accumulated through Storage capacity
After the amplified signal charge is stored in 19, the storage capacitor switch transistor 17 is turned off. Subsequently, by setting the photogate line 25 to a high level, the photodiode transistor 26 is turned on, and the signal charge stored in the photodiode 1 is read out to the gate portion of the pixel amplifier transistor 2. This operation is performed by the photodiode 1 Reset operation. At this time, if the structure of the photodiode 1 is determined so that the photodiode 1 after reading out the signal charge is completely depleted, reset noise and afterimage generated by the unread charge of the photodiode 1 can be removed. Thereafter, reading of the output of the pixel amplifier transistor 2 to the storage capacitor 19 is repeated again. However, the amplified signal charge of the pixel amplifier transistor 2 at the time of inputting the signal is different from the amplified signal charge of the pixel amplifier transistor 2 at the time of the previous reset. It goes without saying that the input is made to the storage capacitor 19 in another second column. Next, during the horizontal scanning period, the horizontal shift register 22 sets the horizontal switch transistor.
When the storage capacitors 20 are sequentially turned on, the respective storage capacitors 19 are sequentially connected to the output amplifier 24 via the horizontal switch transistor 20 and the horizontal signal line 23, and the output by the amplified signal charges stored in the storage capacitor 19 is output. can get. At this time, the outputs obtained from the two output amplifiers 24 correspond to the case where one resets the gate of the pixel amplifier transistor 2 and the case where one further inputs the signal charge from the photodiode 1 to this gate. . Therefore, at the final output terminal 24 ', the difference between these two output amplifiers 24 is obtained. In this embodiment, as described above, the difference between the amplified signal when the gate of the pixel amplifier transistor 2 is reset and the amplified signal when a signal charge is input to the gate of the pixel amplifier transistor 2 is output. There is an advantage that reset noise due to reset of the gate of the amplifier transistor 2 and low frequency components of the noise of the pixel amplifier transistor 2 can be suppressed. The method of taking such a difference is in principle the same as the method known as the correlated double sampling method. In this embodiment, the storage capacitors 19 are provided in two columns. However, it is needless to say that two rows can be read simultaneously with four columns. Hereinafter, another embodiment of the present invention will be described with reference to FIG. FIG. 2 is a circuit configuration diagram of another embodiment of the present invention, in which the number of storage capacitors 19 is the same as the number of pixels;
And a horizontal switch transistor 20, a vertical switch transistor 27 selectively scanned by a storage capacitor vertical gate line 28 from a storage capacitor vertical register 31 is provided, and each horizontal signal line 23 is also provided with a storage capacitor. Except that the output amplifier 24 is connected to the amplifier vertical signal line 30 via the readout switch transistor 28 selectively scanned by the vertical gate line 28, and the end of the amplifier vertical signal line 30 is provided. It has the same structure as the embodiment described with reference to FIG. Next, the operation of this embodiment will be described. In the present embodiment, reading of the amplified signal charges from all the pixel amplifier transistors to the storage capacitor 19 is continuously performed using, for example, a vertical blanking period. The method of reading the output of each pixel amplifier transistor 2 into the storage capacitor 19 is the same as in the embodiment described with reference to FIG. In FIG. 2, one of the storage capacitor portion for the amplified signal charge of the pixel amplifier transistor 2 at the time of signal input and the storage capacitor portion for the amplified signal charge of the pixel amplifier transistor 2 at the time of reset is connected. They are omitted for simplicity. Next, the operation in the vertical scanning period will be described. During the vertical scanning period, the vertical switch transistor 27 and the readout switch transistor 29 are transferred from the storage capacitor vertical register 31 via the storage capacitor vertical gate line 28 to the horizontal gate line from the horizontal shift register 22.
By selectively scanning the horizontal switch transistor 20 in the vertical scanning direction and the horizontal scanning direction via 21 respectively, the amplified signal charge stored in each storage capacitor 19 is
The output is sequentially output from the output amplifier 24 via the horizontal signal line 23 and the amplifier vertical signal line 30. The reset of the vertical signal line 14 is performed by setting the signal reset gate line 16 to a high level,
This is performed by turning on the signal reset switch transistor 15, but this can be performed at any timing except when reading the amplified signal charge from the pixel amplifier transistor 2 to the storage capacitor 19. The photodiode 1 can be reset by setting the photodiode line 25 to high level and turning on the photogate transistor 26. At this time, if the reset timing of the photodiodes 1 is appropriately changed, the accumulation time can be changed for all the photodiodes 1 while keeping the same optical signal accumulation time until the signal is read from the reset. This is the electronic shutter operation according to the present embodiment. The electronic shutter operation according to another embodiment is a focal plane shutter that scans the entire screen over one field period. While the video capture time differs by one field, the electronic shutter operation of the present embodiment is such that the entire screen can be scanned within the operation time of the pixel amplifier transistor 2 during the vertical blanking period. This is a plane shutter, which can significantly reduce the difference in image capturing time between the upper end pixel and the lower end pixel on the light receiving surface as compared with the other embodiments. In the above description of the embodiment, the selection of the read-out pixel is performed using the vertical shift register 10 and the horizontal shift register 22. However, it is not always necessary to use the shift register, and any pixel selection circuit may be used. , And one end of the photodiode 1 is dropped to a well, but it is not always necessary to connect the well to a certain voltage application means, and the signal reset switch 15 is not necessarily at one end of the vertical signal line 14 and is not necessarily a light receiving surface. That the photodiode 1 is not necessarily a pn junction, but can have a structure such as a MOS photodiode, and is not limited to 2 × 2 pixels, but is extended to a solid-state imaging device having an arbitrary number of pixels. What can be done, even if the p-type and n-type of the semiconductor characteristics are reversed, the magnitude relationship of the potentials should be reversed, not only silicon but also other Even using a semiconductor material, it is clear that the effect of conforming to the silicon is obtained. [Effects of the Invention] According to the present invention, since the optical signal accumulation time of each pixel can be made completely the same, it is possible to prevent the deterioration of the pixels due to the difference in the optical signal accumulation time between the pixels.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a circuit configuration of one embodiment of the present invention, FIG. 2 is a diagram showing a circuit configuration of another embodiment of the present invention, and FIG. FIG. 3 is a diagram illustrating a configuration. Reference numeral 1 denotes a photodiode, 2 denotes a pixel amplifier transistor, 4 denotes a reset transistor, 19 denotes a storage capacitor, 20 denotes a horizontal switch transistor, and 26 denotes a photogate transistor.

Claims (1)

Claims: 1. A photoelectric conversion means for converting an optical signal into a signal charge and storing the signal charge, a reading means for reading the signal charge stored in the photoelectric conversion means, and a reading means for reading through the reading means. Amplifying means for amplifying the obtained signal charge, and a reset means for resetting the signal charge in the amplifying means as a component of a pixel, and a plurality of which are connected when the amplifying means is reset and outputs thereof are connected to each other. Above pixel
A means for obtaining a difference between two outputs of the amplifying means when the signal charge is input to the amplifying means by selecting the reading means of one of the pixels . 2. A solid-state imaging device according to claim 1, wherein said means for obtaining the difference between the two outputs is means for performing correlated double sampling. 3. A first storage means for storing the output of the amplification means when the amplification means is reset, and a second storage means for storing the output of the amplification means when the signal charge is input to the amplification means. has a storage means, wherein said means for obtaining a difference between two outputs of the amplifying means is to obtain a difference between the two output through said first storage means and the second storage means The solid-state imaging device according to claim 1.