JP2021068758A - Solid-state image pickup device, method for manufacturing solid-state image pickup device and electronic apparatus - Google Patents

Abstract

To provide a solid-state image pickup device, a method for manufacturing a solid-state image pickup device and an electronic apparatus, which are capable of acquiring highly accurate phase difference information with low power consumption without losing saturation charge and moreover without image correction, while suppressing a decrease in sensitivity, resulting in capable of improving image quality without using a complicated reading-out method.SOLUTION: In a solid-state image pickup device 10, a photoelectric conversion function region 2211 formed by a first conductivity type (n type) semiconductor layer (n layer) and a charge storage function region 2212 are arranged, in a photodiode 200 (PD) that serves as a photoelectric conversion part, offset from the central part CTpd of the photodiode 200 (PD) that serves as a photoelectric conversion part; and an isolation region 2241 formed by a second conductivity type (p type) semiconductor layer (p layer) 224 is arranged in a region excluding the photoelectric conversion function region 2211 and the charge storage function region 2212.SELECTED DRAWING: Figure 4

Description

The present invention relates to a solid-state image sensor, a method for manufacturing a solid-state image sensor, and an electronic device.

A CMOS (Complementary Metal Oxide Semiconductor) image sensor is put into practical use as a solid-state image sensor (image sensor) using a photoelectric conversion element that detects light and generates an electric charge.
CMOS image sensors are widely applied as part of various electronic devices such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile terminal devices (mobile devices) such as mobile phones. There is.

The CMOS image sensor has an FD amplifier having a photodiode (photoelectric conversion element) and a floating diffusion layer (FD) for each pixel, and its reading selects a certain line in the pixel array. However, the column parallel output type that reads them out in the column direction at the same time is the mainstream.

By the way, in an imaging device such as a digital camera, as a method for realizing automatic focus adjustment (autofocus (AF)), for example, phase difference information of autofocus (AF) is obtained from a part of pixels of a pixel array section. There are known phase difference detection methods such as the image plane phase difference method in which the phase difference detection pixels for this purpose are arranged and autofocus is performed (see, for example, Patent Documents 1 to 4).

Patent Document 1 describes an imaging device capable of acquiring left and right phase difference information by dividing the center of a photoelectric conversion unit of one pixel by a p-type diffusion layer.

Patent Document 2 describes an imaging device capable of light-shielding either the left or right photoelectric conversion unit of one pixel with metal and acquiring phase difference information from the information of two pixels consisting of a pair of light-shielded left and right pixels.
This image pickup device uses an image of an image signal output from the image sensor to determine a focus adjustment region, which is a target region for focus adjustment in the image sensor, and outputs from pixels in the focus adjustment region. An edge detection means for detecting an edge component of an image based on an image signal output from a signal calculation means, which has a focus adjustment means for performing a phase difference type focus adjustment control based on a pupil-divided image signal. The determination means further determines the region including the region where the edge component is detected as the focus adjustment region.

Patent Document 3 describes a microlens arranged in pixel units on an imaging surface, a pixel unit arranged in pixel units, a color different from that of adjacent pixel units at least in the row direction, and an adjacent pixel unit and a predetermined minimum color array. Each pixel unit has at least a part of the minimum color array, including a color filter that forms a pixel, and a photoelectric conversion region that is arranged in pixel units and photoelectrically converts light transmitted through a microlens and a color filter to generate a pixel signal. The photoelectric conversion region arranged in is biased in a predetermined pupil division direction with respect to the central axis of the passing light beam of the microlens, and the deviation of the photoelectric conversion region is symmetrical between the adjacent pixels of the same color in the minimum color arrangement. The relevant solid-state imaging devices are described.

Patent Document 4 describes a solid-state image sensor capable of acquiring left and right phase difference information by arranging a transparent electrode on the upper part of the accumulation diffusion layer and controlling the potential distribution of the accumulation diffusion layer.
This solid-state imaging device photoelectrically converts the incident light from the subject and generates a charge according to the amount of the incident light, a charge storage region that stores the charge generated in the photoelectric conversion region, and a voltage in the charge storage region. Is provided to modulate the potential for the charge, thereby narrowing the width of the charge storage region and providing a plurality of hybrid pixels having a potential modulation electrode that unevenly distributes the charge storage region.

Japanese Unexamined Patent Publication No. 2012-155095 JP-A-2010-160314 Japanese Unexamined Patent Publication No. 2012-182824 WOA12014-07899

However, the image pickup apparatus described in Patent Documents 1 to 4 has the following disadvantages.

The image pickup apparatus described in Patent Document 1 consumes high power because all pixels simultaneously acquire phase difference information.

In the image pickup apparatus described in Patent Document 2, since the pixel that has acquired the phase difference information has a decrease in sensitivity, it is not possible to read out normal image information, and it is necessary to correct the image information as a defect.

In the solid-state image sensor described in Patent Document 3, since all the color pixels have a Bayer array of 2 × 2 each by deflecting the accumulation and diffusion layer to the left and right, the information on the left and right of the accumulation and diffusion layer is output together. All pixel corrections are needed.

In the solid-state image sensor described in Patent Document 4, it is possible to arrange transparent electrodes on all pixels, but due to high power consumption, it can be developed only on green pixels.

As described above, in the conventional solid-state image sensor as a sensor capable of acquiring phase difference information, it is necessary to change the area of the charge storage region (accumulation diffusion layer) for accumulating the charges generated in the photoelectric conversion region or to shield the light from light. there were.
Therefore, in order to acquire the phase difference information, the loss of saturated charge is large, and it is necessary to reduce the sensitivity and correct the image.
Further, there are disadvantages that the quality of the normal read image is deteriorated and the reading method becomes complicated.

Further, in the conventional solid-state image sensor, there is a limit in suppressing the depletion voltage, and there is a disadvantage that it is difficult to reduce the power consumption.

INDUSTRIAL APPLICABILITY According to the present invention, the depletion voltage can be suppressed without loss of saturated charge while suppressing a decrease in sensitivity, and moreover, low power consumption and highly accurate phase difference information can be acquired without image correction. It is an object of the present invention to provide a solid-state image sensor, a method for manufacturing a solid-state image sensor, and an electronic device capable of improving the image quality without involving a complicated readout method.

The solid-state imaging device according to the first aspect of the present invention has a substrate having a first substrate surface side, a second substrate surface side facing the first substrate surface side, and a first substrate surface side of the substrate. A photoelectric conversion function region that includes a first conductive semiconductor layer formed so as to be embedded between the surface and the surface side of the second substrate, photoelectrically converts incident light, and generates an electric charge according to the amount of incident light, and the photoelectric conversion function. The photoelectric conversion unit includes at least one photoelectric conversion unit that forms a unit pixel having a charge storage function region for accumulating charges generated in the region, and the photoelectric conversion unit includes the photoelectric conversion unit on the surface side of the first substrate on which light is incident. The functional region is arranged, the charge storage functional region is arranged on the second substrate surface side, and at least the photoelectric conversion functional region of the photoelectric conversion functional region and the charge storage functional region is from the central portion of the photoelectric conversion unit. They are staggered.

A second aspect of the present invention is a substrate having a first substrate surface side, a second substrate surface side facing the first substrate surface side, and a first substrate surface side and a second substrate of the substrate. It was generated in the photoelectric conversion functional region and the photoelectric conversion functional region, which includes a first conductive semiconductor layer formed so as to be embedded between the surface side, photoelectrically converts incident light, and generates an electric charge according to the amount of incident light. A method for manufacturing a solid-state imaging device including at least one photoelectric conversion unit that forms a unit pixel having a charge storage function region for accumulating charges, and the light is incident in the step of forming the photoelectric conversion unit. The photoelectric conversion functional region is formed on the surface side of the first substrate, the charge storage functional region is formed on the surface side of the second substrate, and at least the photoelectric conversion functional region of the photoelectric conversion functional region and the charge storage functional region is formed. Is formed so as to be offset from the central portion of the photoelectric conversion portion.

The electronic device according to the third aspect of the present invention includes a solid-state imaging device and an optical system for forming a subject image on the solid-state imaging device, and the solid-state imaging device includes a first substrate surface side and the subject image. A first conductive semiconductor formed so as to be embedded between a substrate having a second substrate surface side facing the first substrate surface side and between the first substrate surface side and the second substrate surface side of the substrate. At least one unit pixel including a layer and having a photoelectric conversion functional region for photoelectrically converting incident light and generating charges according to the amount of incident light and a charge storage functional region for accumulating charges generated in the photoelectric conversion functional region is formed. The photoelectric conversion unit includes two photoelectric conversion units, the photoelectric conversion function region is arranged on the first substrate surface side on which light is incident, and the charge storage function region is arranged on the second substrate surface side. Of the photoelectric conversion functional region and the charge storage functional region, at least the photoelectric conversion functional region is arranged so as to be offset from the central portion of the photoelectric conversion portion.

According to the present invention, the depletion voltage can be suppressed without loss of saturated charge while suppressing the decrease in sensitivity, and the phase difference information with low power consumption and high accuracy can be obtained without image correction. It is possible to acquire the image, and it is possible to improve the image quality without involving a complicated reading method.

It is a block diagram which shows the structural example of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows an example of the unit pixel which concerns on this 1st Embodiment. It is a figure for demonstrating the structural example of the reading system of the column output of the pixel part of the solid-state image sensor which concerns on embodiment of this invention. It is a simplified sectional view which shows the structural example of the embedded type photodiode which forms the unit pixel of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the depletion of the n region (n layer) of a photodiode which is a photoelectric conversion part. It is a figure which shows the structural example of the unit pixel which concerns on 1st Embodiment of this invention. It is a figure which shows an example of the pixel array when the unit pixel is a horizontal unit pixel in this 1st Embodiment. It is a figure which shows an example of the pixel array when the unit pixel is an oblique unit pixel in this 1st Embodiment. It is a simplified sectional view which shows the structural example of the embedded type photodiode which forms the unit pixel of the solid-state image sensor which concerns on 2nd Embodiment of this invention. In the second embodiment, it is a simplified cross-sectional view in a predetermined row of an array example in which horizontal unit pixels are arranged in a matrix as shown in FIG. It is a circuit diagram which shows the structural example of the unit pixel of the solid-state image sensor which concerns on 3rd Embodiment of this invention. It is a figure which shows an example of the pixel array when the unit pixel is a horizontal unit pixel and an oblique unit pixel in this 3rd Embodiment. It is a simplified sectional view which shows the structural example of the embedded type photodiode which forms the unit pixel of the solid-state image sensor which concerns on 4th Embodiment of this invention. It is a circuit diagram which shows an example of the unit pixel of the solid-state image sensor which concerns on 4th Embodiment of this invention. It is a figure which shows the structural example of the unit pixel which concerns on 4th Embodiment of this invention. It is a figure which shows an example of the pixel array when the unit pixel is a vertical unit pixel in this 4th Embodiment. It is a figure which shows an example of the pixel array when the unit pixel is an oblique unit pixel in this 4th Embodiment. It is a simplified sectional view which shows the structural example of the embedded type photodiode which forms the unit pixel of the solid-state image sensor which concerns on 5th Embodiment of this invention. It is a circuit diagram which shows the structural example of the unit pixel of the solid-state image sensor which concerns on 6th Embodiment of this invention. It is a figure which shows an example of the pixel array in the case where the unit pixel is a horizontal unit pixel and an oblique unit pixel in this sixth embodiment. It is a circuit diagram which shows the structural example of the unit pixel of the solid-state image sensor which concerns on 7th Embodiment of this invention. It is a circuit diagram which shows the 1st modification of the unit pixel of the solid-state image sensor which concerns on 7th Embodiment of this invention. It is a circuit diagram which shows the 2nd modification of the unit pixel of the solid-state image sensor which concerns on 7th Embodiment of this invention. It is a circuit diagram which shows the structural example of the unit pixel of the solid-state image sensor which concerns on 8th Embodiment of this invention. It is a circuit diagram which shows the structural example of the unit pixel of the solid-state image sensor which concerns on 9th Embodiment of this invention. It is a circuit diagram which shows the structural example of the global shutter system circuit in the pixel part and the reading part of the solid-state image pickup apparatus which concerns on this 9th Embodiment. It is a figure for demonstrating the laminated structure of the solid-state image sensor which concerns on this 9th Embodiment. It is a timing chart for demonstrating the reading operation mainly in the pixel part in the predetermined shutter mode of the solid-state image pickup apparatus which concerns on 9th Embodiment. It is operation sequence diagram for demonstrating the global shutter reading operation of the solid-state image sensor which concerns on this 9th Embodiment in comparison with rolling shutter reading operation. It is a figure for demonstrating the example of anti-blooming control in the solid-state image sensor which concerns on this 9th Embodiment. It is a block diagram which shows the structural example of the solid-state image sensor which concerns on 10th Embodiment of this invention. It is a figure which shows an example of the digital pixel array of the pixel part of the solid-state image pickup apparatus which concerns on tenth embodiment of this invention. It is a circuit diagram which shows an example of the pixel of the solid-state image sensor which concerns on 10th Embodiment of this invention. It is a figure which shows the structural example of the memory part and the output circuit which concerns on 10th Embodiment of this invention. It is a figure which shows an example of the frame reading sequence in the solid-state image pickup apparatus which concerns on tenth embodiment of this invention. It is a schematic diagram for demonstrating the laminated structure of the solid-state image pickup apparatus which concerns on this tenth embodiment. It is a simplified sectional view for demonstrating the laminated structure of the solid-state image pickup apparatus which concerns on this tenth embodiment. It is a figure which shows an example of the structure of the electronic device to which the solid-state image sensor which concerns on embodiment of this invention are applied.

Hereinafter, embodiments of the present invention will be described in association with the drawings.

(First Embodiment)
FIG. 1 is a block diagram showing a configuration example of a solid-state image sensor according to the first embodiment of the present invention.
In the present embodiment, the solid-state image sensor 10 is composed of, for example, a CMOS image sensor.

As shown in FIG. 1, the solid-state image sensor 10 includes a pixel unit 20 as an image pickup unit, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, and a horizontal scanning circuit (column scanning circuit) 50. , And the timing control circuit 60 as a main component.
Among these components, for example, a vertical scanning circuit 30, a reading circuit 40, a horizontal scanning circuit 50, and a timing control circuit 60 constitute a pixel signal reading unit 70.

In the first embodiment, as will be described in detail later, in the solid-state imaging device 10, the pixels (or the pixel unit 20) arranged in a matrix in the pixel unit 20 are embedded photodiodes as photoelectric conversion units. Has (PPD).
The embedded diode (PPD) of the present embodiment has a first substrate surface side (for example, a back surface side) to be irradiated with light and a second substrate surface side (front surface side) facing the first substrate surface side. It includes a substrate and a first conductive type (for example, n type in this embodiment) semiconductor layer (hereinafter, may be referred to as n layer) formed so as to be embedded in the substrate, and generates an electric charge according to the amount of incident light. It includes at least one photoelectric conversion unit that forms a unit pixel having a photoelectric conversion functional region and a charge storage functional region for accumulating charges generated in the photoelectric conversion functional region.

In the present embodiment, basically, in the photoelectric conversion unit, the photoelectric conversion function region is arranged on the first substrate surface side where light is incident, the charge storage function region is arranged on the second substrate surface side, and the photoelectric conversion function region is arranged. And at least the photoelectric conversion functional region out of the charge storage functional regions is arranged so as to be offset from the central portion of the photoelectric conversion portion.
In the photoelectric conversion unit of the first embodiment, the photoelectric conversion function region and the charge storage function region are arranged so as to be offset from the central portion of the photoelectric conversion unit.
Then, the photoelectric conversion unit is a second conductive type (p type in the present embodiment) semiconductor in a region excluding the photoelectric conversion functional region and the charge storage functional region formed by the first conductive type semiconductor layer (n layer). An isolation region formed by a layer (p-layer) or a backside separation section (eg, BDTI; Backside Deep Trench Isolation) embedded so as to optically shield is arranged.
Further, in the solid-state image sensor 10 of the first embodiment, the solid-state imaging device 10 has a lens portion arranged on the surface side of the second substrate and formed by a microlens that injects light into the photoelectric conversion portion, and the lens portion is optical. The center is arranged so as to be located in the central portion of the photoelectric conversion unit.

As described above, in the solid-state imaging device 10 of the first embodiment, in the photoelectric conversion unit of the embedded diode (PPD), the photoelectric conversion function region and the charge storage function region are arranged so as to be offset from the central portion of the photoelectric conversion unit. Since there is no light-shielding object, the depletion voltage can be suppressed without losing the saturated charge because the photoelectric conversion function region and the charge storage function region are separated while suppressing the decrease in sensitivity. Moreover, since it has a phase difference information acquisition function for each pixel, it is possible to acquire highly accurate phase difference information with low power consumption without image correction, and by extension, image quality can be improved without complicated readout methods. It is possible to improve.

In the present embodiment, the first direction is, for example, the column direction (horizontal direction, X direction), row direction (vertical direction, Y direction), or diagonal direction of the pixel portion 20 in which a plurality of pixels are arranged in a matrix. is there,
In the following description, as an example, the first direction is the column direction (horizontal direction, X direction), and the second direction is the row direction (vertical direction, Y direction).

Hereinafter, the configuration and functions of each part of the solid-state image sensor 10 will be described in detail, and then the configuration of the embedded diode (PPD) part and the readout processing related thereto will be described in detail.

(Structure of pixel unit 20 and unit pixel PXL1)
In the pixel unit 20, a plurality of unit pixels PXL1 including a photodiode (photoelectric conversion element) and an intrapixel amplifier are arranged in a two-dimensional matrix of N rows × M columns.

FIG. 2 is a circuit diagram showing an example of a unit pixel according to the first embodiment.

The unit pixel PXL1 has, for example, a photodiode (PD) which is a photoelectric conversion unit (photoelectric conversion element).
For this photodiode PD, a transfer transistor TG-Tr as a charge transfer gate (transfer element), a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element, and a selection element. Each has one selection transistor SEL-Tr.

The photodiode PD generates and accumulates a signal charge (here, an electron) in an amount corresponding to the amount of incident light.
Hereinafter, the case where the signal charge is an electron and each transistor is an n-type transistor will be described, but the signal charge may be a hole or each transistor may be a p-type transistor.
Further, this embodiment is also effective when each transistor is shared among a plurality of photodiodes or when a 3-transistor (3Tr) pixel having no selection transistor is adopted.

In each unit pixel PXL1, an embedded photodiode (PPD) is used as the photodiode (PD).
Since surface levels due to defects such as dangling bonds exist on the surface of the substrate on which the photodiode (PD) is formed, a large amount of electric charge (dark current) is generated by the thermal energy, and the correct signal cannot be read.
In the embedded photodiode (PPD), by embedding the charge storage function region (charge storage portion) of the photodiode (PD) in the substrate, it is possible to reduce the mixing of dark current into the signal.

A specific configuration example of the photodiode PPD for embedding as a photoelectric conversion unit according to the first embodiment will be described later in connection with the drawings.

The reset transistor RST-Tr is connected between the power supply line VRst and the floating diffusion FD, and is controlled through the control signal RST.
The reset transistor RST-Tr may be connected between the power supply line VDD and the floating diffusion FD and may be configured to be controlled through the control signal RST.
The reset transistor RST-Tr resets the floating diffusion FD to the potential of the power supply line VRst (or VDD) when the control signal RST is selected during the H level period and becomes conductive.

The source follower transistor SF-Tr and the selection transistor SEL-Tr are connected in series between the power supply line VDD and the vertical signal line LSGN.
A floating diffusion FD is connected to the gate of the source follower transistor SF-Tr, and the selection transistor SEL-Tr is controlled through the control signal SEL.
In the selection transistor SEL-Tr, the control signal SEL is selected during the H level period and becomes conductive. As a result, the source follower transistor SF-Tr outputs the read signal VSL (PIXOUT) of the column output, which is obtained by converting the charge of the floating diffusion FD into a voltage signal with a gain corresponding to the amount of charge (potential), to the vertical signal line LSGN.
These operations are performed simultaneously and in parallel for each pixel of one row because, for example, the gates of the transfer transistor TG-Tr, the reset transistor RST-Tr, and the selection transistor SEL-Tr are connected in row units. It is said.

Since the unit pixel PXL1 is arranged in N rows × M columns in the pixel unit 20, there are N lines for each control signal SEL, RST, and TG control lines LSEL, LRST, and LTG, and M lines for each of the vertical signal lines LSGN. ..
In FIG. 1, each control line LSEL, LRST, and LTG is represented as one row scanning control line.

The vertical scanning circuit 30 drives the pixels through the row scanning control lines in the shutter row and the readout row according to the control of the timing control circuit 60.
Further, the vertical scanning circuit 30 outputs a row selection signal of the row address of the read row for reading the signal and the row address of the shutter row for resetting the charge accumulated in the photodiode PD according to the address signal.

As described above, in the normal pixel readout operation, the shutter scan is performed by the vertical scanning circuit 30 of the readout unit 70, and then the readout scan is performed.

The read-out circuit 40 includes a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel unit 20, and even if the plurality of column signal processing circuits are configured to enable column parallel processing. Good.

The readout circuit 40 can be configured to include a Correlated Double Sampling (CDS) circuit, an ADC (analog-to-digital converter; AD converter), an amplifier (AMP, amplifier), a sample hold (S / H) circuit, and the like. Is.

As described above, as shown in FIG. 3A, for example, the read circuit 40 may include an ADC 41 that converts the read signal VSL of each column output of the pixel unit 20 into a digital signal.
Alternatively, as shown in FIG. 3B, for example, the read circuit 40 may include an amplifier (AMP) 42 that amplifies the read signal VSL of each column output of the pixel unit 20.
Further, in the read circuit 40, for example, as shown in FIG. 3C, a sample hold (S / H) circuit 43 that samples and holds the read signal VSL of each column output of the pixel unit 20 may be arranged.

The horizontal scanning circuit 50 scans signals processed by a plurality of row signal processing circuits such as the ADC of the readout circuit 40, transfers them in the horizontal direction, and outputs the signals to a signal processing circuit (not shown).

The timing control circuit 60 generates timing signals necessary for signal processing of the pixel unit 20, the vertical scanning circuit 30, the reading circuit 40, the horizontal scanning circuit 50, and the like.

The configuration and function of each part of the solid-state image sensor 10 according to the first embodiment have been described above.
Next, a specific configuration example and a pixel arrangement example of the embedded photodiode PPD as the photoelectric conversion unit according to the first embodiment will be described.

(Specific configuration example of the embedded photodiode PD)
Here, a specific configuration example of the embedded photodiode PD forming the unit pixel PXL1 of the solid-state image sensor 10 according to the first embodiment will be described with reference to FIG.

FIG. 4 is a simplified cross-sectional view showing a configuration example of an embedded photodiode PD forming a unit pixel PXL1 of the solid-state image sensor according to the first embodiment of the present invention.
Here, the embedded photodiode (PD) portion is represented by reference numeral 200.

The embedded photodiode (PD) portion 200 of FIG. 4 has a first substrate surface 211 side (for example, a back surface side) irradiated with light L and a second substrate surface 212 side facing the first substrate surface 211 side. It has a semiconductor substrate (hereinafter, simply referred to as a substrate) 210 having (front side).
The embedded photodiode portion 200 is a first conductive type (n type in the present embodiment) semiconductor layer (n type in the present embodiment) formed so as to be embedded between the first substrate surface 211 side and the second substrate surface 212 side of the substrate 210. In this embodiment, a photodiode 200 (PD) as a photoelectric conversion unit including an n-layer) 221 and having a photoelectric conversion function region 2211 and a charge storage function region 2212 that photoelectrically convert incident light and generate a charge according to the amount of incident light. ) Is included.

In the present embodiment, basically, the photodiode 200 (PD) as the photoelectric conversion unit has a photoelectric conversion function region 2211 on the side of the first substrate surface 211 on which light is incident in the Z direction, which is a direction perpendicular to the substrate surface. 2212 is arranged on the second substrate surface 212 side, and at least the photoelectric conversion function area 2211 of the photoelectric conversion function area 2211 and the charge storage function area 2212 is a photodiode 200 (PD) which is a photoelectric conversion unit. ) Is arranged so as to be offset from the central part CTpd.
In the photodiode 200 (PD) which is the photoelectric conversion unit of the first embodiment, the photoelectric conversion function region 2211 and the charge storage function region 2212 are displaced from the central CTpd of the photodiode 200 (PD) which is the photoelectric conversion unit. Are arranged.

In the present embodiment, the central portion CTpd of the photodiode 200 (PD), which is the photoelectric conversion unit, refers to the central portion of the photodiode 200 (PD) in the first direction (X direction, width direction).

In the example of FIG. 4, in the photodiode 200 (PD), the n-layer (first conductive semiconductor layer) 221 is the substrate 210 in the first direction (X direction) of the central CTpd and shifted to the right. The photoelectric conversion function region 2211 and the charge storage function region 2212 are formed with the same width so as to have a two-layer structure in the normal direction (Z direction of the Cartesian coordinate system in the drawing).
In this example, the photoelectric conversion function region 2211 by the n-layer is formed on the first substrate surface 211 side, and the charge by the n-layer is formed on the upper layer side (second substrate surface 212 side) of the photoelectric conversion function region 2211 by the n-layer. The storage functional region 2212 is formed.

Then, a p + layer (second conductive semiconductor layer) 222 is formed on the surface of the first substrate surface 211 of the photoelectric conversion function region 2211 by the n-layer, and the charge storage function region 2212 by the n layer is on the second substrate surface 212 side. A p + layer (second conductive semiconductor layer) 223 for suppressing dark current is formed on the surface of the above.

The photodiode 200 (PD), which is a photoelectric conversion unit, has a second conductive type in a region other than the photoelectric conversion functional region 2211 and the charge storage functional region 2212 formed by the first conductive semiconductor layer (n layer). An isolation region 2241 formed by a (p-type) semiconductor layer (p-layer) 224 (in this embodiment) is arranged.
In the example of FIG. 4, an isolation region 2241 is formed not only on the left side portion of the photoelectric conversion function region 2211 and the charge storage function region 2212 but also on the right side portion.

Further, in the solid-state image sensor 10 of the first embodiment, a microlens MCL arranged on the second substrate surface 212 side (back surface side) and incident light on the photodiode 200 (PD) which is a photoelectric conversion unit is used. It has a lens portion 225 to be formed.
The lens unit 225 is arranged so that the optical center OCT of the microlens MCL is located in the central portion CTpd of the photodiode 200 (PD), which is a photoelectric conversion unit.

As described above, in the solid-state imaging device 10 of the first embodiment, in the photodiode 200 (PD) which is the photoelectric conversion unit of the embedded diode (PPD), the photoelectric conversion function region 2211 and the charge storage function region 2212 are Since the photodiode 200 (PD), which is a photoelectric conversion unit, is arranged so as to be offset from the central portion CTpd, the photoelectric conversion function region and the charge storage function region are separated while suppressing a decrease in sensitivity because there is no light-shielding object. Therefore, the depletion voltage can be suppressed without losing the saturated charge, and since the phase difference information acquisition function is provided for each pixel, the phase difference information has low power consumption and high accuracy without image correction. By extension, it is possible to improve the image quality without involving a complicated reading method.

Here, the depletion of the n region (n layer) of the photodiode 200 (PD), which is a photoelectric conversion unit, will be considered.

5 (A) and 5 (B) are diagrams for explaining depletion of the n region (n layer) of the photodiode 200 (PD) which is a photoelectric conversion unit.
FIG. 5 (A) shows a simplified structure of the photodiode 200 (PD), which is a photoelectric conversion unit of an embedded diode (PPD) having a narrow pixel pitch, and FIG. 5 (B) shows an embedded diode having a wide pixel pitch (B). The structure of the photodiode 200 (PD), which is the photoelectric conversion unit of PPD), is shown in a simplified manner.

In general, the n region (n layer) 221 of the photodiode needs to be completely depleted.
The depletion potential (voltage) φ "V" needs to be low enough for complete charge transfer.
The maximum depletion potential needs to be in the vicinity of the transfer transistor TG-Tr as the charge transfer gate.
In order to maximize the storage capacity, it is necessary to maximize the concentration of the n region (n layer) 221 while satisfying the above conditions of the space charge density.
However, if the amount of impurities in the n-layer 221 is increased, the PD potential becomes deeper and the read-out voltage rises, so that there is a limit to increasing the concentration of the n-layer 221.

In general, the following model holds in the p + n junction model.

From this model, the following can be derived.
When focusing on the depletion voltage Vapp required for complete depletion, the lower the depletion voltage Vapp, the lower the power supply voltage of the entire sensor system, which has the advantage of leading to low power consumption. From the above equation, the conditions for lowering the depletion voltage Vapp can be considered in two forms of the following model M1 or model M2.

M1: The photodiode PD is formed so that the depletion layer width (distance) Wd is shortened.
M2: The photodiode PD is formed by lowering the n-layer concentration Nd.

From this model, the following can be derived.
As shown in FIG. 5A, at a narrow pixel pitch, the depletion layer distance Wd in the direction X orthogonal to the normal of the substrate 210 is short, so that the depletion voltage Vapp is lower when the donor concentration Nd is the same.
In other words, when the depletion layer width Wd is short, the depletion voltage Vapp is low, so that the LFWC (Linear Full Well Capacity) is large.
As shown in FIG. 5 (B), when the pixel pitch becomes wide, the depletion voltage Vapp rises, and it becomes difficult to read and deplete at a low voltage.

Therefore, the photoelectric conversion function region 2211 and the charge storage function region 2212 are arranged so as to be offset from the central CTpd of the photodiode 200 (PD) which is the photoelectric conversion unit, thereby shortening the depletion layer width Wd and depleting. The voltage Vapp can be lowered, and the LFWC can be increased, and the second conductive type (p type in the present embodiment) semiconductor layer (p layer) is in the region other than the photoelectric conversion function region 2211 and the charge storage function region 2212. By arranging the isolation region 2241 formed by the 224, it is possible to acquire highly accurate phase difference information with low power consumption without image correction.

As described above, in the solid-state imaging device 10 of the first embodiment, in the photodiode 200 (PD) which is the photoelectric conversion unit of the embedded diode (PPD), the photoelectric conversion function region 2211 and the charge storage function region 2212 are The second conductive type (p-type in the present embodiment) is located in the region other than the photoelectric conversion function region 2211 and the charge storage function region 2212, which is arranged so as to be offset from the central CTpd of the photodiode 200 (PD) which is the photoelectric conversion unit. ) By arranging the isolation region 2241 formed by the semiconductor layer (p-layer) 224, low consumption is suppressed without loss of saturated charge and without image correction while suppressing a decrease in sensitivity. It is possible to acquire highly accurate phase difference information with electric charge, and it is possible to improve the image quality without involving a complicated readout method.

(Arrangement of unit pixels in the pixel unit 20)
Next, an arrangement configuration example and an arrangement example of unit pixels in the pixel unit 20 according to the first embodiment will be described.

6 (A) to 6 (C) are diagrams showing a configuration example of a unit pixel according to the first embodiment of the present invention.
In the pixel unit 20, a plurality of unit pixels PXL1 are arranged in a matrix.
In the first embodiment, the plurality of unit pixels include at least one of a horizontal unit pixel PXL1L, a vertical unit pixel PXL1V, and an oblique unit pixel PXL1D.

As shown in FIG. 6A, the horizontal unit pixels PXL1L are arranged so that the photodiodes 200 (PD), which are photoelectric conversion units including the isolation region 2241, are arranged in parallel in the column direction.

As shown in FIG. 6B, the vertical unit pixels PXL1V are arranged so that the photodiodes 200 (PD), which are photoelectric conversion units including the isolation region 2241, are arranged in parallel in the row direction.

As shown in FIG. 6C, the oblique unit pixel PXL1D is parallel in the oblique direction in which the photodiode 200 (PD), which is a photoelectric conversion unit including the isolation region 2241, has a predetermined angle with respect to the column direction and the row direction. It is arranged so as to be.

7 (A) and 7 (B) are diagrams showing an example of a pixel array in the case where the unit pixel is a horizontal unit pixel in the first embodiment.
FIG. 7 (A) is a diagram showing an example of one arrangement in which horizontal unit pixels are arranged in a matrix of 4 rows and 4 columns, and FIG. 7 (B) is a simplified cross-sectional view taken along line XX of FIG. 7 (A). is there.

In the pixel array ARY20A of FIG. 7, as described above, the unit pixel is formed as a horizontal unit pixel PXL1L, and the photoelectric conversion unit includes an isolation region 2241, a photoelectric conversion function region 2211, and a charge storage function region 2212 for each row. The arrangement position of a certain photodiode 200 (PD) in the row direction is reversed.

Further, as described above, each horizontal unit pixel PXL1L includes a transfer transistor TG-Tr that transfers the charge accumulated in the charge storage function region 2212, and the transfer transistor TG-Tr is photoelectric on the second substrate surface side. It is connected to the charge storage function region 2212 of the photodiode 200 (PD), which is a conversion unit.

Further, the horizontal unit pixel PXL1L is formed in a rectangular shape, the transfer transistor TG-Tr is formed on one edge side, and the plurality of horizontal unit pixels have one edge portion on which the transfer transistor TG-Tr is formed in the array row. , The transfer transistor facing one edge of the horizontal unit pixel PXL1L adjacent in the row direction is arranged so as to face the other edge side on which the transfer transistor is not formed.

FIG. 8 is a diagram showing an example of a pixel array when the unit pixel is an oblique unit pixel in the first embodiment.
FIG. 8 is a diagram showing an example of one arrangement in which horizontal unit pixels are arranged in a matrix of 4 rows and 4 columns.

In the pixel array 20B of FIG. 8, as described above, the unit pixel is formed as an oblique unit pixel PXL1D, and the inclination direction of a predetermined angle between the photodiode 200 (PD), which is a photoelectric conversion unit, and the isolation region 2241 is formed for each row. Is different.

The diagonal unit pixel PXL1D is formed in a rectangular shape, the transfer transistor TG-Tr is formed on one edge side, and the plurality of horizontal unit pixels have one edge on which the transfer transistor TG-Tr is formed in the array row. It is arranged so as to face the other edge side where the transfer transistor facing one edge portion of the diagonal unit pixel PXL1DL adjacent in the row direction is not formed.

As described above, the solid-state imaging device 10 of the first embodiment has a photoelectric conversion function region 2211 and a charge storage function region 2212 in a photodiode 200 (PD) which is a photoelectric conversion unit of an embedded diode (PPD). Is arranged so as to be offset from the central CTpd of the photodiode 200 (PD), which is a photoelectric conversion unit, and a second conductive type (in the present embodiment) is used in a region other than the photoelectric conversion function region 2211 and the charge storage function region 2212. An isolation region 2241 formed by a p-type) semiconductor layer (p-layer) 224 is arranged.
Therefore, according to the solid-state image sensor 10 of the first embodiment, the saturation charge is lost because the photoelectric conversion function region and the charge storage function region are separated while suppressing the decrease in sensitivity because there is no light-shielding object. Since the depletion voltage can be suppressed and the phase difference information acquisition function is provided for each pixel, it is possible to acquire highly accurate phase difference information with low power consumption without image correction. As a result, it is possible to improve the image quality without involving a complicated reading method.

Further, since the photoelectric conversion unit has a photoelectric conversion function region 2211 and a charge storage function region 2212 arranged offset from the central CTpd, and an isolation region 2241 arranged in the remaining region, the unit pixel has a simple structure. It is possible to realize various aspects such as horizontal unit pixel PXL1L, vertical unit pixel PXL1V, diagonal unit pixel PXL1D, and the like according to the specifications.

(Second Embodiment)
FIG. 9 is a simplified cross-sectional view showing a configuration example of an embedded photodiode PD forming the unit pixel PXL2 of the solid-state image sensor according to the second embodiment of the present invention.
FIG. 10 is a simplified cross-sectional view of a predetermined row of an array example in which horizontal unit pixels are arranged in a matrix as shown in FIG. 7 in the second embodiment.

The unit pixel PXL2 of the second embodiment is different from the unit pixel PXL1 of the first embodiment as follows.

In the pixel PXL1 of the first embodiment, the photoelectric conversion function region 2211 and the charge storage function region 2212 are arranged so as to be offset from the central CTpd of the photodiode 200 (PD) which is the photoelectric conversion unit.

On the other hand, in the pixel PXL2 of the second embodiment, the photoelectric conversion function region 2211 is arranged so as to be offset from the central portion CTpd of the photodiode 200 (PD) which is the photoelectric conversion unit, and the charge storage function region 2212 is arranged. The central portion CTam is arranged so as to exist in the central portion CTpd of the photodiode 200 (PD) which is a photoelectric conversion unit.
An isolation region 2241 formed by a second conductive type (p type in the present embodiment) semiconductor layer (p layer) 224 is arranged in a region other than the photoelectric conversion function region 2211 and the charge storage function region 2212. ing.

Other configurations are the same as those of the first embodiment described above, and according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment described above, and a solid with higher sensitivity. It becomes possible to realize an image sensor.

(Third Embodiment)
FIG. 11 is a circuit diagram showing a configuration example of a unit pixel PXL3 of the solid-state image sensor according to the third embodiment of the present invention.
12 (A) and 12 (B) are diagrams showing an example of a pixel array in the case where the unit pixels are horizontal unit pixels and diagonal unit pixels in the third embodiment.

The unit pixel PXL3 of the third embodiment is different from the unit pixel PXL1 of the first embodiment and the unit pixel PXL2 of the second embodiment as follows.

In the unit pixel PXL3 of the third embodiment, the photodiode 200 (PD), which is a photoelectric conversion unit, overflows from the charge storage function region 2212 as shown in FIGS. 11 and 12 (A) and 12 (B). It has an overflow gate transistor OFG-Tr that discharges electric charges.

Other configurations are the same as those of the first embodiment or the second embodiment described above, and according to the third embodiment, the same effects as those of the first embodiment and the second embodiment described above can be obtained. Not only can it be obtained, but it is also possible to acquire phase difference information without blooming, and it is possible to realize a solid-state image sensor that can avoid fluctuations in the saturated charge amount and reduction in area efficiency. It becomes.

(Fourth Embodiment)
FIG. 13 is a simplified cross-sectional view showing a configuration example of an embedded photodiode PD forming the unit pixel PXL4 of the solid-state image sensor according to the fourth embodiment of the present invention.
FIG. 14 is a circuit diagram showing an example of the unit pixel PXL4 of the solid-state image sensor according to the fourth embodiment of the present invention.

The unit pixel PXL4 of the fourth embodiment is different from the unit pixel PXL1 of the first embodiment as follows.

In the unit pixel PXL1 of the first embodiment, one (first) photoelectric conversion function region 2211 and one (first) charge storage function region 2212 are of the photodiode 200 (PD) which is a photoelectric conversion unit. The region is arranged so as to be offset from the central CTpd, and is formed by a second conductive type (p type in this embodiment) semiconductor layer (p layer) 224 in a region other than the photoelectric conversion function region 2211 and the charge storage function region 2212. One (first) isolation region 2241 is arranged.
ing.

On the other hand, in the unit pixel PXL4 of the fourth embodiment, as shown in FIG. 13, the first photoelectric conversion functional region 2211-1 and the first photoelectric conversion functional region 2211-1 that photoelectrically convert the incident light and generate an electric charge according to the amount of the incident light. Photodiode 200-1 (PD1), which is a first photoelectric conversion unit having a first charge storage function region 2212-1 for accumulating charges generated in the first photoelectric conversion function region 2211-1, and incident light A second charge storage function region 2212- that stores the charges generated in the second photoelectric conversion function region 2211-2 and the second photoelectric conversion function region 2211-2, which are photoelectrically converted and generate charges according to the amount of incident light. It is configured to include a photodiode 200-2 (PD2), which is a second photoelectric conversion unit having 2.
In the example of FIG. 13, the photodiode 200-1 (PD1) which is the first photoelectric conversion unit and the photodiode 200-2 (PD2) which is the second photoelectric conversion unit are arranged in parallel and are of the second conductive type. It is separated by a separation layer 201 formed by a semiconductor layer (p layer).

Further, in the unit pixel PXL4 of the fourth embodiment, the photodiode 200-1 (PD1), which is the first photoelectric conversion unit, has the first photoelectric conversion function region 2211-1 and the first charge storage function region 2212. -1 is arranged so as to be offset from the central portion CTpd1 of the photodiode 200-1 (PD1) which is the first photoelectric conversion unit.
Similarly, in the photodiode 200-2 (PD2) which is the second photoelectric conversion unit, the second photoelectric conversion function region 2211-2 and the second charge storage function region 2212-2 are the second photoelectric conversion unit. The photodiode 200 (PD2) is arranged so as to be offset from the central portion CTpd2.

In the present embodiment, as described above, the central portion CTpd1 of the photodiode 200-1 (PD1), which is the first photoelectric conversion unit, is the first direction (X) of the photodiode 200-1 (PD1). The central part in the direction (direction, width direction).
Similarly, the central portion CTpd2 of the photodiode 200-2 (PD2), which is the second photoelectric conversion unit, refers to the central portion of the photodiode 200-2 (PD2) in the first direction (X direction, width direction). ..

In the example of FIG. 13, in the photodiode 200-1 (PD1) which is the first photoelectric conversion unit, the n-layer (first) is shifted to the right in the first direction (X direction) of the central portion CTpd1. (Conductive semiconductor layer) 221 has a two-layer structure in the normal direction of the substrate 210 (Z direction of the Cartesian coordinate system in the drawing). The load storage functional region 2212-1 is formed with the same width.
In this example, the first photoelectric conversion functional region 2211-1 by the n-layer is formed on the first substrate surface 211 side, and the upper layer side (second) of the first photoelectric conversion functional region 2211-1 by the n-layer. A first charge storage function region 2212-1 with n layers is formed on the substrate surface 212 side).

A p + layer (second conductive semiconductor layer) 222-1 is formed on the surface of the first substrate surface 211 of the first photoelectric conversion functional region 2211-1 by the n-layer, and the first charge storage functional region by the n-layer is formed. A p + layer (second conductive semiconductor layer) 223-1 for suppressing dark current is formed on the surface of 2212-1 on the second substrate surface 212 side.

The photodiode 200-1 (PD1), which is the first photoelectric conversion unit, has the first photoelectric conversion functional region 2211-1 and the first charge storage formed by the first conductive semiconductor layer (n layer). An isolation region 2241-1 formed by a second conductive type (p type in this embodiment) semiconductor layer (p layer) 224 is arranged in a region other than the functional region 2212-1.
In the p-type isolation region 2241-1, backside separation is performed using a ferroelectric substance such as TaO having a high refractive index or a material having a high shielding effect such as polysilicon in order to improve the optical isolation characteristics. Part 201-1 is embedded.

Similarly, in the photodiode 200-2 (PD2), which is the second photoelectric conversion unit, the n-layer (first conductive semiconductor) is shifted to the left in the first direction (X direction) of the central portion CTpd2. The second photoelectric conversion function region 2211-2 and the second load storage function so that the layer) 221 has a two-layer structure in the normal direction of the substrate 210 (Z direction of the Cartesian coordinate system in the drawing). Regions 2212-2 are formed with the same width.
In this example, the second photoelectric conversion functional region 2211-2 by the n-layer is formed on the first substrate surface 211 side, and the upper layer side (second) of the second photoelectric conversion functional region 2211-2 by the n-layer. A second charge storage function region 2212-2 with n layers is formed on the substrate surface 212 side).

A p + layer (second conductive semiconductor layer) 222-2 is formed on the surface of the first substrate surface 211 of the second photoelectric conversion functional region 2211-2 by the n-layer, and the second charge storage functional region by the n-layer is formed. A p + layer (second conductive semiconductor layer) 223-2 for suppressing dark current is formed on the surface of 2212-2 on the second substrate surface 212 side.

The photodiode 200-2 (PD2), which is the second photoelectric conversion unit, has the second photoelectric conversion functional region 2211-2 and the first charge storage formed by the first conductive semiconductor layer (n layer). An isolation region 2241-2 formed by a second conductive type (p type in this embodiment) semiconductor layer (p layer) 224 is arranged in a region other than the functional region 2212-2.
In the p-type isolation region 2241-2, backside separation is performed using a ferroelectric substance such as TaO having a high refractive index or a material having a high shielding effect such as polysilicon in order to improve the optical isolation characteristics. Part 201-2 is embedded.

Further, in the solid-state image sensor 10C of the fourth embodiment, the photodiode 200-1 (PD1) and the second photoelectric conversion unit, which are arranged on the second substrate surface 212 side (back surface side) and are the first photoelectric conversion unit, are used. It has a lens unit 225C formed by a microlens MCL4 that injects light into a photodiode 200-2 (PD2) that is a photoelectric conversion unit.
The lens unit 225C is composed of a photodiode 200-1 (PD1), which is a first photoelectric conversion unit, and a second photoelectric conversion unit, in which the optical center OCT4 of the microlens MCL4 is arranged in parallel with the separation layer 201 interposed therebetween. It is arranged so as to exist in the central portion CTbdr of the boundary region of a photodiode 200-2 (PD2).

As described above, the solid-state imaging device 10C of the fourth embodiment has the first photoelectric conversion function region 2211-1 and the first photoelectric conversion function that photoelectrically convert the incident light and generate an electric charge according to the amount of the incident light. Photodiode 200-1 (PD1), which is a first photoelectric conversion unit having a first charge storage function region 2212-1 for accumulating charges generated in the region 2211-1, and incident light are photoelectrically converted, and the amount of incident light is achieved. A second having a second photoelectric conversion functional region 2211-2 for generating charges according to the above and a second charge storage functional region 2212-2 for accumulating charges generated in the second photoelectric conversion functional region 2211-2. It includes a photodiode 200-2 (PD2) which is a photoelectric conversion unit, and a photodiode 200-1 (PD1) which is a first photoelectric conversion unit and a photodiode 200-2 (PD2) which is a second photoelectric conversion unit. ) Are arranged in parallel and separated by a separation layer 201 formed by a second conductive semiconductor layer (p layer).
Therefore, according to the third embodiment, it is possible to acquire highly accurate phase difference information with low power consumption without loss of saturated charge and without image correction while suppressing a decrease in sensitivity. As a result, it is possible to improve the image quality without involving a complicated reading method.

(Arrangement of unit pixels in pixel unit 20C)
Next, an arrangement configuration example and an arrangement example of unit pixels in the pixel unit 20C according to the fourth embodiment will be described.

15 (A) to 15 (C) are diagrams showing a configuration example of a unit pixel according to a fourth embodiment of the present invention.
In the pixel unit 20C, a plurality of unit pixels PXL4 are arranged in a matrix.
In the fourth embodiment, the plurality of unit pixels include at least one of a horizontal unit pixel PXL4L, a vertical unit pixel PXL4V, and an oblique unit pixel PXL4D.

As shown in FIG. 15A, the horizontal unit pixel PXL4L includes a photodiode 200-1 (PD1) which is a first photoelectric conversion unit including a first isolation region 2241-1, and a second iso. The photodiode 200-2 (PD2), which is the second photoelectric conversion unit including the isolation region 2241-2, is arranged so as to be parallel in the column direction.

As shown in FIG. 15B, the vertical unit pixel PXL4V includes a photodiode 200-1 (PD1) which is a first photoelectric conversion unit including a first isolation region 2241-1, and a second iso. The photodiode 200-2 (PD2), which is the second photoelectric conversion unit including the isolation region 2241-2, is arranged so as to be parallel in the row direction.

As shown in FIG. 15C, the oblique unit pixel PXL4D includes a photodiode 200-1 (PD1) which is a first photoelectric conversion unit including a first isolation region 2241-1, and a second iso. The photodiode 200-2 (PD2), which is the second photoelectric conversion unit including the isolation region 2241-2, is arranged in parallel in the oblique direction having a predetermined angle with respect to the column direction and the row direction.

The photodiode 200-1 (PD1), which is the first photoelectric conversion unit, includes a first transfer transistor TG1-Tr that transfers the charge stored in the first charge storage function region 2212-1. The first transfer transistor TG1-Tr is connected to the first charge storage function region 2212-1 of the photodiode 200-1 (PD1), which is the first photoelectric conversion unit, on the second substrate surface 212 side. ..
The photodiode 200-2 (PD2), which is the second photoelectric conversion unit, includes a second transfer transistor TG2-Tr that transfers the accumulated charge in the second charge storage function region 2212-2. The second transfer transistor TG2-Tr is connected to the second charge storage function region 2212-2 of the photodiode 200-2 (PD2), which is the second photoelectric conversion unit, on the second substrate surface 212 side. ..

Then, in this example, each unit pixel is formed as a vertical unit pixel PXL3L as described above, and in the vertical unit pixel PXL3D, the first transfer transistor TG1-Tr and the second transfer transistor TG2-Tr are separated. The layers 201 are arranged so as to face each other with the layer 201 in between.

16A and 16B are diagrams showing an example of a pixel array in the case where the unit pixel is a vertical unit pixel in the fourth embodiment.
FIG. 16 (A) is a diagram showing an example of one arrangement in which vertical unit pixels are arranged in a matrix of 4 rows and 4 columns, and FIG. 16 (B) is a simplified cross-sectional view taken along the line YY of FIG. 16 (A). is there.

In the pixel array 20C of FIG. 16, as described above, each vertical unit pixel PXL4V includes a transfer transistor TG1-Tr that transfers the charge stored in the charge storage function region 2212-1, and the transfer transistor TG1-Tr includes the transfer transistor TG1-Tr. On the surface side of the second substrate, it is connected to the charge storage function region 2212-1 of the photodiode 200-1 (PD1), which is a photoelectric conversion unit.
Further, each vertical unit pixel PXL4V includes a transfer transistor TG2-Tr that transfers the charge accumulated in the charge storage function region 2212-2, and the transfer transistor TG2-Tr is a photoelectric conversion unit on the second substrate surface side. It is connected to the charge storage function region 2212-2 of a photodiode 200-2 (PD2).
Each vertical unit pixel PXL4V is arranged such that the first transfer transistor TG1-Tr and the second transfer transistor TG2-Tr are close to each other and face each other.

FIG. 17 is a diagram showing an example of a pixel array when the unit pixel is an oblique unit pixel in the fourth embodiment.
FIG. 17 is a diagram showing an example of one arrangement in which diagonal unit pixels are arranged in a matrix of 4 rows and 4 columns.

In the pixel array 20C of FIG. 17, as described above, the unit pixel is formed as an oblique unit pixel PXL4D, and the inclination direction of a predetermined angle between the photodiode 200 (PD), which is a photoelectric conversion unit, and the isolation region 2241 is formed for each row. Is different.

The diagonal unit pixel PXL1D is formed in a rectangular shape, and even in each diagonal unit pixel PXL4D, the first transfer transistor TG1-Tr and the second transfer transistor TG2-Tr are arranged so as to be close to each other and face each other.

As described above, in the solid-state image sensor 10C of the fourth embodiment, the photodiode 200-1 (PD1), which is the first photoelectric conversion unit, has the first photoelectric conversion functional region 2211-1 and the first. The charge storage function region 2212-1 of the above is arranged so as to be offset from the central portion CTpd1 of the photodiode 200-1 (PD1) which is the first photoelectric conversion unit, and the photodiode 200-2 (photodiode 200-2) which is the second photoelectric conversion unit is arranged. In PD2), the second photoelectric conversion function region 2211-2 and the second charge storage function region 2212-2 are arranged so as to be offset from the central portion CTpd2 of the photodiode 200 (PD2) which is the second photoelectric conversion unit. ing.
The photodiode 200-1 (PD1), which is the first photoelectric conversion unit, has the first photoelectric conversion functional region 2211-1 and the first charge storage formed by the first conductive semiconductor layer (n layer). An isolation region 2241-1 formed by a second conductive type (p type in this embodiment) semiconductor layer (p layer) 224 is arranged in a region other than the functional region 2212-1.
Also in this case, in the p-type isolation region 2241-1, in order to improve the optical isolation characteristics, the backside is made of a ferroelectric substance such as TaO having a high refractive index or a material having a high shielding effect such as polysilicon. Separation section 201-1 is embedded.
Similarly, the photodiode 200-2 (PD2), which is the second photoelectric conversion unit, has the second photoelectric conversion functional region 2211-2 and the first charge formed by the first conductive semiconductor layer (n layer). An isolation region 2241-2 formed by a second conductive type (p type in the present embodiment) semiconductor layer (p layer) 224 is arranged in a region other than the storage function region 2212-2.
Similarly, in this case, in the p-type isolation region 2241-2, in order to improve the optical isolation characteristics, a ferroelectric substance such as TaO having a high refractive index or a material having a high shielding effect such as polysilicon is used. The backside separation portion 201-2 is embedded.

Therefore, according to the solid-state image sensor 10C of the fourth embodiment, the phase difference with low power consumption and high accuracy is suppressed without a decrease in sensitivity, without loss of saturated charge, and without image correction. It is possible to acquire information, and by extension, it is possible to improve the image quality without involving a complicated reading method.

Further, the photoelectric conversion function region 2211-1 and the charge storage function region 2212-1, the photoelectric conversion function region 2211-2, the charge storage function region 2212-2, and the remaining region in which the photoelectric conversion unit is arranged so as to be offset from the central CTpd. Since the isolation regions 2241-1,2241-2 are arranged in, it is possible to realize a unit pixel with a simple structure, and specifications such as horizontal unit pixel PXL4L, vertical unit pixel PXL4V, and diagonal unit pixel PXL4D, etc. Various aspects are possible according to the above.

(Fifth Embodiment)
FIG. 18 is a simplified cross-sectional view showing a configuration example of an embedded photodiode PD forming a unit pixel PXL5 of the solid-state imaging device according to the fifth embodiment of the present invention.

The unit pixel PXL5 of the fifth embodiment is different from the unit pixel PXL4 of the fourth embodiment as follows.

In the pixel PXL4 of the fourth embodiment, the photodiode 200-1 (PD1), which is the first photoelectric conversion unit, has the first photoelectric conversion function region 2211-1 and the first charge storage function region 2212-1. , The photodiode 200-2 (PD2), which is the second photoelectric conversion unit, is arranged so as to be offset from the central portion CTpd1 of the photodiode 200-1 (PD1), which is the first photoelectric conversion unit. The functional region 2211-2 and the second charge storage functional region 2212-2 are arranged so as to be offset from the central portion CTpd2 of the photodiode 200 (PD2), which is the second photoelectric conversion unit.

On the other hand, in the pixel PXL5 of the fifth embodiment, the first photoelectric conversion function region 2211-1 is shifted from the central portion CTpd1 of the photodiode 200-1 (PD1) which is the first photoelectric conversion unit. The first charge storage function region 2212-1 is arranged so as to exist in the central portion CTpd1 of the photodiode 200-1 (PD1) which is the first photoelectric conversion unit.
The photodiode 200-1 (PD1), which is the first photoelectric conversion unit, has the first photoelectric conversion functional region 2211-1 and the first charge storage formed by the first conductive semiconductor layer (n layer). An isolation region 2241-1 formed by a second conductive type (p type in this embodiment) semiconductor layer (p layer) 224 is arranged in a region other than the functional region 2212-1.
Similarly, the second photoelectric conversion function region 2211-2 is arranged so as to be offset from the central portion CTpd2 of the photodiode 200-2 (PD2), which is the second photoelectric conversion portion, and the second charge storage function region 2212- 2 is arranged so as to exist in the central portion CTpd2 of the photodiode 200-2 (PD2) which is the second photoelectric conversion unit.
The photodiode 200-2 (PD2), which is the second photoelectric conversion unit, has the second photoelectric conversion functional region 2211-2 and the first charge storage formed by the first conductive semiconductor layer (n layer). An isolation region 2241-2 formed by a second conductive type (p type in this embodiment) semiconductor layer (p layer) 224 is arranged in a region other than the functional region 2212-2.

Other configurations are the same as those of the fourth embodiment described above, and according to the fifth embodiment, it is possible to obtain the same effects as those of the fourth embodiment described above, and a solid with higher sensitivity. It becomes possible to realize an image sensor.

(Sixth Embodiment)
FIG. 19 is a circuit diagram showing a configuration example of a unit pixel PXL6 of the solid-state image sensor according to the sixth embodiment of the present invention.
20 (A) and 20 (B) are diagrams showing an example of a pixel array in the case where the unit pixels are horizontal unit pixels and diagonal unit pixels in the sixth embodiment.

The unit pixel PXL6 of the sixth embodiment is different from the unit pixel PXL4 of the fourth embodiment and the unit pixel PXL5 of the fifth embodiment as follows.

In the unit pixel PXL6 of the sixth embodiment, the photodiode 200-1 (PD1) which is the first photoelectric conversion unit and the photodiode 200-2 (PD2) which is the second photoelectric conversion unit are shown in FIG. Further, as shown in FIGS. 20 (A) and 20 (B), the first overflow gate transistor OFG1-Tr and the second overflow gate transistor OFG2- that discharge the charge overflowing from the charge storage function region 2212-1,2122-2. It has a Tr.

Other configurations are the same as those of the fourth or fifth embodiment described above, and according to the sixth embodiment, the same effects as those of the fourth and fifth embodiments described above can be obtained. Not only can it be obtained, but it is also possible to acquire phase difference information without blooming, and it is possible to realize a solid-state image sensor that can avoid fluctuations in the saturated charge amount and reduction in area efficiency. It becomes.

(7th Embodiment)
FIG. 21 is a circuit diagram showing a configuration example of a unit pixel PXL7 of the solid-state image sensor according to the seventh embodiment of the present invention.

The unit pixel PXL7 of the seventh embodiment is different from the unit pixel PXL4 of the fourth embodiment and the unit pixel PXL5 of the fifth embodiment as follows.

In the unit pixel PXL7 of the seventh embodiment, a binning transistor (binning switch) BIN-Tr is connected between the floating diffusion FD, which is an output node, and the reset transistor RST-Tr, and binning. By turning the transistor BIN-Tr on and off, the capacitance of the floating diffusion FD is made variable, and the conversion gain of the floating diffusion FD is switched.

In this example, for example, when the control signal BIN is at a low level and the first binning transistor BIN-Tr is in the off state, the conversion gain becomes a high conversion gain (High).
In this case, the gate capacitance C0 of the source follower transistor SF-Tr, the interwiring capacitance C1 between the contact wirings, the junction capacitance C2 in the n + diffusion layer forming the floating diffusion FD, and the capacitance Cfd of the floating diffusion FD of the pixel PXL to be read. The inter-wiring capacitance C3 between the metal wirings is added up and added as an additional capacitance Cbin1 (= C0 + C1 + C2 + C3).
The first total capacitance of the floating diffusion FD in the case of this high conversion gain is Cbin1.

On the other hand, when the control signal BIN is at a high level and the first binning transistor BIN-Tr is in the ON state, the conversion gain becomes a low conversion gain (Low).
In this case, the capacitance Cfd of the floating diffusion FD of the pixel PXL to be read, the gate capacitance C0 of the source follower transistor SF-Tr, the interwiring capacitance C1 between the contact wirings, the junction capacitance C2 in the n + diffusion layer forming the floating diffusion FD, and the like. The inter-wiring capacitance C3 between the metal wirings is added up, and in addition to the additional capacitance Cbin1 (= C0 + C1 + C2 + C3), the gate capacitance C4 of the binning transistor BIN-Tr and the inter-wiring capacitance C5 between the other metal wirings are added up. It is added as an additional capacity Cbin2 (= C4 + C5).
The second total capacitance of the floating diffusion FD in the case of this low conversion gain is Cbin1 + Cbin2.

In the seventh embodiment, the reading unit 70 reads out the pixel signal with the first conversion gain corresponding to the first total capacitance set by the capacitance variable unit (not shown) in one reading period. The conversion gain mode read of the pixel signal and the pixel signal are read with the second conversion gain corresponding to the second total capacity (different from the first total capacity) set by the capacitance variable unit. And, it is configured to be possible to do.
That is, in the solid-state image sensor 10F of the seventh embodiment, for the charge (electrons) photoelectrically converted in one storage period (exposure period), the first reading period is performed inside the pixel. It is provided as a solid-state image sensor with a wide dynamic range that outputs a signal by switching between a conversion gain (for example, high conversion gain) mode and a second conversion gain (low conversion gain) mode and outputs both a bright signal and a dark signal. ..

(First modification)
FIG. 22 is a circuit diagram showing a first modification of the unit pixel PXL7 of the solid-state image sensor according to the seventh embodiment of the present invention.

In the first modification, the reset element is shared by all the pixels in one row ... PXLn-1, PXLn, PXLn + 1, ... For example, the pixel PXL0 on one end side of one row (not shown in FIG. 22). The floating diffusion FD and the power supply line VDD (not shown in FIG. 22) formed in the vicinity of the pixel PXLN-1 on the other end side of one row are connected to the wiring WR in a longitudinal manner corresponding to each pixel. NDn-1, NDn, which are connected via BINn-1-Tr, BINn-Tr, BINn + 1-Tr, and the nodes on the wiring WR between the binning switches. , NDn + 1 ... and the corresponding pixels ... PXLn-1, PXLn, PXLn + 1 ... Floating diffusion FDs are connected.
In the first embodiment, the binning transistor (switch) BIN (N-1) -Tr, which is the farthest end side (not shown), functions as a shared reset element.

With such a configuration, according to the first modification, the number of connections of the floating diffusion FD can be flexibly switched, and the dynamic range is excellently expandable. Further, since the number of transistors in the pixel is small, the PD aperture ratio can be increased, and the photoelectric conversion sensitivity and the number of saturated electrons can be increased.

(Second modification)
FIG. 23 is a circuit diagram showing a second modification of the unit pixel PXL7 of the solid-state image sensor according to the seventh embodiment of the present invention.

The difference between the second modification and the first modification of FIG. 22 is as follows.
In this second modification, the first binning transistors (binning switches) BIN1n-1-Tr, 81n-Tr, and BIN1n + 1-Tr are connected vertically on the wiring WR and formed so as to correspond to each pixel. In addition, a second binning transistor (binning switch) formed by, for example, an NMOS transistor between the floating diffusion FD of each pixel PXLn-1, PXLn, PXLn + 1 and the nodes NDn-1, NDn, NDn + 1 of the wiring WR. BIN2n-1-Tr, BIN2n-Tr, and BIN2n + 1-Tr are connected.

The first binning transistor BIN1n-1-Tr, BINn-Tr, and BIN1n + 1-Tr are selectively turned on and off by the first capacitance change signals BIN1n-1, BIN1n, and BIN1n + 1, respectively, and the second binning transistor BIN2n-1- Tr, BIN2n-Tr, and BIN2n + 1-Tr are selectively turned on and off by the second capacitance change signals BIN2n-1, BIN2n, and BIN2n + 1, respectively.
In this example, as shown in FIG. 23, the first capacitance change signal BIN1n-1, BIN1n, BIN1n + 1 and the second capacitance change signal BIN2n-1, BIN2n, BIN2n + 1 form a pair and form a pair at the same timing (in phase). ) Switch between H level and L level.

In such a configuration, the first binning transistors BIN1n-1-Tr, BINn-Tr, and BIN1n + 1-Tr are used for connecting and disconnecting the adjacent FD wiring WR.
The second binning transistors BIN2n-1-Tr, BIN2n-Tr, and BIN2n + 1-Tr are arranged in the vicinity of the transfer transistor TG-Tr of each pixel PXLn-1, PXLn, and PXLn + 1, and in the high conversion gain mode, the floating diffusion FD. It is used to minimize the parasitic capacitance of the node.

(8th Embodiment)
FIG. 24 is a circuit diagram showing a configuration example of the unit pixel PXL8 of the solid-state image sensor according to the eighth embodiment of the present invention.

The unit pixel PXL8 of the eighth embodiment is different from the unit pixel PXL6 of the unit pixel PXL6 of the sixth embodiment as follows.

In the unit pixel PXL8 of the eighth embodiment, as in the seventh embodiment, the binning transistor (binning switch) BIN-between the floating diffusion FD which is the output node and the reset transistor RST-Tr. A Tr is connected, and by turning on and off the binning transistor BIN-Tr, the capacitance of the floating diffusion FD is made variable, and the conversion gain of the floating diffusion FD is switched.

Also in this example, for example, when the control signal BIN is at a low level and the first binning transistor BIN-Tr is in the off state, the conversion gain becomes a high conversion gain (High).
In this case, the gate capacitance C0 of the source follower transistor SF-Tr, the interwiring capacitance C1 between the contact wirings, the junction capacitance C2 in the n + diffusion layer forming the floating diffusion FD, and the capacitance Cfd of the floating diffusion FD of the pixel PXL to be read. The inter-wiring capacitance C3 between the metal wirings is added up and added as an additional capacitance Cbin1 (= C0 + C1 + C2 + C3).
The first total capacitance of the floating diffusion FD in the case of this high conversion gain is Cbin1.

On the other hand, when the control signal BIN is at a high level and the first binning transistor 81 is in the ON state, the conversion gain becomes a low conversion gain (Low).
In this case as well, the capacitance Cfd of the floating diffusion FD of the pixel PXL to be read, the gate capacitance C0 of the source follower transistor SF-Tr, the interwiring capacitance C1 between the contact wirings, and the junction capacitance C2 in the n + diffusion layer forming the floating diffusion FD. In addition to the additional capacitance Cbin1 (= C0 + C1 + C2 + C3), the gate capacitance C4 of the binning transistor BIN-Tr and the inter-wiring capacitance C5 between other metal wirings are added together. It is added as an additional capacity Cbin2 (= C4 + C5).
The second total capacitance of the floating diffusion FD in the case of this low conversion gain is Cbin1 + Cbin2.

It should be noted that also in the eighth embodiment, it is possible to apply the modified examples shown in FIGS. 22 and 23.

(9th Embodiment)
FIG. 25 is a circuit diagram showing a configuration example of a unit pixel PXL9 of the solid-state image sensor according to the ninth embodiment of the present invention.

In the ninth embodiment, the solid-state image sensor 10H includes a photoelectric conversion reading unit and a signal holding unit as a unit pixel PXL9 in the pixel unit 20H, has a global shutter operation function, and has a substantially wide dynamic range. , For example, it is configured as a stacked CMOS image sensor, which makes it possible to realize a high frame rate.

In the solid-state imaging device 10H according to the ninth embodiment, as will be described in detail later, a pixel signal is sampled simultaneously and in parallel by all pixels in a signal holding unit as a pixel signal storage in a voltage mode. The conversion signal corresponding to the read signal held in the first to fourth signal holding capacitors is read out to a predetermined signal line, and the conversion signal corresponding to the read reset signal is read out simultaneously and in parallel to the predetermined signal line to read the column. Supply to circuit 40.

Hereinafter, the configuration and function of the pixel unit 20H of the solid-state image sensor 10H, the readout processing related thereto, the laminated structure of the pixel portion 20H and the readout unit 70, and the like will be described in detail.

(Structure of unit pixel PXL9 and pixel unit 20H)
As shown in FIG. 25, the pixel 200H arranged in the pixel unit 20H includes a photoelectric conversion reading unit 230 and a signal holding unit 240.
As will be described in detail later, the pixel portion 20H of the ninth embodiment is configured as a laminated CMOS image sensor of the first substrate 110 and the second substrate 120, but in this example, FIG. 25 As shown in the above, a photoelectric conversion reading unit 230 is formed on the first substrate 110, and a signal holding unit 240 is formed on the second substrate 120.

The photoelectric conversion reading unit 230 of the pixel 200 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.
In the example of FIG. 25, as an example, the photoelectric conversion reading unit 230 employs the unit pixel PXL7-1 of the first modification of the unit pixel PXL7 according to the seventh embodiment of FIG. 22.

Specifically, the photoelectric conversion reading unit 230 includes a first photodiode PD1 (200-1) which is a first photoelectric conversion unit and a photodiode PD2 (200-2) which is a second photoelectric conversion unit. Have.
The first photodiode PD1 has a first transfer transistor TG1-Tr and a first overflow gate transistor OFG1-Tr as transfer elements.
The second photodiode PD2 has a second transfer transistor TG2-Tr and a second overflow gate transistor OFG2-Tr as transfer elements.
Then, the reset transistor RST1-Tr as the reset element, the source follower transistor SF1-Tr as the source follower element, the current transistor IC1-Tr as the current source element, the binning transistor BIN1-Tr, and the floating diffusion FD1 as the output node ND1. , And one read node ND2 each.

Then, in the ninth embodiment, the output buffer unit 231 includes the source follower transistor SF1-Tr, the current transistor IC1-Tr, and the read node ND2.

In the photoelectric conversion reading unit 230H according to the ninth embodiment, the reading node ND2 of the output buffer unit 231 is connected to the input unit of the signal holding unit 240.
The photoelectric conversion reading unit 230 converts the electric charge of the floating diffusion FD1 as an output node into a voltage signal according to the amount of electric charge, and outputs the converted voltage signal VSL to the signal holding unit 240.

Further, the photoelectric conversion reading unit 230 outputs a voltage signal VSL corresponding to the stored charges of the photodiodes PD1 and PD2 transferred to the floating diffusion FD1 as an output node during the transfer period PT after the storage period PI.
The photoelectric conversion reading unit 230 outputs a reading reset signal (signal voltage) (VRST) and a reading signal (signal voltage) (VSIG) as pixel signals to the signal holding unit 240.

The reset transistor RST1-Tr is connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion FD1 via a binning transistor, and is controlled by a control signal RST applied to the gate through the control line.
In the reset transistor RST1-Tr, the control signal RST is selected during the H level reset period and becomes conductive, and the floating diffusion FD1 is reset to the potential of the power supply line Vdd of the power supply voltage VDD.

In the source follower transistor SF1-Tr as the source follower element, the source is connected to the read node ND2, the drain side is connected to the power supply line Vdd, and the gate is connected to the floating diffusion FD1.
The drain and source of the current transistor IC1-Tr as a current source element are connected between the read node ND2 and the reference potential VSS (for example, GND). The gate of the current transistor IC1-Tr is connected to the supply line of the control signal VBNPIX.
Then, the signal line LSGN1 between the read node ND2 and the input unit of the signal holding unit 240 is driven by the current transistor IC1-Tr as a current source element.

The signal holding unit 240 of the pixel 200H basically includes an input unit 241 including an input node ND22, a sample holding unit 242, a first output unit 243, a second output unit 244, a third output unit 245, and a fourth. 246, and the holding nodes ND23, ND24, ND25, and ND26 are included.

The input unit 241 is connected to the read node ND2 of the photoelectric conversion read unit 230 via the signal line LSGN1, and inputs the read signal (VSIG1) and the read reset signal (VRST1) output from the read node ND2 to the sample hold unit 242. To do.

The sample hold unit 242 includes a first sampling transistor SHR1-Tr as a first switch element, a second sampling transistor SHS1-Tr as a second switch element, and a third sampling transistor as a third switch element. SHR2-Tr, fourth sampling transistor SHS2-Tr as a fourth switch element, first signal holding capacitor CR21, second signal holding capacitor CS21, third signal holding capacitor CR22, fourth signal holding capacitor It is configured to include CS22.

The first sampling transistor SHR1-Tr is connected between the input node ND22 and the holding node ND23 connected to the signal line LSGN1.
The first sampling transistor SHR1-Tr sets the first signal holding capacitor CR21 of the sample holding unit 242 to the reading node of the photoelectric conversion reading unit 230 via the holding node ND23 during the global shutter period or the clearing period of the signal holding capacitor. Selectively connect to ND2.
In the first sampling transistor SHR1-Tr, for example, the control signal SHR1 is in a conductive state during a high level period.
The first signal holding capacitor CR21 is connected between the holding node ND23 and the reference potential VSS.

The second sampling transistor SHS1-Tr is connected between the input node ND22 and the holding node ND24 connected to the signal line LSGN1.
The second sampling transistor SHS1-Tr sets the second signal holding capacitor CS21 of the sample holding unit 242 to the reading node of the photoelectric conversion reading unit 230 via the holding node ND24 during the global shutter period or the clearing period of the signal holding capacitor. Selectively connect to ND2.
In the second sampling transistor SHS1-Tr, for example, the control signal SHS1 becomes conductive during a high level period.
The second signal holding capacitor CS21 is connected between the holding node ND24 and the reference potential VSS.

The third sampling transistor SHR2-Tr is connected between the input node ND22 and the holding node ND25 connected to the signal line LSGN1.
The third sampling transistor SHR2-Tr connects the third signal holding capacitor CR22 of the sample holding unit 242 to the reading node of the photoelectric conversion reading unit 230 via the holding node ND25 during the global shutter period or the clearing period of the signal holding capacitor. Selectively connect to ND2.
In the third sampling transistor SHR2-Tr, for example, the control signal SHR2 becomes conductive during a high level period.
The third signal holding capacitor CR22 is connected between the holding node ND25 and the reference potential VSS.

The fourth sampling transistor SHS2-Tr is connected between the input node ND22 and the holding node ND26 connected to the signal line LSGN1.
The fourth sampling transistor SHS2-Tr connects the fourth signal holding capacitor CS22 of the sample holding unit 242 to the reading node of the photoelectric conversion reading unit 230 via the holding node ND26 during the global shutter period or the clearing period of the signal holding capacitor. Selectively connect to ND2.
In the fourth sampling transistor SHS2-Tr, for example, the control signal SHS2 becomes conductive during a high level period.
The fourth signal holding capacitor CS22 is connected between the holding node ND26 and the reference potential VSS.

The first sampling transistor SHR1-Tr, the second sampling transistor SHS1-Tr, the third sampling transistor SHR2-Tr, and the fourth sampling transistor SHS2-Tr are MOS transistors, for example, p-channel MOS (MOSFET). Formed by transistors.

The first output unit 243 basically outputs the signal held by the first signal holding capacitor CR21 according to the holding voltage during the global shutter period. The source follower transistor SF2R-Tr as the second source follower element. The retained signal is selectively output to the vertical signal line LSGN11 via the selection transistor SEL1R-Tr.

The source follower transistor SF2R-Tr and the selection transistor SEL1R-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN11.

The holding node ND23 is connected to the gate of the source follower transistor SF2R-Tr, and the selection transistor SEL1R-Tr is controlled by the control signal SEL1 applied to the gate through the control line.
In the selection transistor SEL1R-Tr, the control signal SEL1 is selected during the H level selection period and becomes conductive. As a result, the source follower transistor SF2R-Tr outputs the read-out voltage (VRST) of the column output corresponding to the holding voltage of the first signal holding capacitor CR21 to the vertical signal line LSGN11.

The second output unit 244 basically outputs the signal held by the second signal holding capacitor CS21 according to the holding voltage during the global shutter period. The source follower transistor SF3S-Tr as the third source follower element. The retained signal is selectively output to the vertical signal line LSGN12 via the selection transistor SEL2S-Tr.

The source follower transistor SF3S-Tr and the selection transistor SEL2S-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN12.

The holding node ND24 is connected to the gate of the source follower transistor SF3S-Tr, and the selection transistor SEL2S-Tr is controlled by the control signal SEL1 applied to the gate through the control line.
In the selection transistor SEL2S-Tr, the control signal SEL1 is selected during the H level selection period and becomes conductive. As a result, the source follower transistor SF3S-Tr outputs the read-out voltage (VSIG) of the column output corresponding to the holding voltage of the second signal holding capacitor CS21 to the vertical signal line LSGN12.

The third output unit 245 basically outputs the signal held by the third signal holding capacitor CR22 according to the holding voltage during the global shutter period. The source follower transistor SF4R-Tr as the fourth source follower element. The retained signal is selectively output to the vertical signal line LSGN11 via the selection transistor SEL3R-Tr.

The source follower transistor SF4R-Tr and the selection transistor SEL3R-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN11.

A holding node ND25 is connected to the gate of the source follower transistor SF4R-Tr, and the selection transistor SEL3R-Tr is controlled by the control signal SEL1 applied to the gate through the control line.
In the selection transistor SEL3R-Tr, the control signal SEL1 is selected during the H level selection period and becomes conductive. As a result, the source follower transistor SF4R-Tr outputs the read-out voltage (VRST) of the column output corresponding to the holding voltage of the third signal holding capacitor CR22 to the vertical signal line LSGN11.

The fourth output unit 246 basically outputs the signal held by the fourth signal holding capacitor CS22 according to the holding voltage during the global shutter period. The source follower transistor SF5S-Tr as the fifth source follower element. The retained signal is selectively output to the vertical signal line LSGN12 via the selection transistor SEL4S-Tr.

The source follower transistor SF5S-Tr and the selection transistor SEL4S-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN12.

The holding node ND26 is connected to the gate of the source follower transistor SF5S-Tr, and the selection transistor SEL4S-Tr is controlled by the control signal SEL1 applied to the gate through the control line.
In the selection transistor SEL4S-Tr, the control signal SEL1 is selected during the H level selection period and becomes conductive. As a result, the source follower transistor SF5S-Tr outputs the read-out voltage (VSIG) of the column output corresponding to the holding voltage of the fourth signal holding capacitor CS22 to the vertical signal line LSGN12.

As described above, in the solid-state imaging device 10H according to the ninth embodiment, the pixel signal is simultaneously sampled by all the pixels in the signal holding unit 240 as the pixel signal storage in the voltage mode, and the first signal holding capacitor is used. The conversion signal corresponding to the read signal held in the CR21, the second signal holding capacitor CS21, the third signal holding capacitor CR22, and the fourth signal holding capacitor CS22 is read out to the vertical signal lines LSGN11 and 12, and the column readout circuit 40 Supply to.

In the pixel unit 20H according to the ninth embodiment, unit pixels 200H having the above configuration are arranged as a pixel array, for example, as shown in FIG. 26, and a plurality of pixel arrays are combined and configured. There is.

FIG. 26 is a circuit diagram showing a configuration example of a global shutter system circuit in the pixel portion 20H and the readout portion of the solid-state image sensor 10H according to the ninth embodiment.

The solid-state image sensor 10H according to the ninth embodiment has a plurality of charge storage units for phase difference information in one unit pixel, and holds signals as a memory unit capable of holding each signal globally. It has a unit 240. The signals globally held by the signal holding unit 240 are sequentially read out (rolling).

(Laminate structure of solid-state image sensor 10H)
Next, the laminated structure of the solid-state image sensor 10H according to the ninth embodiment will be described.

FIG. 27 is a diagram for explaining a laminated structure of the solid-state image sensor 10H according to the ninth embodiment.

The solid-state image sensor 10H according to the ninth embodiment has a laminated structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
The solid-state image sensor 10 is formed as, for example, an image sensor having a laminated structure cut out by dicing after being bonded at a wafer level.
In this example, the first substrate 110 is laminated on the second substrate 120. Further, the second substrate 120 is supported by the support member 130.

On the first layer 111 of the first substrate 110, a pixel array is formed in which the photoelectric conversion reading unit 230 of each unit pixel 200 of the pixel unit 20H is arranged around the central portion thereof.
Then, a part of the column readout circuit 40 is formed around the pixel array.

As described above, in the first embodiment, the photoelectric conversion reading unit 230 of the pixel 200 is basically formed in a matrix on the first layer 111 of the first substrate 110.
A second layer 112 including a microlens array and a color filter array is laminated on the light incident side of the first layer 111 of the first substrate 110.

On the second substrate 120, a holding unit array in which signal holding units 240 of each pixel 200 connected to the output node ND2 of each photoelectric conversion reading unit 230 of the pixel array are arranged in a matrix centering on the central portion. In addition, vertical signal lines LSGN11,12 are formed.
The holding array may be completely shielded by a metal wiring layer.
Then, a part of the column reading circuit 40 is formed around the holding unit array.

In such a laminated structure, for example, the read node ND2 of each photoelectric conversion reading unit 230 of the pixel array of the first substrate 110 and the input node ND22 of the signal holding unit 240 of each pixel 200 of the second substrate 120 are shown in FIG. As shown in 25, electrical connection is performed using via micro bump BMP, (Die-to-Die Via), or the like, respectively.

(Reading operation of solid-state image sensor 10H)
The characteristic configurations and functions of each part of the solid-state image sensor 10H have been described above.
Next, an outline of the operation of reading out the differential pixel signal of the solid-state image sensor 10H according to the ninth embodiment will be described.

FIG. 28 is a timing chart for explaining the reading operation mainly in the pixel portion in the predetermined shutter mode of the solid-state image sensor 10H according to the ninth embodiment.
29 (A) and 29 (B) are operation sequence diagrams for explaining the global shutter read-out operation of the solid-state image sensor 10H according to the ninth embodiment in comparison with the rolling shutter read-out operation.
FIG. 30 is a diagram for explaining an example of anti-blooming control in the solid-state image sensor 10H according to the ninth embodiment.

In the circuit configuration example of FIG. 25, the first photodiode PD1 which is the first photoelectric conversion unit and the photodiode PD2 which is the second photoelectric conversion unit are read out independently.
First, the reset level of the floating diffusion FD is read out by the photoelectric conversion reading unit 230, and is held by the signal holding capacitors CR21 and CR22 of the signal holding unit 240.
Next, a signal corresponding to the accumulated charge of the first photodiode PD1 is read out and held by the signal holding capacitor CH21 of the signal holding unit 240.

Then, for example, in the column read circuit 40 that constitutes a part of the read unit 70, amplification processing and AD conversion processing for the read reset signal VRST and the read signal VSIG of the pixel signal pickout that are simultaneously and simultaneously supplied in a differential manner are performed. Also, the difference between the two signals {VRST-VSIG} is taken and the CDS processing is performed.

Similarly, a signal corresponding to the accumulated charge of the second photodiode PD2 is read out and held by the signal holding capacitor CH 22 of the signal holding unit 240. That is, signal reading, signal holding, CDS processing, AD conversion processing, and the like for the second photodiode PD2 are performed in the same manner.
As a result, the pixel signals read out by the first photodiode PD1 and the second photodiode PD2 with low noise are processed as distortion-free phase difference information.

The pixel gain can be controlled by the BIN switch and can be controlled according to the PD signal amount (illuminance), and PDAF signal processing in a wide range is possible, that is, the PDAF function in HDR becomes possible.

As shown in FIG. 29, in the case of the existing rolling readout, the accumulation period start time differs depending on the vertical coordinates, so that the phase difference information differs depending on the vertical coordinates.
In particular, when the object is moving at high speed, the timing of reading is different between the upper end and the lower end of the pixel array, and the phase difference information differs depending on the position of the object, so that the phase difference information is distorted.
On the other hand, in the case of the global shutter, this problem is solved and the distortion of the phase difference information does not occur even in the moving image.

Further, in the ninth embodiment, by arranging the signal holding unit 240 as a memory unit in the pixel, it is possible to capture the first photodiode PD1 and the second photodiode PD2 almost simultaneously. By installing an AB (anti-blooming) gate on the photodiode PF, it is possible to prevent the signal of one side (PD1) from being mixed when reading one signal (for example, PD2), and normal photoelectric conversion characteristics can be obtained. Obtainable.

As shown in FIG. 30, the AB gate can also be potential-controlled.
That is, as OF_AB <OF_TG, it is possible to prevent the overflow charge from being mixed from the PD pixel sharing the floating diffusion FD while reading the signal corresponding to the accumulated charge of the photodiode pd.
The binning transistor BIN-Tr makes it possible to electrically conduct the FD node to increase the capacity of the charge conversion unit and increase the convertible capacity, and as a result, more photoelectric conversion becomes possible.

As described above, according to the ninth embodiment, the pixel unit 20H has a pixel array in which photoelectric conversion reading units 230 of a plurality of unit pixels 200 are arranged in a matrix and a signal holding of the plurality of pixels 200. The unit 240 is configured as, for example, a stacked CMOS image sensor, which includes a holding array in which the units 240 are arranged in a matrix.

That is, in the ninth embodiment, the solid-state image sensor 10H includes a photoelectric conversion readout unit and a signal holding unit as pixels in the pixel unit 20H, has a global shutter operation function, and has a substantially wide dynamic range. , For example, it is configured as a stacked CMOS image sensor, which makes it possible to realize a high frame rate.

Therefore, according to the solid-state image sensor 10H of the ninth embodiment, not only the global shutter can be realized, but also the electric charge overflowing from the photodiode during the accumulation period is used in real time, so that the dynamic range is widened. It is possible to realize a high frame rate.
Further, according to the ninth embodiment, it is possible to substantially realize a wide dynamic range and a high frame rate, reduce noise, and expand the effective pixel area to the maximum. It is possible to maximize the value per cost.

Further, according to the solid-state image sensor 10H of the ninth embodiment, it is possible to prevent a decrease in area efficiency in layout while preventing a complicated configuration.

Further, the solid-state image sensor 10H according to the ninth embodiment has a laminated structure of a first substrate (upper substrate) 110 and a second substrate (lower substrate) 120.
Therefore, in the ninth embodiment, the cost is obtained by basically forming the first substrate 110 side only with the elements of the NMOS system and maximizing the effective pixel area by the pixel array. You can maximize the value per unit.

(10th Embodiment)
FIG. 31 is a block diagram showing a configuration example of the solid-state image sensor according to the tenth embodiment of the present invention.
In the present embodiment, the solid-state image sensor 10I is composed of, for example, a CMOS image sensor including digital pixels (Digital Pixel) as pixels.

As shown in FIG. 31, the solid-state image sensor 10I has a pixel unit 20I as an image pickup unit, a vertical scanning circuit (row scanning circuit) 30I, an output circuit 80, and a timing control circuit 60 as main components. ..
Among these components, for example, the vertical scanning circuit 30I, the output circuit 80, and the timing control circuit 60 constitute a pixel signal reading unit 70I.

In the tenth embodiment, the solid-state image sensor 10I has a photoelectric conversion readout unit 230 and a signal holding unit 240I as digital pixels in the pixel unit 20I, and the signal holding unit 240I is an AD (analog digital) conversion unit. It is configured as, for example, a stacked CMOS image sensor that includes a memory unit and has a global shutter operation function.
In the solid-state imaging device 10I according to the tenth embodiment, as will be described in detail later, each digital pixel DP has an AD conversion function, and the AD conversion unit is a voltage read by a photoelectric conversion reading unit. It has a comparator (comparator) that compares a signal with a reference voltage and performs a comparison process to output a digitized comparison result signal.
Then, the comparator, for example, under the control of the read unit 70I, digitizes the first comparison result signal with respect to the voltage signal corresponding to the overflow charge overflowing from the photoelectric conversion element to the output node (floating diffusion) during the storage period. The first comparison process to output and the second comparison to output the digitized second comparison result signal with respect to the voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node in the transfer period after the accumulation period. Process and perform.

Hereinafter, the outline of the configuration and function of each part of the solid-state image sensor 10I, in particular, the configuration and function of the pixel unit 20I and the digital pixel, the readout processing related thereto, the laminated structure of the pixel portion 20I and the readout unit 70I, and the like are described in detail. Describe.

(Structure of pixel unit 20I and digital pixel 200I)
FIG. 32 is a diagram showing an example of a digital pixel array of the pixel portion of the solid-state image sensor 10I according to the tenth embodiment of the present invention.
FIG. 33 is a circuit diagram showing an example of pixels of the solid-state image sensor 10I according to the tenth embodiment of the present invention.

As shown in FIG. 32, in the pixel unit 20I, a plurality of digital pixels 200B are arranged in a matrix of N rows and M columns.
Note that FIG. 32 shows an example in which nine digital pixels 200I are arranged in a matrix of 3 rows and 3 columns (matrix of M = 3 and N = 3) for simplification of the drawing. ..

The digital pixel 200I according to the tenth embodiment has a photoelectric conversion reading unit (denoted as PD in FIG. 32) 230, an AD conversion unit (denoted as ADC in FIG. 32) 250, and a memory unit (denoted as MEM in FIG. 32). ) 260 is included.
As will be described in detail later, the pixel portion 20I of the tenth embodiment is configured as a laminated CMOS image sensor of the first substrate 110 and the second substrate 120, but in this example, FIG. 33 As shown in the above, a photoelectric conversion reading unit 230 is formed on the first substrate 110, and an AD conversion unit 250 and a memory unit 260 of the signal holding unit 240I are formed on the second substrate 120.

The photoelectric conversion reading unit 230 of the digital pixel 200I has the same configuration as that of FIG. 25. Therefore, the detailed description thereof will be omitted.

However, the photoelectric conversion reading unit 230I according to the tenth embodiment is a floating diffusion as an output node from the photodiode PD1 which is a photoelectric conversion element during the storage period PI in the first comparison processing period PCMP1 of the AD conversion unit 250. The voltage signal VSL corresponding to the overflow charge overflowing to the FD1 is output.

Further, the photoelectric conversion reading unit 230 uses the stored charge of the photodiode PD1 transferred to the floating diffusion FD1 as an output node during the transfer period PT after the storage period PI in the second comparison processing period PCMP2 of the AD conversion unit 250. The corresponding voltage signal VSL is output.
The photoelectric conversion reading unit 230 outputs a reading reset signal (signal voltage) (VRST) and a reading signal (signal voltage) (VSIG) as pixel signals to the AD conversion unit 250 during the second comparison processing period PCMP2.

The AD conversion unit 250 of the digital pixel 200I compares the analog voltage signal VSL output by the photoelectric conversion reading unit 230 with a lamp waveform or a fixed voltage reference voltage VREF changed with a predetermined inclination. It has a function to convert to a digital signal.

As shown in FIG. 33, the AD conversion unit 250 includes a comparator (COMP) 251, an input side coupling capacitor C251, an output side load capacitor C252, and a reset switch SW-RST.

In the comparator 251, the voltage signal VSL output from the output buffer unit 231 of the photoelectric conversion reading unit 230 to the signal line LSGN1 is supplied to the inverting input terminal (-) as the first input terminal, and the second input terminal. The reference voltage VREF is supplied to the non-inverting input terminal (+), and the voltage signal VST and the reference voltage VREF are compared, and a comparison process is performed to output a digitized comparison result signal SCMP.

In the comparator 251, the coupling capacitor C251 is connected to the inverting input terminal (-) as the first input terminal, and the output buffer unit 231 and the second substrate of the photoelectric conversion reading unit 230 on the first substrate 110 side. By AC-coupling the input unit of the comparator 251 of the AD conversion unit 250 on the 120 side, noise reduction is achieved and a high SNR can be realized at low illuminance.

Further, in the comparator 251 the reset switch SW-RST is connected between the output terminal and the inverting input terminal (-) as the first input terminal, and the load capacitor C252 is connected between the output terminal and the reference potential VSS. It is connected.

Basically, in the AD conversion unit 250, the analog signal (potential VSL) read from the output buffer unit 231 of the photoelectric conversion reading unit 230 to the signal line LSGN1 has a reference voltage VREF, for example, a certain inclination in the comparator 251. It is compared with the ramp signal RAMP, which is a linearly changing slope waveform.
At this time, the counters arranged for each row are operating as in the comparator 251. The voltage signal VSL is converted into a digital signal by changing the counter value with the lamp signal RAMP having the lamp waveform while maintaining a one-to-one correspondence. Convert to.
Basically, the AD conversion unit 250 converts a change in the reference voltage VREF (for example, a lamp signal RAMP) into a change in time, and counts the time in a certain period (clock) to obtain a digital value. Convert to.
Then, when the analog signal VSL and the lamp signal RAMP (reference voltage VREF) intersect, the output of the comparator 251 is inverted and the input clock of the counter is stopped, or the clock at which the input has been stopped is input to the counter. , The value (data) of the counter at that time is stored in the memory unit 260 to complete the AD conversion.
After the end of the above AD conversion period, the data (signal) stored in the memory unit 260 of each digital pixel 200I is output from the output circuit 80 to a signal processing circuit (not shown), and a two-dimensional image is generated by a predetermined signal processing. ..

In the memory unit 260, for example, the read signal corresponding to the accumulated charge of the first photodiode PD1 is AD-converted and stored in the first memory 261 and read according to the accumulated charge of the second photodiode PD2. The signal is AD-converted and stored in the second memory 262.

(First comparison process and second comparison process in the comparator 251)
Then, the comparator 251 of the AD conversion unit 250 of the first embodiment is driven by the reading unit 70I so as to perform the following two first comparison processing and the second comparison processing during the pixel signal reading period. Be controlled.

In the first comparison process CMPR1, the comparator 251 responds to the overflow charge overflowing from the photodiode PD1 which is a photoelectric conversion element to the floating fusion FD1 which is an output node during the storage period PI under the control of the readout unit 70I. The first digitized comparison result signal SCMP1 with respect to the voltage signal VSL1 is output.
The operation of the first comparison process CMPR1 is an overflow charge sampling operation, but is also referred to as a time stamp ADC mode operation.

In the second comparison process CMPR2, the comparator 251 responds to the stored charge of the photodiode PD1 transferred to the floating fusion FD1 which is the output node during the transfer period PT after the storage period PI under the control of the readout unit 70I. The second digitized comparison result signal SCMP2 with respect to the voltage signal VSL2 (VSIG) is output.
Actually, in the second comparison processing CMPR2, before digitization of the voltage signal VSL2 (VSIG) according to the accumulated charge, digitalization of the voltage signal VSL2 (VRRT) corresponding to the reset voltage of the floating diffusion FD1 at the time of reset is performed. To perform the conversion.
The operation of the second comparison process CMPR2 is a sampling operation of accumulated charges, but is also referred to as an operation of a linear ADC mode.

In the present embodiment, basically, in the storage period PI, after the photodiode PD1 and the floating diffusion FD1 are reset to the reset level, the transfer transistor TG1-Tr is switched to the conductive state and the transfer period PT is started. It is the period until the end.
The period PCMPR1 of the first comparison process CMPR1 is the period from when the photodiode PD1 and the floating diffusion FD1 are reset to the reset level until the floating diffusion FD1 is reset to the reset level before the transfer period PT is started. Is.
The period PCMPR2 of the second comparison process CMPR2 is a period after the floating diffusion FD1 is reset to the reset level, and is a period including a period after the transfer period PT.

FIG. 34 is a diagram showing a configuration example of a memory unit and an output circuit according to a tenth embodiment of the present invention.

In the comparator 251, the first comparison result signal SCMP1 in which the voltage signal corresponding to the overflow charge of the floating diffusion FD1 is digitized by the first comparison processing CMPR1 and the storage of the photodiode PD1 by the second comparison processing CMPR2. The second comparison result signal SCMP2 in which the charge is digitized is associated and stored as digital data in the memories 261,262.
The memory unit 260 is composed of SRAM and DRAM, is supplied with a digitally converted signal, corresponds to a photo conversion code, and can be read out by an external IO buffer 81 of an output circuit 80 around a pixel array.

FIG. 35 is a diagram showing an example of a frame readout sequence in the solid-state image sensor 10I according to the tenth embodiment of the present invention.
Here, an example of the frame readout method in the solid-state image sensor 10I will be described.
In FIG. 35, TS indicates the processing period of the time stamp ADC, and Lin indicates the processing period of the linear ADC.

As mentioned above, the overflow charge is accumulated in the floating diffusion FD1 during the accumulation period PI. The time stamp ADC mode operates during the accumulation time PI.
In practice, the time stamp ADC mode operates during the accumulation period PI until the floating diffusion FD1 is reset.
When the operation of the time stamp ADC mode is completed, the mode shifts to the linear ADC mode, the signal (VRST) at the time of resetting the floating diffusion FD1 is read, and the digital signal is converted to be stored in the memory unit 260.
Further, after the storage period PI ends, in the linear ADC mode, the signal (VSIG) corresponding to the stored charge of the photodiode PD1 is read and converted so that the digital signal is stored in the memory unit 260.
The read frame is executed by reading the digital signal data from the memory node and has such a MIMO data format, eg, through the IO buffer 81 (FIG. 34) of the output circuit 80, the solid-state imaging device 10 (image). It is sent to the outside of the sensor). This operation can be performed globally for all pixel arrays.

Further, in the pixel unit 20I, the photodiode PD1 is reset by using the reset transistor RST1-Tr and the transfer transistor TG1-Tr at the same time for all the pixels, so that the exposure for all the pixels is started in parallel at the same time. Further, after the predetermined exposure period (accumulation feedback PI) is completed, the output signal from the photoelectric conversion / reading unit is sampled by the AD conversion unit 250 and the memory unit 260 using the transfer transistor TG1-Tr, so that all pixels can be simultaneously displayed. The exposure is finished in parallel. As a result, a complete shutter operation is electronically realized.

The vertical scanning circuit 30I drives the photoelectric conversion reading unit 230 of the digital pixel 200I through the line scanning control line in the shutter line and the reading line according to the control of the timing control circuit 50.
The vertical scanning circuit 30I has a reference voltage VREF1 set according to the first comparison processing CMPR1 and the second comparison processing CMPR2 for the comparator 251 of each digital pixel 200I according to the control of the timing control circuit 50. , VREF2 is supplied.
Further, the vertical scanning circuit 30I outputs a row selection signal of the row address of the read row for reading the signal and the row address of the shutter row for resetting the charge accumulated in the photodiode PD according to the address signal.

As shown in FIG. 34, for example, the output circuit 80 includes an IO buffer 81 arranged corresponding to the memory output of each digital pixel 200I of the pixel unit 20I, and outputs digital data read from each digital pixel 200I to the outside. To do.

The timing control circuit 60 generates a timing signal necessary for signal processing of the pixel unit 20I, the vertical scanning circuit 30I, the output circuit 80, and the like.

In the tenth embodiment, the reading unit 70I controls reading a pixel signal from the digital pixel 200I, for example, in the global shutter mode.

(Laminate structure of solid-state image sensor 10B)
Next, the laminated structure of the solid-state image sensor 10B according to the third embodiment will be described.

36 (A) and 36 (B) are schematic views for explaining the laminated structure of the solid-state image sensor 10I according to the tenth embodiment.
FIG. 37 is a simplified cross-sectional view for explaining the laminated structure of the solid-state image sensor 10I according to the tenth embodiment.

The solid-state image sensor 10I according to the tenth embodiment has a laminated structure of a first substrate (upper substrate) 110I and a second substrate (lower substrate) 120I.
The solid-state image sensor 10I is formed as an image sensor having a laminated structure cut out by dicing after being bonded at a wafer level, for example.
In this example, the first substrate 110I and the second substrate 120I are laminated.

The first substrate 110I is formed with a photoelectric conversion reading unit 230 of each digital pixel 200I of the pixel unit 20I centered on the central portion thereof.
A photodiode PD is formed on the first surface 111 side where the light L of the first substrate 110I is on the incident side, and a microlens MCL and a color filter are formed on the light incident side.
A transfer transistor TG1-Tr, a reset transistor RST1-Tr, a source follower transistor SF1-Tr, a current transistor IC1-Tr, a storage transistor SG1-Tr, and a storage capacitor CS1 are formed on the second surface side of the first substrate 110I.

As described above, in the tenth embodiment, the photoelectric conversion reading unit 230 of the digital pixel 200I is basically formed in a matrix on the first substrate 110I.

On the second substrate 120I, the AD conversion unit 250 and the memory unit 260 of each digital pixel 200I are formed in a matrix.
Further, the vertical scanning circuit 30I, the output circuit 80, and the timing control circuit 60 may also be formed on the second substrate 120I.

In such a laminated structure, for example, the readout node ND2 of each photoelectric conversion readout unit 230 of the first substrate 110I and the inverting input terminal (-) of the comparator 251 of each digital pixel 200I of the second substrate 120I are shown in FIG. As shown in 33, electrical connections are made using signal lines LSGN1, microbump BMP, vias (Die-to-Die Via), and the like, respectively.
Further, in the present embodiment, the readout node ND2 of each photoelectric conversion readout unit 230 of the first substrate 110I and the inverting input terminal (-) of the comparator 251 of each digital pixel 200I of the second substrate 120I are coupled capacitors. It is AC-coupled by C251.

According to the solid-state image sensor 10I having digital pixels of the tenth embodiment, as in the first embodiment described above, since there is no light-shielding object, a decrease in sensitivity is suppressed and a photoelectric conversion functional region is provided. Since the charge storage function area is divided, the depletion voltage can be suppressed without losing the saturated charge, and since the phase difference information acquisition function is provided for each pixel, the power consumption is low without image correction. It is possible to acquire highly accurate phase difference information, and by extension, it is possible to improve the image quality without involving a complicated reading method.

Further, since the photoelectric conversion unit has a photoelectric conversion function region 2211 and a charge storage function region 2212 arranged so as to be offset from the central CTpd, and an isolation region 2241 arranged in the remaining region, the unit pixel has a simple structure. It is possible to realize various aspects such as horizontal unit pixel PXL1L, vertical unit pixel PXL1V, diagonal unit pixel PXL1D, and the like according to the specifications.
In addition, it is possible to acquire phase difference information without blooming, and it is possible to realize a solid-state image sensor that can avoid fluctuations in the amount of saturated charges and a decrease in area efficiency.

Further, according to the tenth embodiment, the solid-state image sensor 10I includes a photoelectric conversion reading unit 230, an AD conversion unit 250, and a memory unit 260 as digital pixels in the pixel unit 20I, and has a global shutter operation function. It is configured as, for example, a stacked CMOS image sensor.
In the solid-state imaging device 10I according to the tenth embodiment, each digital pixel 200 has an AD conversion function, and the AD conversion unit 250 compares the voltage signal read by the photoelectric conversion reading unit 210 with the reference voltage. It also has a comparator 251 that performs a comparison process that outputs a digitized comparison result signal.
Then, under the control of the readout unit 70I, the comparator 251 digitizes the first comparison result signal for the voltage signal corresponding to the overflow charge overflowing from the photodiode PD1 to the output node (floating diffusion) FD1 during the storage period. The first comparison process CMPR1 that outputs SCMP1 and the second digitized comparison result for the voltage signal corresponding to the accumulated charge of the photodiode PD1 transferred to the floating node FD1 (output node) during the transfer period after the accumulation period. The second comparison process CMPR2, which outputs the signal SCMP2, is performed.

Therefore, according to the solid-state image sensor 10I of the tenth embodiment, since the electric charge overflowing from the photodiode during the storage period is used in real time, it is possible to realize a wide dynamic range and a high frame rate. Become.
Further, according to the present invention, it is possible to substantially realize a wide dynamic range and a high frame rate, reduce noise, maximize the effective pixel area, and per cost. It is possible to maximize the value of.

Further, according to the solid-state image sensor 10I of the tenth embodiment, it is possible to prevent a decrease in area efficiency in layout while preventing a complicated configuration.

Further, the solid-state image sensor 10I according to the tenth embodiment has a laminated structure of a first substrate (upper substrate) 110I and a second substrate (lower substrate) 120I.
Therefore, in the tenth embodiment, the cost is obtained by basically forming the first substrate 110I side only with the elements of the NMOS system and expanding the effective pixel area to the maximum by the pixel array. You can maximize the value per unit.

The solid-state imaging devices 10, 10A to 10I described above can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

FIG. 38 is a diagram showing an example of the configuration of an electronic device equipped with a camera system to which the solid-state image sensor according to the embodiment of the present invention is applied.

As shown in FIG. 38, the electronic device 300 has a CMOS image sensor 310 to which the solid-state image sensors 10, 10A to 10I according to the present embodiment can be applied.
Further, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light (imaging a subject image) to the pixel region of the CMOS image sensor 310.
The electronic device 300 includes a signal processing circuit (PRC) 330 that processes the output signal of the CMOS image sensor 310.

The signal processing circuit 330 performs predetermined signal processing on the output signal of the CMOS image sensor 310.
The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor including a liquid crystal display or output to a printer, and can be directly recorded on a recording medium such as a memory card. Is possible.

As described above, by mounting the above-mentioned solid-state image sensors 10, 10A to 10I as the CMOS image sensor 310, it is possible to provide a high-performance, compact, and low-cost camera system.
Electronic devices such as surveillance cameras and medical endoscope cameras are used in applications where camera installation requirements include restrictions such as mounting size, number of cables that can be connected, cable length, and installation height. Can be realized.

10,10A-10I ... Solid-state imaging device, 20,20A-20I ... Pixel unit, PCXL, PXLA to PXLH ... Unit pixel, PD1 ... First photodiode (first photoelectric conversion unit) ), PD2 ... 2nd photodiode (2nd photoelectric conversion unit), TG1-Tr ... 1st transfer transistor (1st transfer element), TG2-Tr ... 2nd transfer transistor (Second transfer element), 210 ... semiconductor substrate, 230 ... photoelectric conversion readout unit, 240 ... signal holding unit, 30 ... vertical scanning circuit, 40 ... readout circuit, 50 ...・ Horizontal scanning circuit, 60 ・ ・ ・ Timing control circuit, 70, 70I ・ ・ ・ Read unit, 300 ・ ・ ・ Electronic device, 310 ・ ・ ・ CMOS image sensor, 320 ・ ・ ・ Optical system, 330 ・ ・ ・ Signal processing Circuit (PRC).

Claims (27)

A substrate having a first substrate surface side and a second substrate surface side facing the first substrate surface side,
A photoelectric layer including a first conductive semiconductor layer formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, photoelectrically converts incident light, and generates an electric charge according to the amount of incident light. A conversion function region and at least one photoelectric conversion unit that forms a unit pixel having a charge storage function region for accumulating charges generated in the photoelectric conversion function region are included.
The photoelectric conversion unit
The photoelectric conversion functional region is arranged on the surface side of the first substrate on which light is incident, and the charge storage functional region is arranged on the surface side of the second substrate.
A solid-state imaging measure in which at least the photoelectric conversion functional region of the photoelectric conversion functional region and the charge storage functional region is arranged so as to be offset from the central portion of the photoelectric conversion portion. The solid-state image sensor according to claim 1, wherein the photoelectric conversion function region and the charge storage function region are arranged so as to be offset from the central portion of the photoelectric conversion unit. The photoelectric conversion function region is arranged so as to be offset from the central portion of the photoelectric conversion unit.
The solid-state imaging device according to claim 1, wherein the charge storage function region is arranged so that the central portion thereof exists in the central portion of the photoelectric conversion unit. It is arranged on the surface side of the second substrate and has a lens unit that injects light into the photoelectric conversion unit.
The lens unit
The solid-state image sensor according to any one of claims 1 to 3, wherein the optical center is arranged so as to exist in the central portion of the photoelectric conversion unit. The photoelectric conversion unit
The isolation region formed by the second conductive semiconductor layer or the region excluding the photoelectric conversion functional region and the charge storage functional region formed by the first conductive semiconductor layer is embedded so as to be optically shielded. The solid-state imaging device according to any one of claims 1 to 4, wherein the backside separation unit is arranged. A plurality of the unit pixels are arranged in a matrix, and the plurality of unit pixels are included in the plurality of unit pixels.
Horizontal unit pixels in which the photoelectric conversion units including the isolation region are arranged in parallel in the column direction, and
Vertical unit pixels in which the photoelectric conversion units including the isolation region are arranged in parallel in the row direction, and
The fifth aspect of claim 5 which includes at least one of an oblique unit pixel in which the photoelectric conversion unit including the isolation region is arranged in parallel in an oblique direction having a predetermined angle with respect to a column direction and a row direction. Solid-state image sensor. The unit pixel is formed as the horizontal unit pixel,
The solid-state image sensor according to claim 6, wherein the position of the photoelectric conversion unit including the isolation region and at least the photoelectric conversion functional region is reversed for each row in the column direction. The unit pixel is formed as the diagonal unit pixel,
The solid-state image sensor according to claim 6, wherein the tilt direction of a predetermined angle between the photoelectric conversion unit and the isolation region is different for each row. Each unit pixel is
A transfer transistor for transferring the charge stored in the charge storage function region is included.
The transfer transistor is
The solid-state image sensor according to any one of claims 6 to 8, which is connected to the charge storage function region of the photoelectric conversion unit on the surface side of the second substrate. The unit pixel is formed in a rectangular shape, and the transfer transistor is formed on one edge side.
In the plurality of unit pixels, the one edge portion on which the transfer transistor is formed in the array row faces the other edge portion side on which the transfer transistor facing the one edge portion of the unit pixel adjacent in the column direction is not formed. 9. The solid-state imaging device according to claim 9. The photoelectric conversion unit
The solid-state image sensor according to any one of claims 1 to 10, further comprising an overflow gate for discharging the overflowing charge from the charge storage function region. The unit pixel is
A first having a first photoelectric conversion functional region for photoelectrically converting incident light and generating charges according to the amount of incident light and a first charge storage functional region for accumulating charges generated in the first photoelectric conversion functional region. Photoelectric conversion unit and
A second having a second photoelectric conversion functional region for photoelectrically converting incident light and generating charges according to the amount of incident light and a second charge storage functional region for accumulating charges generated in the second photoelectric conversion functional region. Including the photoelectric conversion part of
The first photoelectric conversion unit and the second photoelectric conversion unit are
The solid-state image sensor according to claim 1, which is arranged in parallel and separated by a separation layer formed by a second conductive semiconductor layer or a backside separation portion embedded so as to optically shield the semiconductor layer. The first photoelectric conversion unit is
The first photoelectric conversion functional region and the first charge storage functional region are arranged so as to be offset from the central portion of the first photoelectric conversion portion.
The second photoelectric conversion unit is
The solid-state image sensor according to claim 12, wherein the second photoelectric conversion functional region and the second charge storage functional region are arranged so as to be offset from the central portion of the second photoelectric conversion portion. The first photoelectric conversion unit is
The first photoelectric conversion functional region is arranged so as to be offset from the central portion of the first photoelectric conversion unit.
The first charge storage functional region is arranged so that the central portion thereof is located in the central portion of the first photoelectric conversion unit.
The second photoelectric conversion unit is
The second photoelectric conversion functional region is arranged so as to be offset from the central portion of the second photoelectric conversion unit.
The solid-state image sensor according to claim 12, wherein the second charge storage functional region is arranged so that the central portion thereof is located in the central portion of the second photoelectric conversion unit. It has a lens unit that is arranged on the surface side of the second substrate and that emits light into the first photoelectric conversion unit and the second photoelectric conversion unit.
The lens unit
Any of claims 12 to 14, wherein the optical centers are arranged so as to exist in the central portion of the boundary region between the first photoelectric conversion unit and the second photoelectric conversion unit, which are arranged in parallel with the separation layer interposed therebetween. The solid-state image sensor according to claim 1. The first photoelectric conversion unit is
A first isolation region formed by the second conductive semiconductor layer is formed in a region other than the first photoelectric conversion functional region and the first charge storage functional region formed by the first conductive semiconductor layer. Placed,
The second photoelectric conversion unit is
A second isolation region formed by the second conductive semiconductor layer is formed in a region other than the second photoelectric conversion functional region and the second charge storage functional region formed by the first conductive semiconductor layer. The solid-state imaging device according to any one of claims 12 to 15, which is arranged. A plurality of the unit pixels are arranged in a matrix, and the plurality of unit pixels are included in the plurality of unit pixels.
A horizontal unit pixel in which the first photoelectric conversion unit including the first isolation region and the second photoelectric conversion unit including the second isolation region are arranged in parallel in the column direction. When,
A vertical unit pixel in which the first photoelectric conversion unit including the first isolation region and the second photoelectric conversion unit including the second isolation region are arranged in parallel in the row direction. When,
The first photoelectric conversion unit including the first isolation region and the second photoelectric conversion unit including the second isolation region are oblique to have a predetermined angle with respect to the column direction and the row direction. The solid-state image sensor according to claim 16, further comprising at least one of an oblique unit pixel arranged in parallel. The first photoelectric conversion unit is
The first transfer transistor for transferring the charge accumulated in the first charge storage functional region is included.
The first transfer transistor is
On the surface side of the second substrate, it is connected to the first charge storage function region of the first photoelectric conversion unit.
The second photoelectric conversion unit is
The second transfer transistor for transferring the charge accumulated in the second charge storage functional region is included.
The second transfer transistor is
The solid-state image sensor according to any one of claims 12 to 17, which is connected to the second charge storage function region of the second photoelectric conversion unit on the surface side of the second substrate. Each of the unit pixels is formed as the vertical unit pixel.
In the unit pixel
The fixed imaging device according to claim 18, wherein the first transfer transistor and the second transfer transistor are arranged so as to face each other with the separation layer interposed therebetween. The first photoelectric conversion unit is
It has a first overflow gate that discharges the charge overflowing from the first charge storage function region, and has a first overflow gate.
The second photoelectric conversion unit is
The solid-state image sensor according to any one of claims 12 to 19, further comprising a second overflow gate for discharging the charge overflowing from the second charge storage functional region. The unit pixel is
A photoelectric that includes at least one photoelectric conversion unit, reads out the electric charge accumulated in the photoelectric conversion unit to an output node, converts the electric charge of the output node into a voltage signal according to the amount of charge, and outputs the converted voltage signal. Conversion reader and
The solid-state imaging according to any one of claims 12 to 20, further comprising a signal holding unit capable of holding a pixel signal corresponding to the accumulated charge of the photoelectric conversion unit read by the photoelectric conversion reading unit. apparatus. The photoelectric conversion reading unit is
The photoelectric conversion functional region that photoelectrically converts incident light and generates an electric charge according to the amount of incident light, and at least one photoelectric conversion unit having the charge storage functional region that accumulates the electric charge generated in the photoelectric conversion functional region.
A transfer transistor that transfers the charge accumulated in the charge storage function region of the photoelectric conversion unit, and
An output node to which the charge accumulated in the charge storage function region of the photoelectric conversion unit is transferred through the transfer transistor, and
An output buffer unit that converts the electric charge of the output node into a voltage signal according to the amount of electric charge and outputs the converted voltage signal.
Includes a reset transistor that resets the output node to a predetermined potential during the reset period.
The signal holding unit is
The solid-state image sensor according to claim 21, wherein a signal for the voltage signal corresponding to the accumulated charge in the charge storage function region of the photoelectric conversion unit transferred to the output node can be held. The photoelectric conversion reading unit is
The first having a first photoelectric conversion functional region for photoelectrically converting incident light and generating an electric charge according to the amount of incident light and a first charge storage functional region for accumulating charges generated in the first photoelectric conversion functional region. 1 photoelectric conversion unit and
The first having a second photoelectric conversion functional region that photoelectrically converts incident light and generates an electric charge according to the amount of incident light and a second charge storage functional region that accumulates the electric charge generated in the second photoelectric conversion functional region. 2 photoelectric conversion part and
A first transfer transistor that transfers the charge accumulated in the first charge storage function region of the first photoelectric conversion unit, and a first transfer transistor.
A second transfer transistor that transfers the charge accumulated in the second charge storage function region of the second photoelectric conversion unit, and a second transfer transistor.
It is accumulated in the charge storage function region of at least one of the first photoelectric conversion unit and the second photoelectric conversion unit through at least one transfer transistor of the first transfer transistor and the second transfer transistor. The signal holding unit, including the output node to which the electric charge is transferred,
The first signal with respect to the voltage signal according to the accumulated charge in the first charge storage function region of the first photoelectric conversion unit transferred to the output node, and
The solid-state imaging according to claim 21 or 22, wherein a second signal with respect to the voltage signal corresponding to the accumulated charge in the second charge storage function region of the second photoelectric conversion unit transferred to the output node can be held. apparatus. The signal holding unit is
The first input node and
The second input node and
A first signal holding capacitor capable of holding a first read reset signal output from the read node of the photoelectric conversion read unit of the pixel and input to the input node.
A second signal holding capacitor capable of holding a first read signal output from the read node of the photoelectric conversion reading unit of the pixel and input to the input node.
A third signal holding capacitor capable of holding a read reset signal output from the read node of the photoelectric conversion reading unit of the pixel and input to the input node.
A fourth signal holding capacitor capable of holding a read signal output from the read node of the photoelectric conversion reading unit of the pixel and input to the input node, and
A first switch element that selectively connects the first signal holding capacitor to the reading node of the photoelectric conversion reading unit, and
A second switch element that selectively connects the second signal holding capacitor to the reading node of the photoelectric conversion reading unit, and
A third switch element that selectively connects the third signal holding capacitor to the reading node of the photoelectric conversion reading unit, and
A fourth switch element that selectively connects the fourth signal holding capacitor to the reading node of the photoelectric conversion reading unit, and
A first output unit that includes a source follower element that outputs a signal held in the first signal holding capacitor according to a holding voltage and selectively outputs a converted signal to a signal line.
A second output unit that includes a source follower element that outputs the signal held in the second signal holding capacitor according to the holding voltage and selectively outputs the converted signal to the signal line.
A third output unit that includes a source follower element that outputs the signal held in the third signal holding capacitor according to the holding voltage and selectively outputs the converted signal to the signal line.
23. Claim 23 includes a source follower element that outputs a signal held in the fourth signal holding capacitor according to a holding voltage, and a fourth output unit that selectively outputs the converted signal to a signal line. The solid-state imaging device described. The signal holding unit is
A comparator that compares the voltage signal read by the photoelectric conversion reading unit with the reference voltage, performs analog-to-digital (AD) conversion processing on the read voltage signal, and outputs a digitized comparison result signal.
The solid according to any one of claims 21 to 23, comprising a memory that holds the comparison result signal by the comparator with respect to the voltage signal corresponding to the accumulated charge of the photoelectric conversion unit transferred to the output node. Image sensor. A substrate having a first substrate surface side and a second substrate surface side facing the first substrate surface side,
A photoelectric layer including a first conductive semiconductor layer formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, photoelectrically converts incident light, and generates an electric charge according to the amount of incident light. A method for manufacturing a solid-state imaging device, comprising at least one photoelectric conversion unit that forms a conversion function region and a unit pixel having a charge storage function region for accumulating charges generated in the photoelectric conversion function region.
In the step of forming the photoelectric conversion unit,
The photoelectric conversion functional region is formed on the surface side of the first substrate on which light is incident, and the charge storage functional region is formed on the surface side of the second substrate.
A method for manufacturing a solid-state image sensor, in which at least the photoelectric conversion functional region is formed by shifting the photoelectric conversion functional region and the charge storage functional region from the central portion of the photoelectric conversion portion. Solid-state image sensor and
The solid-state image sensor has an optical system for forming a subject image, and the solid-state image sensor has an optical system.
The solid-state image sensor
A substrate having a first substrate surface side and a second substrate surface side facing the first substrate surface side,
A photoelectric layer including a first conductive semiconductor layer formed so as to be embedded between the first substrate surface side and the second substrate surface side of the substrate, photoelectrically converts incident light, and generates an electric charge according to the amount of incident light. A conversion function region and at least one photoelectric conversion unit that forms a unit pixel having a charge storage function region for accumulating charges generated in the photoelectric conversion function region are included.
The photoelectric conversion unit
The photoelectric conversion functional region is arranged on the surface side of the first substrate on which light is incident, and the charge storage functional region is arranged on the surface side of the second substrate.
An electronic device in which at least the photoelectric conversion functional region is arranged so as to be offset from the central portion of the photoelectric conversion functional region and the charge storage functional region.

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