JP2704106B2 - Frame synchronization method for data signal multiplex transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization system for a data signal multiplex transmission apparatus, and more particularly, to a cyclic redundancy check (Cyclic Re-Check) for each channel.
The present invention relates to a frame synchronization method for a data signal multiplex transmission apparatus that secures frame synchronization when multiplex transmission of a plurality of data signals having bits (dundancy check, hereinafter referred to as CRC) from a transmission side to a reception side via a transmission path.

[0002]

2. Description of the Related Art Conventionally, in this type of frame synchronization system for a data signal multiplex transmission apparatus, a frame synchronization pattern expressing frame synchronization information is added to a multiplex signal separately from a data signal in order to establish frame synchronization. Was transmitting. Therefore, the transmission side requires a frame synchronization pattern generation and addition circuit, and the reception side requires a frame synchronization pattern detection circuit. In another frame synchronization method for a data signal multiplex transmission apparatus, a CRC operation is performed on the receiving side to establish frame synchronization instead of adding a frame synchronization pattern, and a CRC check bit included in the multiplexed signal is checked. Had been detected. Therefore, this method can only discriminate an arbitrary frame phase,
Channel identification information is separately added to the data signal.

[0003]

In the conventional frame synchronization method for a data signal multiplex transmission apparatus, in the case of adding a frame synchronization pattern, a transmission is performed to add a frame synchronization pattern, which is frame synchronization information, to the data multiplexed signal. All of the path capacity cannot be used for data signal transmission, and a detection circuit for detecting a frame synchronization pattern must be provided, which causes a problem that the circuit scale becomes large. Even when the frame synchronization pattern is not added to the multiplexed signal, since each channel has a CRC check bit using the same generator polynomial, it is not possible to identify the position of each channel in the multiplexed signal, There is a problem that the entire transmission path capacity cannot be used for data transmission because of the additional addition.

The present invention solves the above-mentioned problems, and provides a frame synchronization system for a data signal multiplex transmission apparatus which can use all of the transmission path capacity for data transmission without newly adding a frame synchronization pattern in a multiplex signal. Is to do.

[0005]

According to the method of the present invention, an error detection code by a cyclic redundancy check operation is added to a data signal inputted from the outside, and n is added to the data signal.
Channel transmission signal generating means for outputting as a channel transmission signal; multiplexing means for receiving an n-channel transmission signal from the channel transmission signal generating means and outputting the multiplexed signal as a time-division multiplexed signal; Receiving means for detecting the frame phase and channel phase of the multiplexed signal and separating the signals for each channel, and inputting the channel received signal by the separating means to perform error detection and error detection code deletion. In a frame synchronization system used in a data signal multiplexing transmission apparatus having a channel reception signal generating means for outputting a data signal to the outside, only one of a plurality of channels included in the channel transmission signal generating means is different from other channels. Calculation result obtained by performing cyclic redundancy check calculation using polynomial Its sends out as the added channel transmission signal to the data signal as an error detection code
The added channel is used as a frame in data signal multiplex transmission.
A channel transmission signal generating means as a system head channel, and a generator polynomial which receives a multiplexed signal output from the multiplexing means via the transmission path and uses the multiplexed signal in only one channel. Performs a cyclic redundancy check operation, and the operation result is the received signal
Detects the frame phase if it matches the bit pattern in
Bit pattern matching in the received signal on the other hand
If no phase is detected, it is assumed that the frame phase is not detected.
The frame is shifted the phase again and the same CRC calculation and
Bit pattern match detection when bit pattern match is detected
And a frame synchronization detecting unit that repeats until the operation is completed .

[0006]

[0007]

Next, this embodiment will be described with reference to the drawings. FIG. 1 is a configuration diagram of one embodiment of the present invention. This embodiment includes a multiplexed signal transmitting circuit 1 as a transmitting side and a multiplexed signal receiving circuit 2 as a receiving side, and FIG. 1 also shows a transmission line 3 connecting the transmitting side and the receiving side. Shown.

The multiplexed signal transmission circuit 1 includes n channel signal transmission circuits 20-1, 20-2,..., 20-n for generating transmission signals for every n channels, and n channel signal transmission circuits. And a multiplexing circuit 30 for generating a multiplexed signal 301 obtained by time-division multiplexing each channel transmission signal. Channel signal transmission circuits 20-1 to 20
-N is a CRC operation circuit 21-1 to 2 which receives a data signal for each channel and performs a CRC operation on the data signal.
21-n and CRC code insertion circuits 22-1 to 22- which add the operation result to the transmission data as an error detection code.
n.

The multiplexed signal receiving circuit 2 outputs a CRC code detecting circuit 41 for detecting an error detecting code of the first channel of the frame for the multiplexed signal 301 inputted via the transmission line 3, and an output from the CRC code detecting circuit 61. A frame detection circuit 40 having a frame synchronization signal 421 and a frame synchronization counter circuit 42 for generating a channel identification signal 422 by inputting the detected signal 411 and multiplexing received according to the channel identification signal 422 from the frame detection circuit 40. A separation circuit 50 for separating / distributing the signal into channel reception signals for each channel, and inputting the separated channel reception signals and performing a CRC operation to detect error detection codes 711-1 to 711-n added on the transmission side , 71-n, and 711-1 to 71-n as error detection codes. 11-n based on to remove the error detection code included in the channel received signal takes a channel frame synchronization CRC code separating circuit 72-1,72
, 72-n, and n-channel signal receiving circuits 60-1, 60-2,..., 60-n.

Next, the operation of the embodiment of FIG. 1 will be described with reference to FIG. FIG. 2 is a time chart illustrating the operation of each unit in FIG.

[0011] Among the plurality of n channel signal transmission circuits 20-1 to 20-n of the multiplexed signal circuit 1 on the transmission side, the CRC operation is performed using a generator polynomial that is different from the other channels only in one channel. The channel using the different generator polynomial is set as the frame leading channel. This processing is performed, for example, by the channel signal transmission circuit 20-1 in FIG. 1, and the error detection code 211-1 generated by the CRC operation circuit 21-1 is inserted into the transmission data by the CRC code insertion circuit 22-1. The result is a CH (channel) 1 transmission signal 11-1. This is indicated by the CH1 transmission signal 11-1 in FIG. The inserted error detection code is indicated by C1 in the CH1 transmission signal 11-1. For other channels, the channel signal transmission circuit 20-
2 to 20-n, using the same generator polynomial,
The RC calculation is performed by the CRC calculation circuits 21-2 to 21-n, and the generated error detection code is changed to the CRC code insertion circuit 22-n.
2 to 22-n, which are inserted into the transmission data and shown in FIG.
The H2 transmission signals 11-2 to 11-n and the inserted error detection codes are indicated by C2 and Cn in the respective transmission signals. The channel frame period in which the error detection code is inserted into the transmission data does not need to be frame-synchronized between the channels as shown in FIG. 2 and may be asynchronous. The channel transmission signal of each channel is input to the multiplexing circuit 30 and time-division multiplexed to become the multiplexed signal 301 in FIG. The multiplexed state of the error detection codes C1, C2, and Cn of the respective channels is shown in the multiplexed signal 301 in FIG.
Indicated by C2 and Cn.

In the multiplexed signal receiving circuit 2 on the receiving side, an arbitrary frame is applied to the multiplexed signal 301 received using the generator polynomial used in only one channel in the CRC code detecting circuit 41 of the frame detecting circuit 40. A CRC operation is performed on the phase to detect an error detection code included in the multiplexed signal. The detection is first performed from an arbitrary frame phase, and a CRC calculation is performed in a unit of a channel frame period which is a period in which an error detection code is inserted. If the result matches a bit pattern in a received signal, the frame phase is changed. Consider it detected. If a matching bit pattern is not detected in the received signal, it is regarded as a frame phase non-detection, and the same CRC calculation and similar bit pattern matching detection are performed again by shifting the frame phase. This process is repeated until a bit pattern match is detected. When a bit pattern matching the CRC operation result is detected in the received multiplexed signal, the CRC code detection circuit 41
Outputs a detection signal 411 to the frame synchronization counter circuit 42. Thereby, the frame synchronization counter circuit 4
2 is reset to be in a state synchronized with the frame phase of the reception multiplexed signal 301. Further, a channel identification signal 422 is generated in the frame synchronization counter circuit 42 and output to the separation circuit 50.

The demultiplexing circuit 50 receives the multiplexed signal 30
1 for each channel according to the channel identification signal 422 received from the frame synchronization counter circuit 42, and the channel signal receiving circuits 60-1 and 60 corresponding to each channel.
−2,..., 60-n. , 60-n of the channel signal receiving circuits 60-1, 60-2, ..., 60-n
.., 71-n perform a CRC operation on the channel reception signal received from the separation circuit 50 using the respective generator polynomials, and calculate the result and the bit pattern in the channel reception signal. Are detected. The time when the CRC calculation result matches the channel reception signal is the channel frame phase synchronization state. Therefore, the CRC code separating circuit 72-
, 72-n, the error detection code is separated and removed from the channel reception signal, and only the channel data is output to the outside.

[0014]

As described above, according to the present invention, in a frame synchronization system for a data signal multiplex transmission apparatus, only one channel of a plurality of data signals having CRC check bits to be multiplexed is different from other channels. By adding a CRC check bit using a generator polynomial and detecting this CRC check bit on the receiving side, a circuit for adding / detecting a frame synchronization pattern is not required, and there is no need to separately add channel identification information. This has the effect that all of the capacity can be used for transmission of the data signal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of each unit in FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 multiplexed signal circuit 2 multiplexed signal receiving circuit 3 transmission line 20-1 to 20-n channel signal transmitting circuit 21-1 to 21-n CRC operation circuit 22-1 to 22-n CRC code insertion circuit 30 multiplexing circuit 40 frame detection circuit 41 CRC code detection circuit 42 frame synchronization counter circuit 50 separation circuit 60-1 to 60-n channel signal reception circuit 71-1 to 71-n CRC operation circuit 72-1 to 72-n CRC code separation circuit

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-278436 (JP, A) JP-A-58-220546 (JP, A) JP-A-58-220545 (JP, A)

Claims (1)

(57) [Claims] 1. A channel transmission signal generating means for adding an error detection code by a cyclic redundancy check operation to a data signal inputted from the outside and outputting as an n-channel transmission signal, and said channel transmission signal generating means. Multiplexing means for inputting the n-channel transmission signal according to the above and outputting the multiplexed signal as a time-division multiplexed signal, receiving the multiplexed signal from the multiplexing means, detecting the frame phase and the channel phase thereof, and Data signal multiplexing transmission including: a separating unit that separates the received signals from each other, and a channel received signal generating unit that inputs a channel received signal by the separating unit, performs error detection on the received signal and deletes an error detection code, and outputs a data signal to the outside. In the frame synchronization method used for the device, one of a plurality of channels included in the channel transmission signal generating means is included. The additional channels sends out as the added channel transmission signal to the data signal as an error detection code calculation results obtained by performing cyclic redundancy check operation by using a different generator polynomial only other channels Yaneru Data signal multiplexing
A channel transmission signal generating means for use as a frame leading channel in transmission, a multiplexing signal output from the multiplexing means being received via the transmission path, and a multiplexing signal generated using only one channel for the multiplexed signal. Performs a cyclic redundancy check operation using a polynomial and if the operation result matches the bit pattern in the received signal.
Although it is assumed that the frame phase has been detected,
If no matching bit pattern is detected, the frame position
Assuming that phase is not detected, the frame is shifted again and the same
CRC operation and bit pattern match detection
A frame synchronization detecting means for repeating until a pattern match is detected .