JP2702291B2 - Interrupt controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for an interrupt controller in a microcomputer.

[0002] The present invention is particularly applied to an interrupt controller which can designate a priority for an interrupt request.

In the present invention, the vector interrupt processing is
A macro service process is a process of interrupting the execution of a program by the processing means (CPU) when an interrupt occurs and starting another program in response to the interrupt request. The macro service processing means that the processing means does not branch to another program. This is a process of inserting a predetermined process corresponding to the generated interrupt.

[0004]

2. Description of the Related Art Generally, a microcomputer is configured as shown in FIG.
The configuration is as shown in FIG.

In FIG. 10, a microcomputer 1
Is based on a command read from a program memory in the memory 3 and is based on a central processing unit (hereinafter, referred to as a “CPU”).
2 executes the processing. In addition, the peripheral function block 5
Data writing or reading (hereinafter referred to as “access”) is controlled via U2 and the internal bus 6, and is controlled.
It operates independently of the CPU 2.

The peripheral function block 5 includes a timer and a serial interface block.
When the peripheral function block 5 detects a special state, such as when the timer reaches a certain value or when reception of serial data is completed, the peripheral function block 5
Generates an interrupt request signal 7 in order to notify this fact. The interrupt request signal 7 is transmitted to an interrupt controller (hereinafter, referred to as an interrupt controller).
It is called "INTC". ) 4 is input.

The INTC 4 performs a state in which an interrupt request may be sent to the CPU 2 (interrupt permission state), the presence or absence of another interrupt request, and the priority order of the interrupt request. An interrupt processing request signal to the CPU 2 (hereinafter referred to as an "INTRQ signal")
8 is sent. When detecting and receiving the INTRQ signal 8, the CPU 2 outputs various control signals 9 such as a signal indicating that the interrupt request has been received to the INTC 4.

The CPU 2 that has received the interrupt request executes the interrupt processing corresponding to the corresponding interrupt request signal 7, that is, the interrupt processing corresponding to the peripheral function block 5, interrupting the conventionally executed program.

Here, the priority order of the interrupt request signal 7 will be described. When there are a plurality of interrupt request signals 7, an interrupt request signal 7 (hereinafter referred to as “emergency interrupt request”) for which interrupt processing is to be performed urgently according to the type of the interrupt request signal 7 and an interrupt request signal that may be delayed 7 (hereinafter referred to as “general interrupt request”).

It is necessary to execute an emergency interrupt request corresponding to an emergency interrupt request by interrupting the interrupt process of the general interrupt request even during execution of the interrupt process of the general interrupt request.
Therefore, it is necessary to set a priority for each of the interrupt request signals 7. The interrupt processing for the interrupt request signal 7 set to a higher priority needs to be controlled so as to be interrupted even during the interrupt processing for the interrupt request signal 7 set to a lower priority. The above priority control is performed by the INTC4.

Next, FIG. 11 shows a configuration diagram of a conventional INTC 4, and the operation will be described with reference to a timing chart of FIG. FIG. 11 is an example of four levels of priority designation.

In FIG. 11, INT (0), INT
The (1), INT (2) and INT (3) signals are the interrupt request signals 7 output from the peripheral function block 5, and the respective interrupt request signal control devices IC (0) 11,
IC (1) 12, IC (2) 13, and IC (3) 14 (hereinafter referred to as "IC (0), IC (1), IC (2), IC
(3) ". ) Is entered. IC (0) 11,
Since the IC (1) 12, the IC (2) 13, and the IC (3) 14 have the same structure, only the IC (0) 11 will be described.

An interrupt request signal 7 is generated and INT (0)
When the signal becomes "1", an interrupt request flag latch (hereinafter referred to as "interrupt request flag") 112 is set to "1". CPU 2 uses internal address bus to set IC (0)
Outputs data to internal data bus 20, pointing to address 11;
When a write signal is generated, the output of the write signal control circuit 23
24 becomes “1”, and the data output from the CPU 2 is transferred from the internal data bus 20 to the mask bit latch (hereinafter, referred to as “mask bit”) 111 and the priority bit latch (hereinafter, referred to as “priority bit”) 116 and 117. Written. When the content of the mask bit 111 is "1", the output of the AND circuit 114 is
Fixed to “0” by 119, but mask bit 11
When the content of 1 is “0”, the output of the AND circuit 114 is
It is determined by the EI signal and the interrupt request flag 112.
Here, the EI signal is a vector interrupt enable / disable signal.
When the I signal is "1", interrupt processing is permitted.

The priority bits 116 and 117 are bits for specifying the priority of the interrupt request signal 7 and are four levels of two priority bits 0, 1, 2, and 3 (0 is the highest priority level and 3 Is the lowest). The priority bit 116 is the upper bit, and 117 is the lower bit.

The comparator 118 compares the output of the scan counter 15 with the contents of the priority bits 116 and 117, and sets the output to "1" when they match. Therefore, the mask bit is "0" and the EI signal is "1".
At this time, when the INT (0) signal becomes "1" and the output of the comparator 118 becomes "1", the RA signal which is the vector address table creation signal as the output of the AND circuit 115 becomes "1" and the OR circuit 22 Is also "1".

The CLK signal is a timing clock signal. The output circuit 18a reads the output of the OR circuit 22 at the timing when the CLK signal is "0", and then the CLK signal becomes "1".
Output when.

The scan counter 15 is a counter for scanning the priority order, and normally repeats the scan signals 28 and 29 in order to scan the priority level, such as "0 → 1 → 2 → 3 → 0...". Output. However, it is cleared when the contents of the scan counter 15 match the contents of the output 30 of the running priority register (hereinafter referred to as "ISPR") 16 and starts counting from "0". If the content of ISPR16 is "2", "0 →
1 → 2 → 0 → ... ”. When the output of the OR circuit 22 is "1", the scan counter 15 suspends the counting operation and holds the content.

The ISPR 16 stores the priority of an interrupt request for which the CPU 2 is performing interrupt processing.
When the OEVC signal which is one of the two control signals 9 is "1", the scan signals 28 and 29 which are the outputs of the scan counter 15 are read. Here, the OEVC signal is a vector address table corresponding to the generated interrupt.
This is a vector address ISPR storage signal that outputs an address of 17 and stores the priority of the interrupt generated in the ISPR 16. However, although the contents previously stored in the ISPR 16 are kept as they are, the higher priority level is output to the output 30 of the ISPR 16. Also, OE
When the VC signal is output, IC (0) 11, IC (1) 1
2. AND circuit 115 of IC (2) 13 and IC (3) 14
When the output of the AND gate corresponding to "1" becomes "1", the corresponding interrupt vector address is stored in the internal data bus from the vector address table 17 via the output buffer 19.
Read to 20. The CPU 2 determines the type of the interrupt request signal 7 based on the interrupt vector address.

When the CLRIF signal which is an interrupt request flag clear signal for clearing the interrupt request flag 112 which is one of the control signals 9 of the CPU 2 becomes "1", the output of the AND circuit 110 becomes "1" and the interrupt request is made. Flag 112
Is reset to “0”. The RESET (reset) signal is a signal for initializing the INTC4.
When the signal becomes "1", the interrupt request flag 112 becomes "0", the mask bit 111 becomes "1", and the priority bits 116 and 117 become "1" and "1".
16 is initialized to a state where no interrupt processing is executed.

Now, INT (0), INT (1), IN
For the T (2) and INT (3) signals, the mask bits 111 are "0", "0", "0", "0",
Priority bits 116 and 117 are "1, 0" (priority level 2), "1, 0" (priority level 2),
The case in which “0, 0” (priority level 0) and “0, 1” (priority level 1) are set will be described with reference to the timing chart of FIG.

In FIG. 12, when the INT (0) signal is generated at the timing T2, the output of the scan counter 15 indicates the priority level 3 at the timing T4.
And the RA signal at the output of the AND circuit 115 becomes "1". Then, the output of the OR circuit 22 becomes "1", and the content of the scan counter 15 stops at level 2. At timing T5, the INTRQ signal becomes "1", the INT (0) signal is accepted, and an interrupt process is requested to the CPU 2.

In response to the INTRQ signal, the CPU 2
The EVC signal is set to “1” at timing T6. At the timing T7, the output of the ISPR16 indicates the priority level 2. If the CPU 2 sets the CLRIF signal to "1", the interrupt request flag 112 is cleared to "0". Then, the outputs of the AND circuits 114 and 115 become "0", and the output of the OR circuit 22 also becomes "0". Then T
At 8 timings, the contents of the scan counter 15 are
Since it matches the output of 16, the scan counter 15 is cleared and scanning starts from the priority level 0.

When the INT (2) signal is generated at the timing T10, the output of the scan counter 15 matches the content of the priority bit in the IC (1) 12 at the timing T11, so that the INTRQ signal becomes "1" at the timing T11. , Priority level 0 INT (2) signal is received. Then, after T11 timing, the scan counter 15
Is fixed to “0”. Next, even if the INT (3) signal is generated at the timing T14, since the content of the scan counter 15 is "0", no coincidence output is generated in the comparator in the IC (3) 14, so that the currently accepted signal is received. INT
(2) An INT (3) signal (priority level 1) having a lower priority level than a signal (priority level 0) is not accepted.

At the end of the interrupt processing, the CPU 2
Generate a CLRIP signal that clears the highest priority level stored in R16. C at T15 timing
When PU2 sets the CLRIP signal to “1”, the ISPR16
Resets the currently output priority level 0 at the timing T16 and outputs the immediately preceding priority level 2. Then, the scan counter 15 sequentially scans again with the contents of “0 → 1 →”.

As described above, conventionally, interrupt priority control is performed by sequential scanning of the priority level by the scan counter, and interrupt processing of a high priority interrupts even during interrupt processing of a low priority level. I can do it. Also, during the interrupt processing with a high priority level, an interrupt processing request with a low priority level cannot be executed.

[0026]

However, in the INTC provided with the conventional interrupt priority control means, since the priority is sequentially scanned and searched, if the priority level increases, it takes time for the scanning operation to complete one cycle. There is a disadvantage that it takes a lot. In recent microcomputers, the number of interrupt request signals has been increased, and the number of priority designation levels has been increased to 8 to 16 in order to perform fine control. If the priority level is eight levels, eight rounds of scanning require eight timings.
In this case, the time from when the interrupt request signal is generated to when it is accepted (hereinafter referred to as "response time") is required to be a maximum of 16 timings, which is slow. Such a conventional INT
C has a drawback that it cannot be applied to microcomputers corresponding to the real-time control field, which has recently been applied because of the problem of response time.

An object of the present invention is to provide an interrupt controller which eliminates the above-mentioned disadvantages and can reduce the response time even when the number of priority designation levels increases.

According to the present invention, each of a plurality of interrupt request signals
Set any priority level out of 2 ⁿ levels for
Multiple n-bit priority registers
N bits for storing the priority level of the interrupt processing being executed
Interrupt priority level register and interrupt priority level
N + 1 timing signal for scanning
Generated stage counters and all interrupts generated
Request signal contents of the priority register and the execution
Starting from the most significant bit
Compared to the least significant bit at n timings and the highest priority
Detects the highest interrupt level and assigns the highest priority
When there are a plurality of interrupts of the
One predetermined timing following the imming
According to the priorities, the highest priority interrupt level
Means for selecting one of the interrupts
Controller and further transmits the interrupt request signal.
Means for making a macro service processing request, wherein the n
Check whether there is a macro service processing request during the timing period.
If a macro service processing request is detected,
Macro service processing request prior to all interrupts
Request means for outputting the request as an interrupt request signal .

The present invention also provides a plurality of interrupts to be input.
Means for controlling the priority of the request signal and outputting it to the processing means
Interrupt controller in an information processing device equipped with
And either vector interrupt processing or macro service processing
Processing specifying means for specifying whether each interrupt request is input
Set 2 ⁿ (n is a natural number) priority levels for signals
This priority level and the settings for each device
Priority designation and the process designation from the process designation means
To detect interrupt requests at a maximum of n timings
Number of interrupt request signal controllers and priority levels
A switch that sequentially and repeatedly generates n timing signals
Tage counter and interrupt currently being executed by the processing means
Running priority register that stores the priority level of the process
And the current execution according to the output of this running priority register.
A currently running interrupt controller that controls the interrupt
The interrupt request signal control device comprises: an interrupt request signal;
Priority bits to set the priority level of the
And Torejisuta, compared with the storage contents of the priority level and the running priority registers of all of the interrupt request signal generated in the n timing from the top level sequentially performed toward the lowest level, all the series of means for detecting an interrupt request having the highest priority level comparison, the highest priority in parallel with the timing of the scanning operation in accordance with a predetermined order when the process specifying means specifies the macro service processing Means for detecting an interrupt request.

In the present invention, the information processing device is preferably a microcomputer.

[0031]

The interrupt signal control device sets 2 ⁿ (n is a natural number) priority levels to each input interrupt request signal, and sets the priority levels of all the interrupt request signals generated at n timings. The comparison with the contents stored in the executing priority register is performed in order from the highest level to the lowest level, and an interrupt request having the highest priority level is detected in all the series of level comparisons. On the other hand, if the processing is vector processing, for example,
Is output, the detected interrupt request is issued, and in the case of the macro service processing, the interrupt request having the highest priority is detected in parallel with the timing of the scanning operation in a predetermined order.

Therefore, the highest priority of all the interrupt request signals can be detected at a maximum of n times (3 when the priority level is 8 levels (n = 3)), and the response time is greatly reduced. It is possible to do.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 10 is a block diagram showing a main part of a microcomputer to which the present invention is applied.

In the first embodiment, the microcomputer 1
Interrupt request signal 7 input from peripheral function block 5
INT (0), IN which are four interrupt signals
An INTC 4 having a unit for controlling the T (1), INT (2) and INT (3) signals and outputting the signals to the CPU 2 as a processing unit.

The feature of the present invention is as follows.

A latch 48 as processing specifying means for specifying one of a vector interrupt processing and a macro service processing;
INT (0) to IN which are input interrupt request signals
The T (3) signal is set with 2 ⁿ (n is a natural number) priorities, and the maximum is determined by the set priority levels, the priorities predetermined for each device, and the processing designation output from the latch 48. Four interrupt request signal control devices (hereinafter referred to as “ICs”) that detect an interrupt request at n timings
(0) to IC (3) ". 11) to 14; a stage counter 32 for sequentially generating n timing signals for scanning the priority level; and a running priority register (hereinafter, referred to as "priority level") for storing the priority level of the interrupt processing currently being executed by the CPU 2. ISPR ”). 16 and this ISP
A currently executing interrupt control device (hereinafter referred to as "ICISPR") 40 for controlling the currently executing interrupt in accordance with the output of R16.

In FIG. 1, 17 is a vector address table, 18a is an output circuit for outputting an INTRQ signal (interrupt processing request signal), 19 is an output buffer, 20 is an internal data bus, 23 is a write control circuit, and 36 38 are p-channel MOS transistors.

Next, the details and operation of each component will be described with reference to FIGS. 2, 3 and 4. FIG. Here, FIG. 2 is a detailed circuit diagram of the stage counter 32, and FIG. 3 is an IC (0) 11 to IC
(3) Detailed circuit diagram of 14 (interrupt request signal control device), and FIG. 4 is a detailed circuit diagram of ICISPR40 (currently executing interrupt control device).

In FIGS. 1 and 3, means indicated by the same reference numerals as in FIG. 11 of the conventional example perform the same operations. Here, only different portions will be described.

In FIG. 1, a stage counter 32 generates STG (1), STG (2), STG (3) and STG (0) signals which are timing signals for scanning the priority level of an interrupt request, and performs timing control. I do.
ISPR16 is IC (0) 11, IC (1) 12, IC
(2) The priority level output from the IC 13 and the IC (3) 14 is read at the timing when the OEVC signal becomes "1" when the output of the latch 48 which becomes "1" during macro service is "0". In synchronization with the CLK signal, the highest priority value stored in the ISPR 16 is output as the encoded ISPR (1) signal 42 and ISPR (0) signal 41. When no interrupt request signal is received, the ISPR 16 outputs “0” when the priority is not stored in the ISPR 16 and outputs “1” when the priority is stored. The ENISPR signal 43 as the presence / absence identification signal is set to “0”. ISPR16
If the priority level is stored in the
The R signal 43 becomes "1". The ISPR 16 clears the current priority level by the CLRIP signal which is the highest level clear signal in the ISPR for clearing the latch for specifying the macro service, and outputs the immediately preceding priority level. Here, the ISPR (1) signal 42 has a weight of “2”,
The ISPR (0) signal 41 indicates a weight of "1".

The output circuit 18a outputs the timing signal STG
(3) C of signal or STG (1) signal timing
When the LK signal is "0", the output of the OR circuit 22 is read and output at the timing of the next CLK signal, and the INTRQ signal is output via the AND circuit 34 at the timing of the STG (0) signal. The output circuit 18a is reset to "0" by a RESET signal, a CLRIF signal as an interrupt request flag clear signal, and a CLRMS signal as a macro service interrupt request bit latch clear signal. The latch 48 reads the output of the OR circuit 22 when the clock at the timing of the STG (1) signal is “0” and outputs it at the timing of the next CLK signal, and outputs the same via the AND circuit 49 at the timing of the STG (0) signal. An MSINTRQ signal, which is a macro service interrupt processing request signal, is output. MSIN
The TRQ signal is a signal for outputting a request to execute a macro service process to the CPU. The latch 48 is set to “0” by the RESET signal, the CLRIF signal, and the CLRMS signal.
Is reset to The CLRMS signal is issued during execution of the macro service, and clears a process designation bit latch (hereinafter, referred to as an “MSINT bit”) 160 that designates an interrupt for the macro service.

When the CLK signal is "1", the p-channel MOS transistors 36, 37 and 38 become conductive when the output of the inverter 33 becomes "0", and the V _DD level, that is, "1" indicates that the vector interrupt has occurred. S which is an interrupt request detection signal
This signal is applied to the LPRH signal and the CM (1) signal and the CM (2) signal, which are priority determination signals of the interrupt.
A capacitor (not shown) is added to the SLPRH signal, the CM (1) signal, and the CM (2) signal, and the CLK signal is charged to “1”, “1”, “1” while the CLK signal is “1” ( Hereinafter, it is referred to as “precharged”.) IC (3) 14
Of the IC (2) 13 and the CMOT signal of the IC (2) 13 in the same manner.
(1) 12 CMIN signals, IC (1) 12 and IC (0) 11
And IC (0) 11 connected to ICISPR40, and IC
The CMOT signal of the ISPR 40 is an n-channel MO that becomes conductive when the output of the inverter 33, which is the inverted clock, is "1".
Connected to GND (ground) via S transistor 52.
The CMIN signal of the IC (3) 14 is a stage counter.
STG when specifying macro service of 32
(1) Connect to a DMS signal which is a macro service processing designation signal input in synchronization with the signal.

FIG. 2 is a detailed circuit diagram of the stage counter 32.

In the initial state, the RESET signal is "1"
When the CLK signal becomes “0”, the latch 321 is “1”, the latches 323 and 325 are “0”,
Latch 327 is initialized to "0". Then, the next CLK
At the signal timing, the latch 322 is set to “1” and the latch 324
And 326 become “0”. Next, when the CLK signal becomes "0", the STG (1) signal is output by the AND circuit 342. When the RESET signal becomes "0", the output "1" of the latch 322 becomes "0" through the AND circuit 330 when the CLK signal becomes "0".
Is read into the latch 323. Similarly, when the CLK signal is "0", the output of the latch 323 is read by the latch 324 and becomes "1". When the CLK signal is "0" via the AND circuit 331, the output is read into the latch 325.

If the CLRIF signal and the CLRMS signal are "0", the SLPRH signal is "1", and the DMS signal is "0", the output of the inverter 341 becomes "0". Since it is "0", the RS latch 327 remains "0". AND circuit 339 and
340 is "0", and the OR circuit 338 is "0". When the CLK signal becomes "0", "0" is read into the latch 321 via the OR circuit 329. Next, when the CLK signal becomes "1", the latch 322 becomes "0" and the latch 324 becomes "1".
When the CLK signal becomes "0", the STG (2) signal becomes "1".
become. When the next CLK signal is “0”, the latch
325 becomes "1", and when the CLK signal becomes "1", the latch 325 becomes "0", the latch 326 becomes "1", and when the CLK signal is "0", the STG (3) signal becomes "1". SL
While the PRH signal is "1", the latches 321 and 322 and the latch 32
2, 324 and the latches 325, 326 alternately repeat "1" and "0" sequentially, so that the STG (1) signal
The G (2) signal and the STG (3) signal are output in order. When the SLPRH signal becomes “0”, the inverter 341
Is "1", the output of latch 326 is "1", and C
When the LK signal is "0", the RS latch 327 is set to "1". Next, when the CLK signal becomes “1”, the latch 328 is set.
Becomes “1”, and the STG (0) signal is output. SLP
When the RH signal becomes "0", the AND circuit 339 becomes "0", so that the OR circuit 338 becomes "0" and the STG (1) signal is not output until the CLRIF signal or the CLRMS signal becomes "1". Next, when the CLRIF signal becomes "1", the AND circuit 340 becomes "1", and when the CLK signal becomes "0", the latch 321 becomes "1". CLRIF
Since the OR circuit 333 becomes "1" by the signal, the RS latch 327 is reset to "0". Therefore, STG (0)
The STG (1) signal is output following the signal.

Next, when the DMS signal is "1", the inverter 350 becomes "0" and the AND circuit 330 becomes "0" to suppress the generation of the STG (2) signal and the STG (3) signal. When the STG (1) signal becomes "1", the AND circuit 351
Becomes "1" and the RS latch via OR circuit 352
With the 327 and the latch 328 set to "1", the STG (0) signal is output. Since no STG (3) signal is generated,
The STG (1) signal is not output until the CLRIF signal or the CLRMS signal becomes “1”.

Next, when the CLRMS signal becomes "1",
Since the AND circuit 353 becomes “1”, the CLK signal becomes “0”.
Then, the latch 321 becomes "1". Since the OR circuit 333 becomes "1" by the CLRMS signal, the RS latch 327 is reset to "0". Therefore, the STG (1) signal is output following the STG (0) signal.

Next, the operation of the IC (0) 11 will be described with reference to FIG. INT (0) signal is input and mask bit
When 111 is "0", the interrupt request flag 112 is "1", the EI signal is "1", and the MSINT bit 160 is "0", the output of the AND circuit 114 becomes "1". MSINT bit 16
0 is a bit for designating a macro service process when "1", and a bit for designating a vector interrupt when "0".
It is reset to “0” by the MS signal. Priority bit 116 has a weight of “2” and priority bit 11
7 is the weight of "1".

The content of the priority bit 116 is "0"
At this time, the output of the inverter 120 becomes "1". STG
(1) When the signal becomes "1", the output of the AND circuit 121 becomes "1" at the timing when the CLK signal becomes "0", the n-channel MOS transistor 122 becomes conductive, and the CM (1) signal becomes "0". The CM (1) signal is precharged when the CLK signal is "1" and is "1", but becomes "0" when the AND circuit 121 becomes "1". At the same time, the RS latch 126 via the OR circuit 124 and the AND circuit 125
Is set to “1”.

Next, when the CLK signal becomes "1", the latch
When the signal 127 becomes "1" and the STG (3) signal becomes "1", the AND circuit 141 becomes "1". When the inverter 142 after passing through the OR circuit 166 becomes "0", the n-channel MOS transistor 144 does not conduct, and the p-channel MOS transistor 14 which becomes conductive by "0" of the previous clock.
CMIN signal precharged in 6 and ICISPR40
The output of the inverter 145 becomes "1" when the CMOT signal connected to GND via "1" is "0", the AND circuit 143 becomes "1", and the RA for generating the vector address table 17 becomes "1". Output a signal.

When the STG (2) signal becomes "1", when the priority bit 117 is "0" and the latch 127 is "1", the AND circuit 12 is activated at the timing when the CLK signal is "0".
8 becomes "1", the n-channel MOS transistor 129 conducts, and the CM (2) signal becomes "0". The CM (2) signal is precharged when the CLK signal is "1" and is "1", but becomes "0" when the AND circuit 128 becomes "1".

The AND circuit 132 has a priority bit
117 is “1”, CM (2) signal is “0” and STG (2)
When the signal is "1", the output is "1". AND circuit 13
2 output is “1” or RESET signal is “1”,
Or CLRIF signal is "1" or CLRMS
When the signal is “1” or the RA signal is “0”, ST
When the G (3) signal is "1", the CLK signal is "0", and the AND circuit 149 is "1", the output of the OR circuit 140 becomes "1", and when the next CLK signal becomes "0", RS Latch 126
Is reset to “0”. When the output of the OR circuit 140 is "0", the output of the inverter 133 becomes "1",
The output of the latch 127 is "1" and the STG (3) signal is "1".
At this time, the output of the AND circuit 135 becomes "1", so that the n-channel MOS transistor 134 conducts, and the SLPRH signal becomes "0".

When the output of the latch 127 is "1" and STG (1)
When the STG (2) signal and the STG (3) signal are "0", that is, when the STG (0) signal is "1", the AND circuit 136 becomes "1" and the priority bit 11
The outputs of 6 and 117 are read out on PR (1) and PR (0) signals via output buffers 138 and 139, respectively.

Next, when the INT (0) signal is input when the MSINT bit 160 is "1" and the mask bit 111 is "0", the output of the AND circuit 162 becomes "1".
When the STG (1) signal becomes "1", the AND circuit 165
Becomes “1” and the inverter after passing through the OR circuit 166
When 142 becomes "0", n-channel MOS transistor 14
4 is not conducting, and the CMIN signal pre-charged by the p-channel MOS transistor 146, the ICISPR 40, and the n-channel MOS which have been conducted by the previous CLK signal "0".
When the CMOT signal connected to GND via the transistor 52 is "0", the output of the inverter 145 becomes "1", the AND circuit 143 becomes "1", and outputs the RA signal.

Latches 167 and 168 apply the RA signal to ST
It is captured by either the G (1) signal or the STG (3) signal. When the latch 168 is "1", the CRLIF signal is input, the interrupt request flag 112 is cleared, and when the CLRMS signal is used, the MSINT bit 160 is cleared. At the same time, the latch 167 is cleared. In the case of the CLRMS signal, since the interrupt request flag 112 is not cleared, the operation for determining the priority of the next vector interrupt is started immediately.

Next, ICISPR40 will be described with reference to FIG. In FIG. 4, the circuits having the same reference numbers in the last two digits as FIG. 3 perform the same operation. The difference between FIGS. 3 and 4 is that the output of the AND circuit 114 in FIG. 3 is replaced by the ENISPR signal, and the output of the priority bits 116 and 117 is
(1) The signal and the ISPR (0) signal are replaced by AND circuits 110, 114, 135, 136, 162, and 164.
, N-channel MOS transistor 134 and inverter
119 and 133, NOR circuit 137, OR circuit 113, 16
1, 163, 166 and 169, mask bit 111 and interrupt request flag 112, latches 160, 167 and 168
Are deleted, and only the RA signal and the SLPRH signal are not provided.

Next, the operation of FIG. 1 will be described with reference to a timing chart shown in FIG.

INT (0), INT (1), INT
Each mask bit 111 of (2) and INT (3) signals
Are replaced by “0”, “0”, “0”, “0” respectively, MS
When the INT bit 160 is "1", "0", "0",
At “0”, the priority bits 116 and 117 are “1, 0” (priority level 2), “1, 0” (priority level 2), “0, 0” (priority level 0),
Consider a case in which “0, 1” (priority level 1) is set. (The same as the conventional example except for the addition of the MSINT bit) The EI signal is also "1". STG
(1) The signal, the STG (2) signal, and the STG (3) signal sequentially and repeatedly output "1" and "0" alternately.
When the INT (1) signal becomes "1" at the timing of the TG (3) signal, the interrupt request flag 112 becomes "1".
At this time, since the interrupt request signal has not been received at all and the output ENISPR signal 43 of the ISPR 16 is "0", the AND circuit 421 of the ICISPR 40 remains "0". Similarly, IC (0) 11, IC (2)
Since the outputs of the circuits corresponding to the AND circuit 121 of the IC 13 and the IC (3) 14 are "0", "0", and "0",
(1) The signal remains "1". Then, at the timing T4, the RS latch 126 becomes "1" at the timing when the CLK signal is "0".

At the timing T6, the output of the latch 127 becomes "1", and at the timing when the STG (3) signal becomes "1", the output of the AND circuit 141 becomes "1".
The CMIN signal precharged with the K signal being “1” is n
Cut off by channel MOS transistor 144, ICISP
Since the inverter R40 and the inverter 142 of the IC (0) 11 are "1", the output of the inverter 145 directly connected from GND, that is, the RA signal becomes "1". AND circuit 128
Is "0" because the priority bit 117 is "1", so that the CM (2) signal becomes "1". The output of the AND circuit 132 does not reset the RS latch 126 because the CM (2) signal becomes "1" and the inverter 131 becomes "0". Since the RA signal corresponding to the INT (1) signal is "1", when the CLK signal becomes "0" at timing T6, the output circuit 18a becomes "1". Also, STG
(3) At the timing when the signal becomes “1”, the AND circuit 135
Is "1" and the SLPRH signal is "0".
Then, an STG (0) signal is generated at timing T7.

At the timing T7, the STG (0) signal is "1" and the output of the output circuit 18a becomes "1".
The NTRQ signal becomes "1", requesting the CPU 2 for interrupt processing.

Next, at the timing T9, the CPU 2
When the EVC signal is output, the vector address corresponding to the INT (1) signal is read out onto the internal data bus 20 via the output buffer 19, and the contents of the priority bits 116 and 117 of the INT (1) signal are changed to PR.
(1) and read on PR (0) signal
Is read in.

At the timing T10, the output of the ISPR16 becomes the priority level 2, the ISPR (1) signal 42 is "1", the ISPR (0) signal 41 is "0", and the
The PR signal 43 becomes "1". In addition, CLRI
An F signal is output. When the CLK signal becomes “0”, RS
Latch 327 goes to "0" and latch 328 goes to "0". Next, at timing T11, an STG (1) signal is generated.

When the INT (2) signal is generated at the timing T13, the circuit corresponding to the AND circuit 121 of the IC (2) 13 becomes "1" at the timing T14,
At the timing when the signal is "0", the circuit corresponding to the RS latch 126 of the IC (2) 13 becomes "1". AND circuit 421
Is "0" and the output of the AND circuit 425 is "0", the RS latch 426 remains "0".

Hereinafter, similar to the case of the INT (1) signal,
The STG (2), STG (3) and STG (0) signals are generated at timings T15, T16 and T17, and the INTRQ signal becomes "1" at the timing (T17) following T16.
Next, when the CPU 2 sets the OEVC signal to "1", the ISPR
16 reads priority level 0. That is, an interrupt with a higher priority is accepted. The stage counter 32 outputs the STG (1) signal in response to the CLRIF signal.

Next, when the INT (3) signal is generated at the timing T19, the INT (3) is generated at the timing T20.
The priority check corresponding to the signal starts. At T20 timing, the ISPR (1) signal which is the output of ISPR16
42 and the ISPR (2) signal 43 are each "0",
Since it is “0”, the AND circuit 421 becomes “1”. Then, since the output of the circuit for the AND circuit 125 of the IC (3) 14 remains "0", the circuit for the RS latch 126 of the IC (3) 14 remains "0", and even when the timing of T22 is reached, the IC ( 3) The RA signal at 14 remains "0". Also, no INTRQ signal is generated at the timing T23. Therefore, the INT (3) signal of the priority level 1 cannot be interrupted during the interrupt processing of the INT (1) signal of the priority level 0.

When the CLRIP signal is output at the timing T23, the content of the ISPR16 becomes the immediately preceding priority level 2. Next, when the INT (0) signal is generated at the timing T27, the STG (1) signal is generated at the timing T29,
The output of the AND circuit 165 becomes "1", the RA signal is output in the same manner as the INT (1) signal, and the INTRQ signal and the MSINTRQ signal are generated at T30. Next, CPU 2
When the EVC signal is set to "1", the vector address table 17
Is output to the internal data bus 20. At this time,
Since the latch 48 is "1", the AND circuit 51 does not become "1", so that the value of the ISPR 16 does not change. Next, CLR
When the MS signal is output, the MSINT bit 160 is cleared, and the MSINT bit 160 is output from the STG (1) signal of the stage counter 32 at the same time. Start priority determination.

At timing T35, the output IS of ISPR16
Since the PR (1) signal 42 and the ISPR (0) signal 41 are "1" and "0", respectively, the AND circuit 421 becomes "0" and the CM (1) signal becomes "1". When the output of the AND circuit 425 becomes "1", the RS latch 426 is set, and the CLK signal becomes "1", the output of the latch 427 becomes "1". Since the ISPR (0) signal 41 is "0", the output of the AND circuit 428 becomes "0" and the CM
(2) The signal remains "1". Therefore, the AND circuit
Since the output of 432 remains "0", the output of the OR circuit 440 becomes "0" and the RS latch 426 is not reset.

Since the priority level (level 2) of the INT (0) signal is the same, the priority bits 116 and 11
7 are the same, and the circuit of IC (0) 11 operates in the same manner and latches.
The output of 127 becomes "1". STG (3) signal is "1"
At this timing, the outputs of the AND circuit 441 of ICISPR40 and the AND circuit 141 of IC (0) 11 become "1", the outputs of the inverters 442 and 142 become "0", and the n-channel MOS transistors 444 and 144 are cut off. You. Accordingly, the G of the CMIN signal and the CMOT signal precharged at the timing when the CLK signal becomes "1" is set.
Only the CMOT signal of the ICISPR40 connected to the ND becomes “0”, and the CMIN signal of the ICISPR40 and I
CMIN signal and CMOT signal of C (0) 11 are "1"
Will remain. The output of the inverter 445 of the ICISPR40 becomes “1”, the output of the AND circuit 443 becomes “1”, the output of the inverter 448 becomes “0”, the output of the AND circuit 449 becomes “0”, and the output of the OR circuit 440 becomes Becomes “0”. In IC (0) 11, the output of inverter 145 is "0"
Since the output of the AND circuit 143 becomes “0”, R
The A signal remains at "0". At the same time, the output of the inverter 148 becomes "1", the output of the AND circuit 149 becomes "1", the output of the OR circuit 140 becomes "1", and the RS latch 12
Reset 6 That is, the interrupt of the INT (0) signal is not accepted, and the INTRQ signal is not output. That is, the same priority level is not accepted.

Next, although no timing chart is shown,
When no interrupt is currently accepted, the priority level 0 and the priority bits 116 and 117 are set to "0,
When the INT (0) signal and the INT (1) signal of "0" are generated, that is, when two interrupt signals of the same priority level are generated, the IC is similarly set at the timing when the STG (3) signal is "1". Since the output of the AND circuit 141 of (0) 11 and the IC (1) 12 becomes "1" and the output of the inverter 142 becomes "0", the n-channel MOS transistor 144 is cut off. Now, since no interrupt is accepted, the output of the latch 427 of ICISPR40 is "0", and the output of the AND circuit 441 is as follows.
Since the output of the inverter 442 becomes "0" at "0" and the n-channel MOS transistor 444 is conductive, the IC
The (0) 11 CMOT signal is connected to GND and becomes "0", and the CMIN signal of IC (0) 11 and the CM of IC (1) 12
Since the OT signal and the CMIN signal are "1", IC (0)
Only the output of 11 inverters 145 is "1", and AND circuit
143, that is, the RA signal for the INT (0) signal is "1". However, the inverter 14 of the IC (1) 12
5 becomes "0", and the output of the AND circuit 143, that is, the RA signal for the INT (1) signal becomes "0".
Therefore, the INT (0) signal of the same priority level and the IN (0) signal
Even if the T (1) signal occurs simultaneously, the INT (0) signal has priority.

As described above, the control in which the processing of the interrupt request having the higher priority can be interrupted during the processing of the interrupt request having the lower priority level is performed by scanning the priorities by weight in descending order of the priority bit weight. Can respond faster than the conventional INTC, and when an interrupt of the same priority level as that of the interrupt currently being accepted occurs, it will not accept the interrupt, or will receive two or more interrupts of the same priority level. Are performed at the same time, an interrupt with a higher priority (hereinafter, referred to as a "default value") well set in the circuit is received and an interrupt with a lower default value is not accepted. In addition, it can support macro service processing. Therefore,
In the present embodiment, high-speed and flexible response to various interrupt request processes of various interrupt requests can be achieved.

FIG. 6 is a block diagram showing a second embodiment of the present invention. FIG. 7 is a detailed circuit diagram of the stage counter 32.
FIG. 8 shows IC (0) 11, IC (1) 12 and IC (2) 1.
3. Detailed circuit diagram of IC (3) 14 and FIG.
It is a detailed circuit diagram of ISPR40.

In the second embodiment, the priority levels are eight levels as compared with the first embodiment, but the control is exactly the same except for the control of the eight levels. Circuits with the same reference numbers perform similar operations.

In FIG. 6, the difference from FIG. 1 is that the STG (4) signal is output from the stage counter 32 and the IC
(0) 11, IC (1) 12, IC (2) 13 and IC
(3) The CM (3) signal is input to 14 in common. CM (3) signal includes CM (1) signal and CM
(2) p-channel MOS that is precharged in the same way as a signal
The transistor 45 is connected. Also, IC (0) 1
1, IC (1) 12, IC (2) 13, and IC (3) 14 are all connected to a PR (2) signal 46, and the PR (2) signal 46 is
It is input to SPR16. ISPR from ISPR16
(2) Signal 44 is output to ICISPR40.
The PR (2) signal 46 is a signal indicating the weight of the priority bit “4”.

FIG. 7 is different from FIG.
7, latches 345 and 346, and an AND circuit 349 are added, and the STG (4) signal is added as an output. The stage counter 32 operates in substantially the same manner as in FIG.
Since the STG (4) signal is generated next to the STG (3) signal, normally, the STG (1) → the STG (2) → the STG (3)
Timing signals are generated as shown in → STG (4) → STG (1).

FIG. 8 differs from FIG. 3 in that the CM (3) signal and the STG (4) signal, the inverters 150 and 15
4, AND circuits 151 and 153, and n-channel MOS
A transistor 152, an output buffer 138, and a priority bit 115 have been added. Also, the NOR circuit 13
7, an STG (4) signal is input. Inverter 12
At 0 and 123, priority bits 115 and 116 are input instead of priority bits 116 and 117, respectively.

The priority bit 115 indicates a weight of "4", and the priority bits 115, 116 and 117 indicate eight levels of priority from 0 to 7. Therefore, in the scan of the priority level, the weight of “4” is scanned by the STG (1) signal, the weight of “2” is scanned by the STG (2) signal, and the weight of “1” is scanned by the STG (3) signal.

In the operation shown in FIG. 8, when the priority bit is 1
3 except that the bit is added, since the RS latch 126 is not reset to "0" when the STG (4) signal is generated, the SLPRH signal becomes "0". ) Signal is generated, and the interrupt request is accepted. Further, when the macro service processing is performed with the MSINT bit being “1”, the macro service is selected at the timing of the STG (1) signal. A request occurs.

FIG. 9 differs from FIG. 4 in that the CM (3) signal and the STG (4) signal, inverters 433, 450 and 454, AND circuits 435, 451 and 453, n-channel MOS transistors 434 and 452 Has been added. The ISPR (2) signal is output from the inverter 420
And the ISPR (1) signal is sent to the inverter 423
(0) The signal is input to the inverter 450. Like FIG. 8, FIG. 9 shows a configuration in which scanning is performed at the priority level from the weight of “4”.

As described above, in the second embodiment, “4”
, The weight of “2” → the weight of “1” and the eight levels of priority are controlled by three timings.
At the timing when the signal is output, the ICI
Connect the SPR40 CMOT signal to GND, and
(0) 11, IC (1) 12, IC (2) 13 and IC
(3) By connecting the 14 CMOT signals and the CMIN signals, priority control using default values can be performed at one timing for two or more interrupt requests of the same priority level.

As described above, the priority level is 16 levels (2
⁴ ) It is easily understood that scanning can be performed at four timings. Therefore, it is clear that the priority order of 2 ⁿ levels can perform the priority determination control for the interrupt request at n timings. Also, it is possible to process macro service processing requests promptly even if the priority level increases.

[0082]

As described above, according to the present invention,
When the number of priority levels is within 2 ⁿ , scanning of priority levels is sequentially performed in the order of 2 ⁿ → 2 ^n-1 →... 2 and detection of a macro service is performed in parallel with the timing of the scanning operation. By doing so, it is possible to detect the highest priority interrupt among all the interrupt request signals at the maximum number of timings of n times. It is possible to provide an interrupt controller capable of responding quickly and flexibly to complicated interrupt request processing, and the effect is significant.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the stage counter of FIG. 1;

FIG. 3 is a detailed circuit diagram of the interrupt request signal control circuit of FIG. 1;

FIG. 4 is a detailed circuit diagram of the interrupt request signal control circuit during execution of FIG. 1;

FIG. 5 is an operation timing chart of FIG. 1;

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a detailed circuit diagram of the stage counter of FIG. 6;

FIG. 8 is a detailed circuit diagram of the interrupt request signal control circuit of FIG. 6;

FIG. 9 is a detailed circuit diagram of the interrupt request control circuit during execution of FIG. 6;

FIG. 10 is a block diagram showing a general microcomputer.

FIG. 11 is a block diagram showing a conventional example.

FIG. 12 is an operation timing chart of FIG. 11;

[Explanation of symbols]

Reference Signs List 1 microcomputer 2 central processing unit (CPU) 3 memory 4 interrupt controller (INTC) 5 peripheral function block 6 internal bus 7 interrupt request signal (INT (0) to INT (3)) 8 interrupt processing request signal (INTRQ signal) 9 Control signal 11 Interrupt request signal controller (0) (IC (0)) 12 Interrupt request signal controller (1) (IC (1)) 13 Interrupt request signal controller (2) (IC (2)) 14 Interrupt request Signal control device (3) (IC (3)) 15 Scan counter 16 Active priority register (ISPR) 17 Vector address table 18, 118 Comparator 18a Output circuit 19, 155 Output buffer 20 Internal data bus 22, 39, 53 , 113, 124, 140, 161, 163, 166, 16
9, 329, 333, 338, 352, 424, 440, 500, 513
OR circuit 23 Write control circuit 24 to 27 (Write signal control circuit) output 28, 29 Scan signal 30 (ISPR) output 31 (OR circuit 22) output 32 Stage counter 33, 50, 119, 120, 123, 130 , 131, 133, 142,
145, 147, 148, 150, 154, 334, 335, 341, 34
8, 350, 420, 423, 430, 431, 433, 442, 445
, 447, 448, 450, 454, 542, 545, 547, 548
Inverters 34, 35, 47, 49, 51, 110, 114, 115, 121, 125,
128, 132, 135, 136, 141, 143, 149, 151, 15
3, 162, 164, 165, 330, 331, 332, 339, 340
, 342, 343, 344, 347, 349, 351, 353, 421
, 425, 428, 432, 435, 441, 443, 449, 451
, 453, 510, 533, 535, 541, 543, 549 AND circuit 36, 37, 38, 45, 146, 446, 546 p-channel MOS
Transistor 40 Currently executing interrupt controller (ICISPR) 41 ISPR (0) signal 42 ISPR (1) signal 43 ENISPR signal 44 ISPR (2) signal 46 PR (2) signal 48, 127, 160, 167, 168, 321 to 326, 328, 345
, 346, 427 latch 52, 122, 129, 134, 144, 152, 422, 429, 434
, 444, 452, 534, 544 n-channel MOS transistor 111 mask bit latch (mask bit) 112 interrupt request flag latch (interrupt request flag) 115, 116, 117 priority bit latch (priority bit) 126, 327, 426, 512 RS latch 137 NOR circuit 138, 139, 155 Output buffer 160 Macro service interrupt request bit latch (MS
INT bit) CLK clock signal CRIIF Interrupt request flag clear signal CLRIP Highest level clear signal in ISPR CLRMS Macro service interrupt request bit latch clear signal CM (1) to CM (3) Interrupt priority determination signal CMIN, CMOT Default priority Discrimination signal DMS macro service processing designation signal EI Vector interrupt enable / disable designation signal ENISPR ISPR storage presence / absence identification signal ISPR (0) to ISPR (2) ISPR output signal INT, INT (0) to INT (3) Interrupt request signal INTRQ interrupt processing request signal MSINTRQ macro service interrupt processing request signal OEVC vector address ISPR storage signal PR (0) to PR (2) (priority bit)
Latch output signal RA Vector address table creation signal RESET Reset signal SLPRH Vector interrupt request detection signal STG (0) to STG (4) Timing signal

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-47-41541 (JP, A) JP-A-1-276241 (JP, A)

Claims (1)

(57) [Claims] An interrupt request signal for each of a plurality of interrupt request signals
2 ^Plurality setting any priority level out of ⁿ levels
And an n-bit priority register for storing the priority level of the currently executed interrupt processing
Executing priority register of bit and n + 1 timing of scanning priority level of interrupt
A stage counter for sequentially and repeatedly generating signals, and the priority of all generated interrupt request signals
Register contents and the interrupt priority register during execution
N times from the most significant bit to the least significant bit
The highest priority interrupt level by comparing
And there are multiple interrupts with the highest priority interrupt level.
In this case, one timing following the n timings
The highest priority according to the priority determined in advance
Select one interrupt from interrupts with the highest interrupt level.
An interrupt controller and means for-option, further, the macro service processing request the interrupt request signal
Means for performing macro service processing during the n timings.
Request is detected, and if there is a macro service processing request
In this case, the macro server takes precedence over all other interrupts.
A means for outputting a service processing request as an interrupt request signal is provided.
Interrupt controller, characterized in that was example.