JP2567988B2 - Interrupt controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt controller, and more particularly to an interrupt controller capable of specifying a priority level for an interrupt request in a microcomputer.

[Conventional technology]

Generally, a microcomputer has a structure as shown in FIG.

In FIG. 10, this microcomputer is a CPU
(Central processing unit) 100, memory unit 200, interrupt controller
The CPU 100 executes processing based on an instruction read from the program memory in the memory unit 200, which includes the 300 and the peripheral function unit 400. The peripheral function section 400 is controlled by writing or reading data (hereinafter referred to as “access”) via the CPU 100 and the internal data bus 1, but operates independently of the CPU 100.

The peripheral function unit 400 has a timer and a serial interface function, and when the CPU 100 detects a special state such as when the timer reaches a certain value or when serial data reception is completed, An interrupt request signal INT is generated to notify that.

The interrupt request signal TNT is input to the interrupt controller 300. The interrupt controller 300 sends an interrupt request to the CPU100.
State (interrupt enable state), whether there is another interrupt request, the priority order of interrupt requests, etc. are determined.
If the conditions are met, an interrupt request signal INTRQ is sent to CPU 100 as an interrupt request.

When the CPU 100 detects and accepts the interrupt processing request signal INTRQ, it outputs to the interrupt controller 300 various control signals CNT including a signal indicating that the interrupt request has been accepted. Further, the CPU 100 that has received the interrupt request executes the interrupt request signal INT corresponding thereto, that is, the interrupt processing according to the peripheral function, by interrupting the program that has been executed so far.

Here, the priority of the interrupt request signal INT will be described. When there are multiple interrupt request signals INT, depending on the type of the interrupt request signal INT, the interrupt request signal INT (hereinafter referred to as an emergency interrupt request) that should execute interrupt processing urgently and the interrupt request signal INT that may be delayed (hereinafter general (Referred to as an interrupt request). It is necessary to interrupt the emergency interrupt request during the interrupt processing of the general interrupt request and to execute the corresponding emergency interrupt processing during the interrupt processing of the general interrupt request.

Therefore, it is necessary to set a priority for each interrupt request signal INT. Then, it is necessary to control the interrupt processing for the interrupt request signal INT whose priority is set high so that it is interrupted and executed even during the interrupt processing for the interrupt request signal INT whose priority is set low. The above-described priority control is performed by the interrupt controller 300.

Next, the interrupt controller 300 will be described.

FIG. 11 is a block diagram showing an example of a conventional controller, and FIG. 12 is a timing chart of signals of respective parts for explaining the operation of the interrupt controller. 11th
The example in the figure is for the case where the priority designation is 4 levels.

In FIG. 11, INT0 to INT3 are interrupt request signals output from the peripheral function 400, and are input to the corresponding interrupt request signal control units 3 _{I to} 3 _L. Since the interrupt request signal control units 3 _{I to} 3 _L have the same configuration, the interrupt request signal control unit 3 _I will be described here.

When an interrupt request is generated and the interrupt request signal INT0 becomes "1", the interrupt request flag register 31 is set to "1". CPU100 uses internal address AD for interrupt request signal controller 3 _I
When the data is output to the internal data bus 1 and the write signal WE is generated, the write signal control circuit 8
Mask bit register 31 from the output WS1 becomes "1" internal data bus 1 and the priority bit register 33 _A,
33 Output data of the CPU100 is written to _B.

When the content of the mask bit register 31 is "1", the output of the AND circuit AG11 is fixed to "0" by the inverter IV7, but when the content of the mask bit register 31 is "0", the AND circuit is The output of AG11 is determined by the interrupt enable signal EI and the contents of the interrupt request flag register 32. Interrupt processing is enabled when the interrupt enable signal EI is "1".

The priority bit registers 33 _A and 33 _B are bits that specify the priority of the interrupt request signal INT0, and four levels of 0, 1, 2, and 3 (0 is the highest priority level by the priority bit of 2 bits. (3 is the lowest). Further, the priority bit register 33 _A is the upper bit and the 33 _B is the lower bit.

The comparator 36 has made a comparison between the output and the contents of the priority bit register 33 _A, 33 _B of the scan counter 10, and outputs these matches to "1". Therefore, the contents of mask bit register 31 are "0", and interrupt enable signal EI
When is “1”, the interrupt request signal INT0 becomes “1” and the comparator
When the output of 36 becomes "1", the output RA of the AND circuit AG35 becomes "1" and the output of the third circuit OG1 also becomes "1".

CLK is a timing clock, and the latch circuit 9 _A uses the third circuit OG1 at the timing when the timing clock CLK is “0”.
The output of is read and then output when the timing clock becomes "1".

The scan counter 10 is a counter that scans the priority order. Normally, the scan signals SC1 and SC2 are used to scan the priority level such as "0 → 1 → 2 → 3 → 0 ...".
Are repeatedly output in sequence. But the scan counter
When the content of 10 matches the content of the output ISPRO of the running priority register 7 _B , it is cleared and the counting is started from "0" again. If the contents of the running priority register 7 _B is "2" is counted as "0 → 1 → 2 → 0 → ... ". Further, the scan counter 10 suspends the counting operation when the output of the third circuit OG1 is "1" and holds the contents.

The execution priority register 7 _B stores the priority of the interrupt request that the CPU 100 is processing, and the CPU 1
When the OEVC signal, which is one of the 00 control signals CNT, is "1", the outputs SC1 and SC2 of the scan counter 10 are read. However, although the contents previously stored in the running priority register 7 _B are retained, the contents of the running priority register 7 _B are retained.
7 _B output The higher priority level is output to ISPRO. Also, when the OEVC signal is output, interrupt request signal control
Corresponds to the contents when the output of AND circuit AG35 of 3 _{I to} 3 _L becomes "1".

The interrupt vector address is the vector address table 5
To the content data bus 1 via the output buffer 6. The CPU 100 determines the type of interrupt request signal based on this interrupt vector address.

One of the control signals CNT of CPU100 is CLRIF signal is "1"
Then, the output of the AND circuit AG34 becomes "1" and the interrupt request flag register 32 is reset to "0". Note the reset signal RESET is a signal for initializing the interrupt controller, becomes "1", the interrupt request flag register 32 is "0", the mask bit register 31 is "1", the priority bit register 33 _A, 33 _B is "1 , 1 ", executing priority level 7 _B is initialized to a state in which interrupt processing is not executed at all.

For the interrupt request signals INT0, INT1, INT2, INT3, the contents of the mask bit register 31 are 0, 0, 0, 0 respectively, and the contents of the priority bit registers 33 _A , 33 _B are 1, 0 (priority level 2 ), 1,0 (priority level 2), 0,0 (priority level 0), 0,1 (priority level 1) are described with reference to the timing chart of FIG. To do.

In FIG. 12, when the interrupt request signal INT0 is generated at the timing of T2, the scan counter 10 is generated at the timing of T4.
Since the outputs SC1 and SC2 of 2 indicate the priority level 2, the comparator 3
At 6, the coincidence signal EQ is generated and the output RA of the AND circuit AG35 becomes "1". Then, the output of the OR circuit OG1 becomes "1", and the contents of the scan counter 10 stop at level 2. T5
At the timing of, the interrupt processing request signal INTRQ becomes "1", the interrupt request signal INT0 is accepted, and the CPU 100 is requested to perform interrupt processing. In response to the interrupt processing request signal INTRQ, the CPU 100 sets the OEVC signal to "1" at the timing of T6.
Output priority level 7 _B output ISPR at T7 timing
0 indicates priority level 2.

Here, if the CPU 100 sets the CLRIF signal to "1", the content of the interrupt request flag register 32 is cleared to "0". Then, the outputs of the AND circuits AG11 and AG35 become "0", and the output of the OR circuit OG1 also becomes "0". Then, at the timing of T8, the contents of the scan counter 10 are changed to the running priority register.
Since it matches the output ISPRO of 7 _B , the scan counter 10 is cleared and the scan starts from the priority level “0”.

When the interrupt request signal INT2 is generated at the timing of T10, the output SC1, S of the scan counter 10 at the timing of T11.
Since C2 and the contents of the interrupt request signal controller 3 priority bits register 33 in the _{K A,} 33 _B are matched, an interrupt processing request signal INTRQ is "1" INT2 next priority level 0 is accepted. Then, after the timing of T11, the content of the scan counter 10 is fixed to "0".

Next, even if the interrupt request signal INT3 is generated at the timing of T14, since the content of the scan counter 10 is "0",
The comparator 36 of the interrupt request signal controller 3 in _L, the coincidence signal EQ is does not occur, the interrupt request signal INT2 currently accepted (priority level 0) than the priority level is low interrupt request signal INT3 (priority level 1) cannot be accepted.

CPU100 generates CLRIP signal at the end of interrupt processing. When CPU100 at timing T15 is CLRIP signal becomes "1", the running priority level 7 _B resets the priority level 0 of the current output at the timing T16, and outputs a previous priority level 2 . Then, the scan counter 10
Scans again sequentially with the contents of "0 → 1 → 2 ...".

As described above, conventionally, the interrupt priority control is performed by the priority scan of the priority level by the scan counter 10, and the interrupt process with the high priority can be interrupted and executed even during the interrupt process with the low priority level. Also,
During the interrupt processing with the high priority level, the interrupt processing request with the low priority level cannot be executed.

[Problems to be Solved by the Invention]

However, this conventional interrupt controller has a drawback that it takes a long time to complete one round of the scanning operation when the priority level increases as the priority order is searched for. In recent microcomputers, the number of interrupt request signals is increased and fine control is performed, so that the number of priority designation levels is expanded to "8 to 16". If the priority level is 8 levels, 8 timings are required for one scan.
In this case, the time from the generation of the interrupt request signal to the acceptance thereof (hereinafter referred to as "response time") requires a maximum of 16 timings and is delayed. Such a conventional interrupt controller has a drawback that it cannot be applied to a microcomputer corresponding to a real-time control field, which has been widely applied recently because of a problem of response time.

[Means for solving the problem]

The interrupt controller according to the present invention has 2 ⁿ pieces for each of a plurality of interrupt request signals (n is an integer of 2 or more;
, A plurality of n-bit priority bit registers for setting priority levels, a stage counter for sequentially and repeatedly generating (n + 1) timing signals for scanning the priority level for each interrupt request signal, and a current execution A priority register during execution which stores the contents of the priority bit register of the interrupt request signal corresponding to the interrupt processing, and the contents of the priority bit register of all the interrupt request signals generated including the priority bit register and the execution The contents stored in the priority register are sequentially compared from the most significant bit to the least significant bit in synchronization with the n timing signals, and the bit contents of each interrupt request signal have priority over the bit contents of other interrupt request signals. Corresponding to the priority that has the value If only the highest priority level of the requests is detected, and a plurality of interrupt request signals are detected as having the highest priority level, the interrupt request signals are output in accordance with a pre-specified order. Interrupt request signal control means for detecting in synchronization with the next timing signal following, and means for outputting an interrupt processing request signal when this interrupt request signal control means detects an interrupt request signal with the highest priority register. Have

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The description of the same parts as those of the conventional interrupt controller shown in FIGS. 10 to 12 will be omitted, and only different parts will be described.

In FIG. 1, the stage counter 2 has timing signals STG1 and STG for scanning priority levels of interrupt requests.
Generates 2, STG3, STG0 and performs timing control.

Execution priority level 7 is interrupt request signal control unit 3 _A
Read at the timing when OEVC signal priority level output from to 3 _D becomes "1", the next timing clock CLK
Output as output signals ISPR1 and ISPR0 in synchronism with. The priority level during execution 7 sets the ENISPR signal to "0" when no interrupt request signal is accepted. When the priority level is stored in the running priority level 7, the ENISPR signal becomes "1". Running priority level 7
The CLRIP signal clears the current priority level and outputs the previous priority level. Output signal here
ISPR1 has a weight of "2" and ISPR0 signal has a weight of "1".

The latch circuit 9 reads the output of the OR circuit OG1 when the timing clock CKL of the timing STG3 is “1” is “0” and outputs it with the next timing clock CLK, and the timing signal STG0 is the timing of “1”. And circuit AG2
The interrupt processing request signal INTRQ is output via. Also,
It is reset to "0" by the reset signal RESET and the CLRIF signal.

The P-channel MOS transistors Q1 to Q3 are turned on when the output of the inverter IV1 becomes "0" when the timing clock CLK is "1", and the signals SLPRH, CM1, and CM2 are set to the power supply voltage _VDD level, that is, "1". "I will. A capacitor is added to the signal lines of the signals SLPRH, CM1, and CM2 (not shown), and the capacitors are charged to "1", "1", "1" while CLK is "1" (precharged below). That). The output signal CMOT interrupt request signal controller 3 _D becomes the input signal CMIN interrupt request signal 3 _C, hereinafter the same output signal, serves as an input signal the interrupt request signal controller 3 _A output signal CMOT interrupt during reception of It becomes the input signal CMIN of the request signal section 4 and its output CMOT is grounded.

FIG. 2 is a circuit diagram showing a specific example of the stage counter 2.

When the reset signal RESET becomes "1" in the initial state, the latch circuit L1 is "1", the latch circuits L3 and L5 are "0", and the RS type latch circuit L7 is "0" at the timing when the timing clock CLK becomes "0". Initialized to 0 ", the latch circuit L2 is set to" 1 "and the latch circuit L
4, L6 becomes "0".

Next, when the timing clock CLK becomes "0", the AND circuit AG8 outputs the timing signal STG1. When the reset signal RESET becomes "0", the output "1" of the latch circuit L2 is read into the latch circuit L3 via the AND circuit AG3 when the timing clock CLK is "0".

Similarly, when the timing clock CLK is "1", the output of the latch circuit L3 is read by the latch circuit L4 and becomes "1",
Read by the latch circuit L5 via the AND circuit AG4 when the timing clock CLK is "0".

Now, if the CLRIF signal is "0" and the SLPRH signal is "0", the output of the inverter IV5 is "1" and the output of the inverter IV6 is "0", so the output of the AND circuit AG5 is "0" and the latch circuit L7 remains “0”. Since the outputs of the AND circuits AG6 and AG7 are "0" and the output of the OR circuit OG5 is "0", when the timing clock CLK becomes "0", the latch circuit L1 is passed through the OR circuit OG3.
“0” is read in.

Next, when the timing clock CLK becomes "1", the latch circuit L2 becomes "0", the latch circuit L4 becomes "1", and when the timing clock CLK becomes "0", the timing signal STG2 becomes "1".

When the next timing clock CLK is "0", the latch circuit L5 becomes "1", and when it becomes "1", the latch circuit L5 becomes "0" and the latch circuit L6 becomes "1".
When K is "0", the timing signal STG3 becomes "1".

Latch circuit L7 never becomes "1" while SLPRH signal is "0". Latch circuit L1, L2 and latch circuit L3, L4 and latch circuit
Since "1" and "0" are alternately repeated between L5 and L6, timing signals STG1, STG2, STG3 are sequentially output.

When the SLPRH signal becomes "1", the output of the inverter IV6 becomes "1", and when the output of the latch circuit L6 is "1" and the timing clock CLK is "0", the latch circuit L7 is set to "1".

Next, when the timing clock CLK becomes "1", the latch circuit L8 becomes "1" and the timing signal STG0 is output.

When the SLPRH signal becomes "1", the output of AND circuit AG6 becomes "0".
Therefore, the output of the OR circuit OG5 becomes "0", and the timing signal STG1 is not output until the CLRIF signal becomes "1".

Next, when the CLRIF signal becomes "1", the output of the AND circuit AG7 becomes "1", so that when the timing clock CLK becomes "0", the latch circuit L1 becomes "1". Since the OR circuit OG4 becomes "1" by the CLRIF signal, the latch circuit L7 is reset to "0". Therefore, the timing signal STG1 is output after the timing signal STG0. Figure 3 shows the interrupt request signal controller
FIG. 3 is a circuit diagram showing a specific example of 3 _{A to} 3 _D (only 3 _A is shown).

When the interrupt request signal INT0 is input and the content of the mask bit register 31 is "0" and the interrupt enable signal EI is "1", the output of the AND circuit AG11 becomes "1".

The priority bit register 33 _A has a weight of “2”, 3
3 _B is a weight of "1". When the content of the priority bit register 33 _A is “0”, the output of the inverter IV8 becomes “1”.

When the timing signal STG1 becomes "1", the output of the AND circuit AG12 becomes "1" at the timing when the timing clock CLK is "0", and the n-channel type MOS transistor Q4 becomes conductive.
Set the M1 signal to “0”.

The CM1 signal is precharged to "1" when the timing clock CLK is "1", but becomes "0" when the output of the AND circuit AG12 becomes "1". At the same time, the RS latch circuit 34 is set to "1" via the OR circuit OG7 and the AND circuit AG13.

Next, when the timing clock CLK becomes "1", the latch circuit 35 becomes "1", and when the timing signal STG3 becomes "1", the output of the AND circuit AG17 becomes "1". Inverter IV
When the output of 14 becomes "0", the n-channel type MOS transistor Q8 does not become conductive and the input signal CMIN and the acceptance interrupt request precharged by the P-channel type MOS transistor Q7 made conductive by "0" of the previous timing clock CLK. Inverter when output signal CMOT grounded via control unit 4 is "0"
The output of IV15 becomes "1" and the AND circuit AG18 becomes "1" to output the RA signal.

AND circuit A at the timing of the priority bit register 33 _B "0" timing clock CLK when the timing signal STG2 becomes "1" when the latch circuit 35 is "1" is "0"
The output of G14 becomes "1" and n-channel type MOS transistor
Q5 conducts and sets CM2 signal to "0". The CM2 signal is precharged when the timing clock CLK is "1" and is "1".
However, when the AND circuit AG14 becomes "1", it becomes "0".

AND circuit AG15 is a priority bit register 33 _B
Is "1", the CM2 signal is "0" and the timing signal STG2 is "1", the output is "1". The output of the AND circuit AG15 is "1",
Alternatively, when the reset signal RESET is “1” or the CLRIF signal is “1” and the RA signal is “0”, the timing signal STG3 is “1”, the timing clock CLK is “0”, and the AND circuit AG1
When the output of 6 is “1”, the output of the OR circuit OG8 becomes “1”,
When the next timing clock CLK becomes "0", the RS latch circuit 34 is reset to "0".

When the output of the OR circuit OG8 is "0", the output of the inverter IV11 is "1", the output of the latch circuit 35 is "1", and when the timing signal STG3 is "1", the output of the NAND circuit NAG1 is "0". Therefore, the n-channel type MOS transistor Q6 is cut off and the SLPRH signal is set to "1". When the output of the latch circuit 35 is "1" and the timing signals STG1, STG2, STG3 are "0", that is, when the timing signal STG0 is "1", the AND circuit AG19
There "1" output of the next priority bits register 33 _A, 33 _B are read as PR1, PR0 through the output buffer B1, B2.

FIG. 4 is a circuit diagram showing a specific example of the accepting interrupt request control unit 4.

In FIG. 4, a circuit portion similar to that of the circuit in FIG.

The difference between the circuit of FIG. 3 and the circuit of FIG. 4 is that the output of the AND circuit AG11 of FIG. 3 is replaced with the ENISPR signal, and the outputs of the priority bit registers 33 _A and 33 _B become the ISPR1 and ISPR0 signals. Replacement, AND circuits AG20, AG19, AG17, AG18, AG16, NAND circuit NAG1, and n-channel type MOS transistors Q6, Q8
And p-channel type MOS transistor Q7 and inverter IV11,
IV14, IV15, IV16, IV13 and NOR circuit NOG1 are deleted, RA
Other circuits have exactly the same configuration except that there is no signal.

 Next, the operation of this embodiment will be described.

FIG. 5 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

Now, the interrupt request signal INT0, INT1, INT2, the contents of each mask bit register 31 for INT3 are all "0", the priority bit register 33 _A, 33 the contents of _B are "0"
Consider the case where (level 2), "1,0" (level 2), "0,0" (level 0), and "0,1" (level 1) are set (the same as the conventional example). It is also assumed that the EI signal is "1".

When the timing signals STG1, STG2, STG3 output "1" and "0" alternately and repeatedly, and when the interrupt request signal INT1 becomes "1" at the timing of T3, the interrupt request flag register
The contents of 32 become "1". At this time, the interrupt request signal is not accepted at all, and the output signal ENISPR of the execution priority level 7 is "0". Therefore, the output of the AND circuit AG21 of the accepting interrupt request control unit 4 is "0". Similarly, the output of the AND circuit AG12 of the interrupt request signal control units 3 _A , 3 _C , 3 _D is “0”, “0”, “0”, so that the CM signal 1 is “1”. Will remain.

Then, at the timing of T4, the S latch circuit 34 becomes "1" when the timing clock CLK is "0".

At the timing of T6, the output of the AND circuit AG17 becomes "1" at the timing when the output of the latch circuit 35 becomes "1" and the timing signal STG3 becomes "1", and the previous timing clock CL
K is cut off precharge input signal CMIN a MOS transistor Q8 is "1", accepted in the interrupt request control unit 4, the inverter of the interrupt request signal controller 3 _A IV21, the output of IV14 is "1" for grounding The output of the AND circuit AG18, that is, the RA signal becomes "1" by the output "1" of the inverters IV22, IV15 and the CMIN signal which is "1" by the precharge. The output of the AND circuit AG14 is the priority bit register 33 _B.
Since it is "1", it becomes "0", so the CM2 signal becomes "1". The output of the AND circuit AG15 is not reset because the CM2 signal is "1" and the inverter IV12 is "0". Since the RA signal corresponding to the interrupt request signal INT1 is "1", when the timing clock CLK becomes "0" at the timing of T6, the latch circuit 9
Becomes “1”. Also, the output of the NAND circuit NAG1 becomes "0" at the timing when the timing signal STG3 becomes "1", and SLPRH
The signal remains “1”.

Then, the timing signal STG0 is generated at the timing of T7. Since the signal STG0 is "1" and the output of the latch circuit 9 is "1", the interrupt processing request signal INTRQ becomes "1" and the CPU10
Request interrupt processing at 0.

Next, when the OEVC signal is output from the CPU 100 at the timing of T9, the vector address corresponding to the interrupt request signal INT1 is read onto the internal data bus 1 via the output buffer 6, and the priority bit of the interrupt request signal INT1 is read. The contents of registers 33 _A and 33 _B are read into PR1 and PR0 to the priority level 7 during execution.

At the timing of T10, the output of the running priority level 7 becomes the priority level 2 and the output signal ISPR1 becomes "1", the output signal ISPR0 becomes "0", and the new ENISPR becomes "1". Also, CPU100
Outputs the CLRIF signal. When the timing clock CLK becomes "0", the RS latch circuit L7 becomes "0" and the latch circuit L8 becomes "0".

Next, at the timing of T11, the timing signal STG1 is generated.

If the interrupt request signal INT2 is generated at the timing of T13, the interrupt request signal control unit 3 at the timing of T14
The output of the AND circuit AG12 of C becomes "1" and the RS latch circuit 34 becomes "1" when the timing clock CLK is "0".
Becomes Since the output of the AND circuit AG21 is "0" and the output of the AND circuit AG22 is "0", the RS latch circuit 41 is "0".
It remains. Similarly to the case of the interrupt request signal INT1, the timing signals STG2, STG3, STG0 are generated at the timing of T15, T16, T17, and the interrupt processing request signal INTRQ becomes "1" at the timing (T17) next to T16.

Next, when the CPU 100 sets the OEVC signal to "1", the executing priority level 7 reads the priority level 0. Also, CLRIF
According to the signal, the stage counter 2 sequentially outputs the timing signal STG1.

Next, if the interrupt request signal INT3 is generated at the timing of T19, the interrupt request signal INT3 is generated at the timing of 20.
The check of the priority for is started.

At the timing of T20, since the output signals ISPR1 and ISPR0 of the execution priority level 7 are "0" and "0", respectively, the AND circuit AG21 becomes "1" and the CM1 signal becomes "0". Then RS latch circuit 34 for the output of the interrupt request signal controller 3 _D of the AND circuit AG13 remains "0" remains "0", the RA signal even when the timing of T22 is "0" It remains. Further, the interrupt processing request signal INTRQ is not generated at the timing of T23. Therefore priority level 1
Interrupt request signal INT3 cannot be interrupted during interrupt processing of interrupt request signal INT1 of priority level 0.

When the CLRIP signal is output at the timing of T23, the contents of the executing priority level 7 become the priority level 2 immediately before.

Next, when the interrupt request signal INT0 is generated at the timing of T26, the output signals of the execution priority level 27 at the timing of T27 are "1" and "0" for ISPR1 and ISPR0, respectively. The output of the circuit AG21 becomes "0", and CM1
The signal becomes “1”. The output of the AND circuit AG22 becomes "1".
When the RS latch circuit 41 is set and the timing clock CLK becomes “1”, the output of the latch circuit 42 becomes “1”. Since the signal ISPRQ is "0", the output of the AND circuit AG23 becomes "0" and the CM2 signal remains "1".

Therefore, since the output of the AND circuit AG24 remains "0", the output of the OR circuit OG10 becomes "0" and the RS latch circuit 41 is not reset.

Since the priority level (level 2) of the interrupt request signal INT0 is the same as before, the priority bit register 33
_A, 33 content of _B operates similarly interrupt request signal controller 3 _A at the same, the output of the latch circuit 35 becomes "1".

Inverter output is not "1" of the timing signal STG3 the AND circuit AG25 reception during interrupt request control unit 4 at the timing when the "1" and the interrupt request signal controller 3 _A of the AND circuit AG17 IV21, the output of IV14 is " Becomes 0 "and MOS transistor Q12,
Q8 is shut off. Therefore, the input signal CM precharged at the timing when the timing clock CLK becomes "1"
IN, output signal CMOT being grounded, only the output signal CMOT of the accepting interrupt request control unit 4 becomes "0" and its input signal CM
IN and interrupt request signal Control unit 3 _A input signal CMIN, output signal C
MOT remains "1".

The output of the inverter IV22 of the accepting interrupt request control unit 4 becomes "1", the output of the AND circuit AG27 becomes "1", the output of the inverter IV23 becomes "0", and the output of the AND circuit AG26 also becomes "0".
Then, the output of the OR circuit OG10 becomes "0". Further the interrupt request signal controller 3 _A, the output becomes "0" of the inverter IV15, the output of the AND circuit AG18 becomes "0", RA signal remains "0". At the same time, the output of the inverter IV13 becomes "1", the output of the AND circuit AG16 becomes "1", the output of the OR circuit OG8 becomes "1", and the RS latch circuit 34 is reset. That is, the interrupt of the interrupt request signal INT0 is not accepted, and the interrupt processing request signal INTRQ is not output.

Next, although not shown in the timing chart, priority level 0, when no interrupt is currently accepted,
The contents of priority bit registers 33 _A and 33 _B are “0”,
If "0" interrupt request signal INT0, INT1 has occurred, i.e. the same priority when two interrupt signals ranking level occur, similarly interrupt request signal controller 3 at the timing of the timing signal STG3 is "1" _A , 3 _B AND circuit AG17 output is "1" and inverter IV14 output is "0".
The S transistor Q8 is turned off.

Since no interrupt is accepted, the output of the latch circuit 42 of the accepting interrupt request control unit 4 is "0", the output of the AND circuit AG25 is "0", and the output of the inverter IV21 is "1". The adjacent MOS transistor Q12 is conducting. Therefore, the output signal CMOT of the interrupt request signal control unit 3 _A is grounded to "0", and its input signal CMIN and the interrupt request signal control unit
3 _B of the output signal CMOT, the input signal CMIN is "1", an interrupt request signal controller 3 _A only the output of the inverter IV15 becomes "1", the AND circuit output, i.e. the interrupt request signal
RA signal for INT0 becomes "1". However, the output of the interrupt request signal controller 3 _B of the inverter IV15 becomes "0", the output of the AND circuit AG 18, RA signal that is for the interrupt request signal INT1 is "0". Therefore, even if the interrupt request signals INT0 and INT1 having the same priority level are generated at the same time, INT0 has priority.

As described above, the control in which the interrupt request processing with a high priority level can be interrupted while the interrupt request with a low priority level is being processed is performed by scanning the priorities according to the weights from the one with the highest priority bit weight. It can respond faster than the interrupt controller. In addition, if an interrupt with the same priority level as the currently accepted interrupt process occurs, it will not be accepted or two or more interrupts with the same priority level will be accepted. Even if they occur at the same time,
Control is performed such that an interrupt having a higher priority (hereinafter, referred to as a default value) set by the circuit is accepted and an interrupt having a lower default value is not accepted.

Therefore, the present invention can flexibly deal with various interrupt request processes of various interrupt requests at high speed.

 FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

The second embodiment differs from the first embodiment shown in FIGS. 1 to 5 in that the priority level is 8 levels. Along with this, the stage counter 2 _A becomes
The interrupt request signal control units 3 _{E to} 3 _H are changed as shown in FIG. 8 (only 3 _E is shown), and the accepting interrupt request control unit 4 _A is changed as shown in FIG.

Next, this embodiment will be described focusing on the changed portions.

In Figure 6, the difference between FIG. 1 is output timing signal STG4 from the stage counter 2 _A, can be common to CM3 signal to the interrupt request signal controller 3 _E to 3 _H is input. A p-channel type MOS transistor Q13 for precharging is connected to the CM3 signal similarly to the CM1 and CM2 signals. The interrupt request signal controller 3 _E to 3 _H are both PR
2 signals are output and input to the running priority register 7 _A. The signal ISPR2 is output from the executing priority level 7 _A to the accepting interrupt request control unit 4 _A. The PR2 signal is a signal indicating the weight of "4" of the priority bit, and the signal ISPR2 is a signal indicating the weight of "4" at the priority level 7 _A during execution.

In FIG. 7, an AND circuit AG28, latches L9 and L10, and an AND circuit AG29 are added to FIG. 2, and a timing signal STG4 is added as an output. This stage counter 2 _A operates almost in the same way as the circuit of FIG. 2, but since the timing signal STG4 is generated after the timing signal STG3, it is usually "STG1 → STG2 → STG3 → STG4 → STG1 ..." Scan signal is generated.

8, CM3 signal timing signal STG4, inverters IV26, IV27, AND circuits AG30, AG are shown in FIG.
31, n-channel MOS transistor Q14, output buffer B
3, the priority bit register 33 _C is added, the OR circuit OG11 is changed to 5 inputs, and the NOR circuit NOG2 is changed to 4 inputs. Further, the timing signal STG4 is input to the NOR circuit NOG2. The outputs of the priority bit registers 33 _C and 33 _A are input to the inverters IV8 and IV9 instead of the outputs of the priority bit registers 33 _A and 33 _B , respectively. Priority bit register 33 _C represents the weight of "4", representing the eight priority levels of the priority bit register _{33 A ~33 C "0" ~} "7". Therefore, in the scanning of the priority level, the weight of "4" is scanned by the timing signal STG1, the weight of "2" is scanned by the timing signal STG2, and the weight of "1" is scanned by the timing signal STG3.

The operation of the circuit of FIG. 8 is that the SLPRH signal is set to "1" unless the RS latch circuit 34 is reset to "0" when the same timing signal STG4 as that of the circuit of FIG. 3 is generated except that one priority bit is added. ", The next timing signal STG0 is generated, and the interrupt request is accepted.

In FIG. 9, CM3 signal, timing signal STG4, inverters IV28, IV29, IV30, and circuit AG are provided in comparison with FIG.
32, AG33, n-channel MOS transistors Q15, Q16, and a NAND circuit NAG2 are added. The ISPR2 signal is input to the inverter IV17, the ISPR1 signal is input to the inverter IV18, and the ISPRQ signal is input to the inverter IV28. Similar to the circuit of FIG. 8, the circuit of FIG. 9 is configured to scan the priority level from the weight of “4”.

As described above, in the second embodiment, the weight of "4" →
"2" in weight → "1" weights and 3 even when controlling the eight priority levels at the timing, the timing in the same manner as in Example 1 acceptance in the output signal of the interrupt request control 4 _A timing signal STG4 is output CMOT to ground, by connecting the output signal CMOT interrupt request signal controller 3 _E to 3 _H and the input signal CMIN respectively, for two or more interrupt requests of the same priority level, the priority by default values The control of the rank can be scanned at one timing.

From the above description, it is easily understood that scanning can be performed at 5 timings when the priority level becomes 16 levels (2 ⁴ ).

Therefore, it is obvious that the priority level of the 2 ⁿ level can control the priority level determination for the interrupt request at the timing of (n + 1).

〔The invention's effect〕

As described above, according to the present invention, when the number of priority levels is within 2 ⁿ , the priority level scan is performed by 2 ^n.
→ sequentially performed in 2 ^n-1 → ... 2 ⁰ order, the priority by default values only (n + 1) times of the timing by scanning at one time then by be the same priority level default values , Of all the interrupt request signals, the interrupt request signal having the highest priority can be detected.

Therefore, the present invention has an effect that it is possible to quickly and flexibly deal with various interrupt request processes of various interrupt requests that are most suitable for a microcomputer that performs real-time processing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a concrete example of the stage counter of the embodiment shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a circuit diagram showing a concrete example of the interrupt request signal control unit of the embodiment shown in FIG. 4, FIG. 4 is a circuit diagram showing a concrete example of the accepting interrupt request control unit of the embodiment shown in FIG. 1, and FIG. Timing charts for explaining the operation of the embodiment shown in FIGS. 1 to 4, FIG. 6 is a circuit diagram showing a second embodiment of the present invention, and FIG. 7 is shown in FIG. FIG. 8 is a circuit diagram showing a concrete example of the stage counter of the embodiment, FIG. 8 is a circuit diagram showing a concrete example of the interrupt request signal controller of the embodiment shown in FIG. 6, and FIG. 9 is shown in FIG. FIG. 10 is a circuit diagram showing a concrete example of an on-accepting interrupt request control unit of the embodiment, FIG. 10 is a block diagram showing an example of a conventional microcomputer, and FIG. FIG. 12 is a circuit diagram showing an example of a conventional interrupt controller, and FIG. 12 is a timing chart for explaining the operation of the interrupt controller shown in FIG. 1 …… Internal data bus, 2,2 _A …… Stage counter, 3 _A
~ 3 _L ... interrupt request signal control unit, 4, 4 _A ... accepting interrupt request control unit, 5 ... vector address table register,
6 ... Output buffer, 7,7 _A , 7 _B ... Execution priority level, 8 ... Write control circuit, 9,9 _A ... Latch circuit, 10 ...
… Scan counter, 31 …… Mask bit register, 32
...... Interrupt request flag register, 33 _{A to} 33 _C ...... Priority bit register, 34 …… RS latch circuit, 35 …… Latch circuit, 41 …… RS latch circuit, 42 …… Latch circuit, 10
0 …… CPU, 200 …… Memory section, 300 …… Interrupt controller, 400 …… Peripheral function section.

Claims (3)

(57) [Claims] 1. A plurality of n-bit priority bit registers for setting 2 ⁿ (n is an integer of 2 or more, and the same below) priority levels for a plurality of interrupt request signals, and each interrupt request. A stage counter for sequentially and repeatedly generating (n + 1) timing signals for scanning the priority level of the signal, and an executing priority for storing the contents of the priority bit register of the interrupt request signal corresponding to the interrupt process currently being executed. The register, the contents of the priority bit register of all interrupt request signals generated including the priority bit register, and the contents stored in the execution priority register are synchronized with the n timing signals, from the most significant bit to the highest bit. Within the bits of each of the interrupt request signals by sequentially comparing toward the lower bit Detected the interrupt request with the highest priority level corresponding to the priority having a value that has priority over the bit contents of other interrupt request signals, and detected that multiple interrupt request signals had the highest priority level. In this case, an interrupt request signal control means for detecting the interrupt request signal in synchronization with the next timing signal subsequent to the n timing signals in a predetermined order,
An interrupt controller, characterized in that the interrupt request signal control means outputs an interrupt processing request signal when the interrupt request signal of the highest priority register is detected. 2. The interrupt controller according to claim 1, wherein each bit of the priority bit register is set to have a weight of 2 ^(N-1) (N is ^{1 to} n). 3. The contents of the priority bit register are:
3. The interrupt controller according to claim 2, wherein the interrupt controller is configured to sequentially detect and compare the bits having the highest weight.