JP2697099B2 - Speed control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed control device that controls a rotation speed of a rotating body to a desired value.

2. Description of the Related Art Conventionally, as a method of controlling a rotation speed of a rotating body to a desired value, an alternating voltage induced in a stator winding of the rotating body is formed into a rectangular wave without connecting a speed generator to the rotating body. Method using a shaped signal (FG signal) (for example, “Brushless DC motor drive method without position detection element” National Technical Report P614 Vol.33 No.5 OC
T.1987), speed control is performed using only the frequency or repetition period of the FG signal as speed information, and the speed of the rotating body can be controlled relatively stably with a simple configuration. (For example, it is disclosed in Japanese Patent Publication No. 57-18434.) In this frequency or period detection method, the alternating voltage induced in the stator winding is sufficiently amplified until it becomes a rectangular wave signal, and its rectangular shape is obtained. An error output signal is generated assuming that a predetermined edge of the wave signal has velocity information.

For example, in a typical period detection method, a clock pulse is counted in a period from a leading edge (leading edge) of a square wave signal of an alternating voltage after amplification to a next leading edge, so that the rotation speed of the rotating body is reduced. A dependent count value is obtained, and a pulse width modulation signal (used when searching for a chopper type driving method) is generated based on the count value, or the count value is converted into an analog voltage. Error output.

Therefore, in order to realize more accurate control, it is necessary to make the alternating voltage induced in the stator winding the same at a constant rotation speed and make the period of the rectangular wave signal more accurate.

Problems to be Solved by the Invention However, in the above configuration, for example, a rotating body including 12 poles (6 pole pairs) for a rotor and 9 coils for a stator is rotated using a three-phase half-wave driving method. In this case, the period of the rectangular wave signal obtained by amplifying the alternating voltage induced in the stator winding depends on variations in the magnetizing accuracy of the rotor, the mounting accuracy of the rotor and the stator, and the like. Since a cycle longer and shorter than the regular cycle appears alternately, the control system appears as a disturbance having a frequency half the frequency of the rectangular wave signal, and the control characteristics are degraded. In particular, in a control system such as a cylinder motor of a video tape recorder (VTR) that requires high-precision rotation, the frequency of the disturbance has been a problem despite the inertia region of the control system. In addition, since almost no adjustment is performed during mass production, it is difficult to accurately manage the period of the FG signal in all the units.

The present invention has been made in view of the above-described problems, and it is difficult to determine whether the period of the rectangular wave signal is constant even if the period of the rectangular wave signal obtained from the alternating voltage induced in the stator winding is different at the time of constant speed rotation. In this way, it is intended to realize a speed control device that performs high-precision control by correcting the deviation of the period of the rectangular wave signal.

Means for Solving the Problems In order to solve the above problems, the speed control device of the present invention,
Cycle detecting means for detecting a cycle of an AC signal having speed information of a rotating body, memory means for storing a detected value of the cycle detecting means, an arithmetic unit for calculating an error output from the detected value and a reference value, Driving means for supplying driving power to the rotating body based on the error output; and first and second deviations from the continuous first and second cycle detection values stored in the memory means and the reference value. Correction value calculating means for calculating a correction value of the error output from the calculation result when a subtraction value of the first and second deviation amounts is substantially constant; At the time of detection, there is provided an error output correction means for causing the arithmetic unit to correct an error output by period detection, and a monitor means for monitoring that the output of the error output correction means is substantially constant. is there.

The present invention is as if the period of the rectangular wave signal is constant even if the period of the rectangular wave signal obtained from the alternating voltage induced in the stator winding by the above configuration is different at the time of constant speed rotation. The deviation of the period of the square wave signal is corrected by the computing unit, so even if the period of the square wave signal obtained from the induced alternating voltage is shifted, it does not appear as a disturbance in the control system and high accuracy Control can be performed.

Embodiment Hereinafter, a speed control device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, which is realized by using a processor. An alternating voltage signal induced in a stator winding (not shown) of the rotating body 1 is input to the waveform shaper 2. The output signal of the waveform shaper 2 is a channel selector 3a, a calculator 3b, a memory
3c, a cycle detector 3d, and data buses 4, 5, and 6 are supplied to a channel selector 3a of the processor 3. The channel selector 3a generates an address update signal for the memory 3c of the processor 3, and the address update signal is supplied to the memory 3c of the processor 3 via the control bus 4.

The output signal of the waveform shaper 2 is supplied to a period detector 3d. The period detector 3d measures the period of the output signal of the waveform shaper 2 and supplies it to the memory 3c of the processor 3 via the data bus 6. The memory 3c stores the cycle detection value at an address based on the address update signal of the channel selector 3a.

Here, a configuration example of the cycle detector 3d will be described.
The period detector 3d includes a counter for counting a reference clock signal and a latch circuit. When the rising edge of the output signal of the waveform shaper 2 is input to the period detector 3d, the count value of the counter is latched by the latch circuit. The counter is reset immediately thereafter. That is, a count value obtained by counting the period from the rising edge of the waveform shaper 2 to the next rising edge by the reference clock signal is stored in the latch circuit. This is because the period of the output signal of the waveform shaper 2 is calculated using a reference clock signal.
It is a digital measurement.

Next, in the processor 3, the calculator 3 b is operated by the cycle detector 3 d from the cycle detector 3 d via the data bus 6 based on the cycle detection value stored in the memory 3 c of the processor 3 and a preset speed reference value. Calculate the speed error output of
The calculation result is supplied to a digital-analog converter 7 (shown as a DA converter in the figure) via a data bus 5. The output of the digital-analog converter 7 is amplified by a power amplifier (shown as a power amplifier in the figure) 8 and supplied to the rotating body 1 as drive power.

FIG. 2 is a signal waveform diagram for explaining the operation of the period correction, and is a signal waveform diagram when the rotating body 1 is rotating at a constant speed. 2A shows a signal waveform (FG signal) of an alternating voltage induced in the stator winding, FIG. 2B shows an output signal waveform of the waveform shaper 2, and FIG. 2C shows a waveform shaper. 2 is a rising signal waveform created from the output signal of No. 2 and its cycle is measured to be speed information. FIG. 2d is a waveform of the speed error signal calculated by the calculator 3b. The speed error signal is not constant and the FG signal is input every time the FG signal is input, even though the rotation speed of the rotating body 1 is constant. It is larger or smaller than 0 '. This is because the cycle of the FG signal is not always constant, but changes every cycle, and becomes larger or smaller than a normal value. For example, when the rotating body 1 is rotating at a set speed,
The period after waveform shaping of the FG signal is P1, P2, and the ratio of P1: P2 is 9
If it is 8: 102, the detection value of the period P1 of the period detector 3d is a time interval from the time t1 to the time t2 in FIG. 2, and is a value that is 2% shorter than the normal value. Also, period detector
The detection value of the period P2 of 3d is a time interval from the time t2 to the time t3, and the value of the period is 2% longer than the normal value.

The same applies to the next cycle from time t3 to time t5. The time interval from time t3 to time t4 is a value that is 2% shorter than the normal value, and the time interval from time t4 to time t5 is the normal value. The value is 2% longer than that. Therefore, in the cycle of the continuous FG signal, a section shorter and a section longer than the normal cycle value appear alternately.

That is, the arithmetic unit 3b of the processor 3 uses a signal in which an interval in which the period value of the FG signal is shorter and longer than the normal value appears.
Calculates the speed error output. In the section where the time interval from the time t1 to the time t2 is measured, the period is shortened by 2%, so that the speed error output when the speed is increased by 2% is obtained. In the section up to t3, since the period is 2% longer, a speed error output when the speed is 2% slower is obtained. Therefore, the error output increases or decreases even though the rotating body 1 is rotating at the set speed, which is not preferable as a control system.

However, in the embodiment of the present invention shown in FIG. 1, when the rotating body 1 is rotating at a constant speed, even if the period ratio of the FG signal is not exactly 100: 100, the deviation of the period can be reduced. By correcting, a sufficient period ratio can be secured,
The configuration is such that high-precision control can be realized, and such a configuration will be described below.

The section of the first FG signal of the continuous FG signal is section A,
If the section of the FG signal is defined as section B, the rotating body 1 is controlled by one cycle of the FG signal, and the control is performed in a state where the cycle of the FG signal is alternately shifted. At this time, 1 /
The control characteristic of the rotating body 1 at the frequency of 2 is the inertial region, and the control region is about 1/12 of the frequency of the FG signal. It is about 1/6. Nevertheless, F
Due to the shift of the cycle of the G signal, the value of the error signal is larger than the value obtained by the original response of the rotating body 1. Normally, the response of the rotating body 1 at half the frequency of the FG signal is hardly affected by disturbance, and as a result, the value of the error output becomes almost constant.

Using the characteristic that the value of the error output of the rotating body 1 at half the frequency of the FG signal becomes substantially constant, the shift of the period of the FG signal is detected. That is, when the cycle of the continuous FG signal alternately increases or decreases, it is determined that the cause is not the response of the rotating body 1 but the cycle shift due to the FG signal, and the correction is performed.

If the rotation speed of the rotating body 1 is constant and there is no deviation in the ratio of the period of the FG signal, the period value of the A section and the B section will be the same. However, when the FG signal is created, the ratio of the period of the FG signal deviates from 100: 100. Therefore, the period value of the A section and the B section is not the same, but is shifted by a value corresponding to the period deviation. Assuming that the shift amount of the cycle in section A is −ΔA, the shift amount of the cycle in section B is ΔA. That is, the shift amount of the period of the FG signal can be obtained from the difference between the deviation amounts of the A section and the B section, and is expressed by the equation (1).

Here, A and B indicate the values of the periods of the A section and the B section, respectively, and D indicates the speed reference value. At this time, the gain of the control system is set smaller than usual by the gain switching means. The selection of the address of the memory 3c according to the section A and the section B is performed based on the address update signal of the channel selector 3a.

Therefore, the deviation ΔA of the period of the FG signal is expressed by the equation (1).
Calculate + ΔA for the deviation obtained from the value of the measured period in section A, and calculate −ΔA for the deviation obtained from the value of the measured period in section B.
The deviation of the signal cycle can be corrected.

FIG. 2e shows the period correction value obtained by the above method,
It has a negative value in section A and a positive value in section B.

Here, the operation of the channel selector 3a will be described with reference to FIG.

In branch 301 of FIG. 3, it is determined whether or not the FG signal of the rotating body 1 has been input to the processor 3.
If the FG signal has not been input, the branch 301 is executed again, and the arrival of the FG signal is waited. If the FG signal has been input, the process proceeds to a processing block 302, where the channel counter C is incremented. Then, the flow shifts to branch 303 to determine whether the channel counter C is even or odd. If the channel counter C is an even number, the process proceeds to the processing block 304, and the address of the memory 3c is set to the address of the section A. If the channel counter C is an odd number in the branch 303, the processing shifts to the processing block 305 and the address of the memory 3c is set to the address of the section B. As described above, the addresses of the memory 3c corresponding to the sections A and B are determined by the channel selector 3a.

Next, the processor 3 based on the equation (1) calculates
FIG. 4 shows a flowchart of the FG signal cycle deviation correction.

Here, in order to increase the detection accuracy of the period detection of the section A and the section B (because one measurement is weak against noise or the like), it is assumed that the values measured several times are averaged. Exclude from average data. Assuming that the number of times of averaging is n, the average values of the deviation amounts in section A and section B are respectively It is represented by Here, Ai is the detection period of section A, and Bi is B
This represents the detection cycle of the section. Therefore, equation (1) becomes equation (2).

First, the processing block 401 calculates the period of the continuous FG signal, the branch 402 obtains the deviation amount from the period of the FG signal, and determines whether the difference between the deviation amounts of the continuous FG signals is substantially constant. . If the difference between the deviation amounts is not substantially constant, the rotation speed of the rotating body 1 has changed, and the rotation speed of the rotating body 1 is determined based on the value of one cycle without correcting the FC signal cycle until the speed becomes constant.
Control.

Next, in a processing block 403, the deviation amount of each of the A section and the B section specified by the channel selector 3a is calculated, and it is determined whether or not the branch 404 has been completed n times.
If not, the process returns to the processing block 403. If the processing is completed n times, the average of the deviation amounts of the A section and the B section is obtained in the processing block 405, and the average value of the B section is calculated from the average value of the B section.
The average value of the section is subtracted, and the subtraction result is halved to obtain a correction value ΔA
Is calculated. The correction value ΔA is stored in the memory 3c,
It is used when calculating the error output thereafter.

After the correction value ΔA is obtained, the FG
Shift to control of period correction.

The arithmetic expression of the speed error output of the arithmetic unit 3b after shifting to the control of the FG cycle correction is as shown in Expressions (3) and (4).

_{O A = A-D + ΔA} ...... (3) O B = B-D-ΔA ...... (4) where, O _A speed error output of the A interval, O _B is the speed error output of the B segment.

In the flowchart of FIG. 4, the correction value ΔA is obtained from the deviation amounts of the sections A and B, but it is also possible to obtain the correction value from each cycle. That is, if the speed reference value D is not taken into account in the equations (1) and (2), the correction value is obtained only from the detected values in the periods of the periods A and B.

As described above, the deviation of the period of the FG signal is corrected using the correction value ΔA obtained from the equation (2) as shown in the equations (3) and (4). It becomes possible. Further, after the shift to the control of the FG cycle correction, since the correction operation is performed using a fixed value, there is no adverse effect on the control system unlike a compensation filter (for example, a trap filter).

Next, since the calculation of the correction value is not performed after shifting to the control of the FG cycle correction, an operation when the correction value is shifted for some reason will be described.

FIG. 5 shows a flowchart for explaining the operation of the monitor means.

In a processing block 501, error outputs O _A and O _B in the A section and the B section are calculated. (This processing block is carried out at a rate control process may be used and the results.) Then, determined in process block 502, A section, B section of each error output O _A, the absolute value of the difference between O _B, It is determined whether the value is equal to or smaller than a threshold value S. Error output O _A, the absolute value of the difference between O _B is transitions to processing block 503 if more than the threshold value S, and ends by substituting "0" into the counter R. In branch 502, the error output O _A, the absolute value of the difference between O _B is transitions to processing block 504 if more than the threshold value S, and increments the monitor counter R. branch
In 505, ends when the value of the monitor counter R is Re smaller than N _R (threshold monitor counter R), and proceeds to processing block 506 is greater than N _R, performs a process of recalculating the correction value .DELTA.A.

As described above, even if the correction value ΔA is shifted, the provision of the monitor means allows the correction value to be calculated again, so that it is possible to deal with the problem without any problem.

As described above, according to this embodiment, the deviation of the period of the FG signal is detected from the fact that the deviation of the value of the period of the continuous FG signal becomes substantially constant, and the memory 3c of the processor 3 is used as an error output correction value. Since the speed error is calculated using the error output correction value during constant speed rotation, an error output that is not affected by the deviation of the FG signal cycle can be output, and high-precision control can be performed. realizable. Also, even when the cycle of the FG signal is shifted due to a temperature change, that is, when the correction value ΔA is shifted, the monitor means detects the shift and calculates the correction value again at that time, so that there is no problem. Can be.

In this embodiment, the alternating voltage induced in the stator winding of the rotating body is used to generate the FG signal. However, the period of the FG signal generated by another method is reduced at half the frequency of the FG signal. If there is a deviation, the present invention exerts a sufficient effect.

Further, although the channel selector, the arithmetic unit, the memory, the cycle detector, the error output correcting means, and the gain switching means are constituted by using the processor, there is no problem even if each is constituted by individual hardware.

Effect of the Invention As described above, the present invention provides a cycle detecting means for detecting a cycle of an AC signal having speed information of a rotating body, a memory means for storing a detected value of the cycle detecting means, the detected value and a reference value. A computing unit that calculates an error output from, and a driving unit that supplies driving power to the rotating body based on the error output,
Calculating first and second deviation amounts from the continuous first and second cycle detection values stored in the memory means and the reference value;
Correction value calculating means for calculating a correction value of the error output from the calculation result when the subtraction value of the first and second deviation amounts is substantially constant; and Output correction means for causing the detector to correct the error output by detecting the period, and monitor means for monitoring that the output of the error output correction means is substantially constant. The deviation of the period caused by the frequency of / 2 is detected from the fact that the deviation amount of the period value of the continuous FG signal becomes substantially constant, and is stored in the memory 3c of the processor 3 as the error output correction value. During high-speed rotation, the speed error is calculated using the error output correction value, so it is possible to output an error output that is not affected by the shift of the FG signal cycle.This has the enormous effect of achieving high-precision control. Play. In addition, even if the correction value ΔA shifts, the provision of the monitor means allows the correction value to be calculated again, so that it is possible to deal with the problem without any problem.

[Brief description of the drawings]

FIG. 1 is a block diagram of a speed control device according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining a circuit operation, FIG. 3 is a flowchart for explaining an operation of a channel selector, and FIG. FIG. 5 is a flowchart for explaining the operation of the error output correction means, and FIG. 5 is a flowchart for explaining the operation of the monitor means. 1 ... motor, 2 ... waveform shaper, 3 ... processor,
3a Channel selector, 3b Arithmetic unit, 3c Memory, 3d Period detector, 4, 5, 6 Data bus, 7
Digital-analog converter, 8 power amplifier.

Claims (3)

(57) [Claims] 1. A cycle detecting means for detecting a cycle of an AC signal having speed information of a rotating body, a memory means for storing a detected value of the cycle detecting means, and an error output calculated from the detected value and a reference value. An arithmetic unit, a driving unit that supplies driving power to the rotating body based on the error output, and a first, second, and third cycle detection values stored in the memory unit. Calculate the second deviation amount, and calculate the first and second deviation amounts.
Correction value calculation means for calculating a correction value of the error output from the calculation result when the subtraction value of the deviation amount is substantially constant,
Error output correction means for causing the arithmetic unit to correct an error output by the cycle detection at each cycle detection time by the correction value; and monitor means for monitoring that the output of the error output correction means is substantially constant. Become a speed control device. 2. An address of memory means for storing a detected value of the cycle detecting means is updated every time the cycle detecting means detects a cycle over at least two cycles of an AC signal having speed information of the rotating body. 2. The speed control device according to claim 1, further comprising a channel selector for comparing the cycle data stored at the corresponding address of the memory means with the reference value and transmitting an error output according to the magnitude to the drive means. 3. The speed control device according to claim 1, wherein when the monitor means determines that the output of the error output correction means is not substantially constant, the correction value is calculated again.