JPH0833773B2 - Servo device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a servo device that controls a rotation speed of a rotating body to a desired value.

2. Description of the Related Art Conventionally, as a method of controlling the rotation speed of a rotating body to a desired value, there is a method of using a speed generator that is connected to the rotating body and generates an output signal having a frequency or voltage according to the rotation speed. Since it occupies the mainstream and uses only the frequency of the output signal (FG signal) of the speed generator or the repetition period as speed information, a servo device in which a series of processing is digitized (for example, Japanese Patent Publication No. Sho 53-19745). , Or U.S. Pat. No. 3,836,756) has the advantage that extremely high stability is obtained.

By the way, according to this frequency or period detection method, an error output signal is generated assuming that a predetermined edge of the output signal of the speed generator sufficiently amplified to become a rectangular wave signal has speed information.

For example, in a typical cycle detection method, depending on the rotation speed of the rotating body, clock pulses are counted in the period from the leading edge (leading edge) of the output signal of the speed generator after amplification to the next leading edge. By obtaining the counted value and producing a pulse width modulation signal (used when the chopper type driving method is adopted) based on this counted value, or by converting the counted value into an analog voltage. You are getting the error output.

Therefore, in order to realize control with higher resolution, it is necessary to increase the number of edges.

An easy way to increase the number of edges is to use both the leading and trailing edges of the square wave signal obtained by amplifying the output signal of the speed generator to obtain the output of the speed generator. There is a method of measuring the cycle twice every half cycle during one cycle of the signal, that is, doubling the output signal of the speed generator to obtain speed information having a frequency twice that of the original output signal.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-described configuration, the output signal of the speed generator is output by using both the leading edge and the trailing edge of the rectangular wave obtained by amplifying the output signal of the speed generator. When multiplying, the duty ratio of the output signal of the speed generator after amplification does not become 50:50 due to the offset of the amplifier and the waveform distortion of the output signal of the speed generator. There was a problem that it appeared as a disturbance and controllability deteriorated.
In particular, if the amplifier is configured by a CMOS (complementary metal oxide semiconductor) process for power saving, it is difficult to double the output signal of the speed generator because the offset is large.

In view of the above problem, the present invention has a duty ratio of 50:50 even if the output signal of the speed generator is not exactly 50:50 due to the offset of the amplifier or the like.
Correct the duty deviation as if it were 50, and 2
The objective is to realize a servo device that performs highly accurate control during multiplication.

Means for Solving the Problems In order to solve the above problems, the servo device of the present invention is
An AC signal having speed information of the rotating body is doubled to generate first and second output signals during one cycle of the AC signal. 2
Multiplication means, cycle detection means for detecting the cycle of the output signal of the multiplication means, memory means for storing the detection value of the cycle detection means, and an arithmetic unit for calculating an error output from the detection value and the reference value. A drive means for supplying drive power to the rotating body based on the error output, and a first of the doubling means.
The deviation from the normal value is calculated from the cycle from the output signal to the second output signal and the cycle from the second output signal to the first output signal, and from the calculation result, the arithmetic unit at each cycle detection time point is calculated. Is provided with an error output correction means for correcting the error output by doubling.

Effect According to the present invention, the deviation of the duty ratio that occurs when the output signal of the speed generator is multiplied by the above configuration is corrected by the arithmetic unit. Even if there is a deviation, a disturbance of the frequency of the output signal of the speed generator hardly appears in the control system, and highly accurate control can be performed.

Embodiment Hereinafter, a servo apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The output of a speed generator (generally called a frequency generator or simply FG) 2 connected to a motor 1 is doubled by a doubler circuit 3. To be done. The output of the doubler circuit 3 is supplied to the channel selector 4. The channel selector 4 generates an address update signal for the memory 5b of the processor 5, and the address update signal is supplied to the processor 5 via the control bus 6.

When the frequency doubler circuit 3 outputs an output signal, a timing signal is output from the timing signal output terminal 4a of the channel selector 4 and supplied to the cycle detector 7. The cycle detector 7 has the timing signal output terminal 4a.
The cycle of the timing signal output from the above, that is, the cycle of the output signal of the frequency doubler circuit 3 is measured and supplied to the memory 5b of the processor 5 via the data bus 8. The memory 5b stores the cycle data at an address based on the address update signal of the channel selector 4.

Next, in the processor 5, the calculator 5a controls the speed of the motor 1 based on the cycle data stored in the memory 5b of the processor 5 from the cycle detector 7 via the data bus 8 and the preset reference speed data. The error output is calculated, and the calculation result is supplied to the digital-analog converter 10 via the data bus 9. The digital-
The output of the analog converter 10 is amplified by a power amplifier (denoted as a power amplifier in the figure) 11 and supplied to the motor 1 as driving power.

FIG. 2 is a circuit connection diagram showing a specific configuration of the doubler circuit 3, and 2a and 2b are input terminals to which an output signal of the speed generator 2 and a reference clock signal are input, respectively. The output signal of the speed generator 2 is amplified by the amplifier 21 to a constant voltage level, then shaped into a rectangular wave by the waveform shaper 22, and input to the D input terminal of the D flip-flop 23.
The Q output terminal of the D flip-flop 24 is connected to the D input terminal of the D flip-flop 24 and one input terminal of the EX-OR (exclusive OR) gate 25.
The output terminal is connected to the other input terminal of the EX-OR gate 25. Clock terminals 23a, 24a of the D flip-flops 23, 24
Is connected to the clock terminal 2b. The output terminal of the EX-OR gate 25 is connected to the output terminal 2c of the doubler circuit.

FIG. 3 is a signal waveform diagram for explaining the operation of the frequency doubler circuit 3, FIG. 3 (a) shows the output signal waveform of the speed generator 2, and FIG. 3 (b) is an amplifier. 21 shows the output signal waveform, FIG. 3 (c) shows the output signal waveform of the waveform shaper 22, which is the signal waveform input to the D flip-flop 23, and FIG. 3 (d) shows the EX-OR gate 25. Output signal waveform, clock 2b at both edges of the signal in FIG. 3 (c)
It is a signal having a pulse width corresponding to one clock of the reference clock signal input to, and is a signal obtained by doubling the output signal of the speed generator 2. That is, FIG. 3D shows the output signal of the doubler circuit 3.

Here, since there is an offset in the amplifier 21, the signal waveform after amplification of the output signal of the speed generator 2 becomes a waveform deviated from the center as shown in FIG. 3 (b). Therefore, the duty ratio of the output signal of the waveform shaper 22 does not become 50:50 as shown in FIG.
The waveform deviates from 50. Therefore, the EX in Fig. 3 (d)
-The output of the OR gate 25 does not have a constant cycle due to the deviation of the duty ratio, and becomes larger or smaller than the normal value. For example, if the motor 1 is rotating at the set speed and the duty ratio after doubling is 48:52, the detected value of the period detector 7 is the time interval from time t1 to time t2 in FIG. And is 4% shorter than the regular value. When the time interval from time t2 to time t3 is detected by the cycle detector 7, the cycle value is 4% of the normal value.
It will be a long value.

Furthermore, the same applies to the next cycle from time t3 to time t5, the time interval from time t3 to time t4 is 4% shorter than the normal value, and the time interval from time t4 to time t5 is the normal value. It is 4% longer. Therefore, by multiplying the output signal of the speed generator 2 by 2, a section shorter and a section longer than the value of the regular cycle appear in one cycle of the output signal of the speed generator 2.

Using a signal obtained by doubling the output signal of the speed generator 2,
That is, when the arithmetic unit 5a of the processor 5 calculates the speed error output using a signal in which a section in which the cycle value is shorter than the normal value and a section in which the cycle value is longer than the normal value are obtained by multiplication, the time interval from time t1 to time t2 is measured. Since the cycle is shortened by 4% in the section where the speed is increased, the speed error is output when the speed is increased by 4%. In the section from time t2 to time t3, the cycle is increased by 4%, so the speed is 4%. It becomes the speed error output when it becomes late. Therefore, the error output increases or decreases even though the motor 1 rotates at the set speed, which is not preferable for the control system. In particular, at the time of start-up, the speed error output does not become a normal value due to the deviation of the duty ratio, so that the motor 1 may hunt or may not start properly.

However, in the embodiment of the present invention shown in FIG.
The duty ratio after doubled by the multiplier circuit 3 is exactly 50: 5.
Even if it is not 0, a sufficient duty ratio can be secured,
It is configured so that highly accurate control can be realized, which will be described below.

High-level section of the output signal of the waveform shaper 22 in the first cycle (Fig. 3c) after doubling the output signal of the speed generator 2)
Is the A section and the second cycle (the low level section of the waveform shaper 22 in the FIG. 3c) is the B section, the motor 1 is controlled by one cycle of the output signal of the speed generator 2, and the doubler circuit It is assumed that the motor is rotating at the set speed without being affected by the duty deviation of. Therefore, the value of one cycle of the output signal of the speed generator 2 becomes a constant value. That is, the sum of the periods of the A section and the B section is also a constant value.

Here, if there is no deviation in the duty ratio due to the frequency doubler circuit 3, the period values of the A section and the B section are the same. However, the duty ratio is 50: 5 due to the offset of the amplifier 21.
Since it deviates from 0, the period values of the A section and the B section do not become the same, but deviate by a value corresponding to the offset. A
Assuming that the period deviation value of the section is ΔA, the period deviation value of the section B is −ΔA. That is, the shift of the cycle at the time of doubling the output signal of the speed generator due to the offset of the amplifier 21 can be obtained from the difference between the A section and the B section and is expressed by the equation (1).

Here, A and B indicate the values of the periods of the A section and the B section, respectively. Further, the selection of the address of the memory 5b according to the A section and the B section is performed based on the address update signal of the channel selector 4.

Therefore, if the deviation ΔA of the duty ratio due to the offset of the amplifier 21 is calculated, the measured cycle value is calculated by + ΔA in the section A, and the measured cycle value is calculated by −ΔA in the section B, the amplifier 21 is calculated. It is possible to correct the deviation of the period due to the offset. Since the calculator 5a calculates the speed error output on the basis of the corrected cycle data at the time of doubling, the influence of the offset of the amplifier 21 does not appear on the speed error output.

FIG. 4 shows a flowchart of the duty ratio correction by the processor 5 based on the above calculation formula.

Here, in order to improve the detection accuracy of the period detection of the A section and the B section (because one measurement is weak against noise etc.), it is assumed that several measurements are averaged, and if the cycles are significantly different, Exclude from average data. If the number of times of averaging is n, the average values of section A and section B are It is represented by. Therefore, the equation (1) becomes the equation (2).

First, in block 401, the duty ratio of the output signal of the speed generator 2 after doubling is 5 due to the offset of the amplifier 21.
Since it is not 0:50, it is 1 of the output signal of the speed generator 2.
Start motor 1 according to the cycle
To determine if the speed has become constant. If the speed is not constant, control is performed based on the value of one cycle of the output signal of the speed generator 2 until the speed becomes constant. If the motor 1 starts to rotate at a constant speed, block 403 measures the period of each of section A and section B, and block 404 determines whether or not the cycle has ended n times. If it has not ended n times, block 403 Return to. When the processing is completed n times, in block 405, the averages of the A section and the B section are obtained, and then the average value of the A section is subtracted from the average value of the B section. Looking for. After the correction value ΔA is obtained, the control shifts to the control of the block 406 which is doubled.

The arithmetic expressions of the speed error output of the arithmetic unit 5a after shifting to the control of double multiplication are as shown in the equations (3) and (4).

O _A = A−D + ΔA (3) O _B = B−D−ΔA (4) where D is the predetermined reference speed data, O _A is the speed error output of section A, and O _B is the section B. Is the speed error output of.

In this way, the deviation of the duty ratio generated when the output signal of the speed generator 2 is multiplied by 2 is calculated by using the correction value ΔA obtained from the expression (2), and the speed error output is obtained as shown in the expressions (3) and (4). Since it corrects, high-precision control becomes possible.

As described above, according to the present embodiment, when the output signal of the speed generator is used by being doubled, the deviation of the duty ratio caused by the offset of the amplifier is calculated based on the value of one cycle of the output signal of the speed generator. Since it is detected during the control and is stored in the memory of the processor as the output correction data, the speed error is calculated using the output correction data when the control shifts to the multiplication by 2 so that the duty ratio deviation An error output that is not affected can be output, and highly accurate control can be realized.

EFFECTS OF THE INVENTION As described above, according to the present invention, the AC signal having the speed information of the rotating body is doubled, and the first and second output signals are generated during one cycle of the AC signal. Cycle detecting means for detecting the cycle of the output signal of the doubling means, memory means for storing the detected value of the cycle detecting means, a calculator for calculating an error output from the detected value and a reference value, and the error output Drive means for supplying drive power to the rotating body based on the above, a cycle from the first output signal to the second output signal of the frequency doubler, and a cycle from the second output signal to the first output signal According to the third aspect, the deviation from the normal value is calculated, and an error output correction unit for causing the arithmetic unit to correct the error output by doubling at each cycle detection time based on the calculated result is provided. Double the output signal of the speed generator The deviation of the duty ratio caused by the offset of the amplifier is detected during the control based on the value of one cycle of the output signal of the speed generator and is stored in the memory of the processor as the output correction data. When the control shifts to the control by multiplying by 2, the speed error output is calculated using the output correction data, so that the error output that is not affected by the deviation of the duty ratio can be output, and the highly accurate control can be realized. Play.

[Brief description of drawings]

FIG. 1 is a block diagram of a servo device according to an embodiment of the present invention, FIG. 2 is a circuit connection diagram showing a concrete example of a frequency doubler circuit, and FIG. 3 is a signal waveform diagram for explaining the circuit operation of FIG. FIG. 4 is a flow chart for explaining the error correction operation. 1 ... Motor, 2 ... Speed generator, 4 ... Channel selector, 5 ... Processor, 7 ... Period detector, 10 ...
Digital-analog converter, 11 ... Power amplifier.

Claims (3)

[Claims] 1. An doubling means for doubling an AC signal having speed information of a rotating body to generate first and second output signals during one cycle of the AC signal, and an output signal of the doubling means. Cycle detecting means for detecting the cycle, a memory means for storing the detection value of the cycle detecting means, an arithmetic unit for calculating an error output from the detection value and a reference value, and the rotating body based on the error output. Deviation from a normal value based on a driving means for supplying driving power and a cycle from the first output signal to the second output signal of the doubler means and a cycle from the second output signal to the first output signal And a servo device including an error output correction unit that causes the arithmetic unit to correct the error output by doubling at each cycle detection time from the calculation result. 2. An amplifier for amplifying an AC signal having speed information of a rotating body, a waveform shaper for shaping the output signal of the amplifier, and signals at both edges of the output signal of the waveform shaper for the AC signal. The servo device according to claim (1), further comprising a doubling means for producing a doubling output of the above. 3. The address of the memory means for storing the detection value of the cycle detecting means is updated every time the doubling means generates an output signal over at least one cycle of the AC signal having the speed information of the rotating body, and the arithmetic unit is also provided with the address. The channel selector according to claim (1), further comprising a channel selector for comparing the cycle data stored in the corresponding address of the memory means with a reference value and sending an error output corresponding to the magnitude of the cycle data to the drive means. Servo device.