JP2692692B2 - Display panel driving method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for driving a display panel composed of a set of cells which are display elements having a memory function, and more particularly to an AC (alternating current) type plasma display panel (Plasma). Display Pane
l: PDP) relates to a driving method and apparatus for performing multi-gradation display (so-called full-color display).

The above AC type PDP sustains discharge by alternately applying voltage waveforms to two sustain discharge electrodes,
A light emitting display is performed. One-time discharge ends within several μs after the pulse application. Ions, which are positive charges generated by the discharge, are accumulated in the insulating layer on the electrode to which a negative voltage is applied, and electrons, which are also negative charges, are insulating layers on the electrode to which a positive voltage is applied. Accumulated in.

Therefore, a high voltage (write voltage) is initially required.
When a pulse (sustain discharge pulse) with a lower voltage (sustain discharge voltage) than the previous one with different polarity is applied after generating the wall charge by discharging with the pulse (write pulse) of, the wall charge accumulated previously overlaps. As a result, the voltage with respect to the discharge space becomes large, and the discharge is started beyond the threshold value of the discharge voltage. That is, the cell that has been subjected to the write discharge once to generate the wall charges is characterized by sustaining the discharge by subsequently applying the sustain discharge pulse with the opposite polarity. This is called memory effect or memory drive. AC
The type PDP realizes display by utilizing this memory effect.

[0004]

2. Description of the Related Art AC type PDPs include a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes.
There is a three-electrode type that uses the third electrode to perform address discharge. In a color PDP that performs multi-gradation display, the fluorescent substance in the cell is excited by the ultraviolet rays generated by the discharge, but this fluorescent substance is extremely weak against the impact of ions, which are positive charges simultaneously generated by the discharge. There are drawbacks. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened. In order to avoid this, a three-electrode type utilizing surface discharge is generally used in the color PDP.

As the above-mentioned three-electrode / surface-discharge type PDP,
Conventionally, one having a schematic plan view thereof shown in FIG. 39 is known. In FIG. 39, 1 is a panel body, 2 is an X electrode, 3 ₁ , 3 ₂ , ..., 3 _K , ..., 3 ₁₀₀₀ is a Y electrode,
4 ₁ , 4 ₂ , ..., 4 _K , ..., 4 _M are address electrodes, and M × 1000 cells 5 are formed at intersections of a pair of X electrodes, Y electrodes and one address electrode. There is. In addition, 6 is a wall that partitions the cell 5, 7 ₁ , 7 ₂ , ..., 7 _K ,
…, 7 ₁₀₀₀ is a display line.

FIG. 40 shows the basic structure of the cell 5 shown in FIG.
8 is a schematic sectional view showing a structure, in which 8 is a front glass
Substrate, 9 is a rear glass substrate, 10 is an X electrode 2 and a Y electrode.
Pole 3 _K(K is an arbitrary number in 1 ... 1000)
Dielectric layer, 11 is a protective film made of a MgO film or the like, 12
Is a phosphor and 13 is a discharge space. 41 is a diagram
39 is a diagram showing a conventional PDP shown in FIG. 39 and its peripheral circuits.
Yes, in the figure, 14 is a write pulse to X electrode 2 and sustain
X-side driver circuit for supplying discharge pulse, 15₁~ 15
_FourIs Y electrode 3₁~ 3₁₀₀₀Address pulse to Y
Side driver IC, 16 is Y electrode 3₁~ 3₁₀₀₀Address to
Y-side driver circuit for supplying pulses other than pulses, 17
₁~ 17_FiveIs the address electrode 4₁~ 4_M(4 in FIG. 40)_KAlso
Address driver I for supplying address pulses to
C and 18 are X-side driver circuit 14 and Y-side driver IC1
5₁~ 15_Four, Y-side driver circuit 16 and address
Driver IC17₁~ 17_FiveIs a control circuit for controlling.

FIG. 42 is a conventional PD shown in FIG.
FIG. 9 is a waveform diagram showing a first example of a conventional method of driving P, showing one driving cycle in a so-called conventional “line sequential driving / self-erasing address system”. In this example, first, the Y electrode of the display line (hereinafter, referred to as a selected line) selected as a display line to which the display data is to be written in this one drive cycle is set to the GND level, and the display lines other than the selected line (hereinafter, referred to as a non-selected line) are set. The potential of the Y electrode (referred to as a selection line) is held at the Vs level, and the write pulse 19 having the voltage Vw is applied to the X electrode 2.
Discharge is performed in all cells on the selected line. In this case, the voltage difference between the X electrode and the Y electrode of the selected line is Vw, and the voltage difference between the X electrode and the Y electrode of the non-selected line is Vw-Vs. Therefore, Vw> Vf (discharge start voltage)> Vw−
By setting Vs, discharge can be caused in all cells on the selected line.

Here, as the discharge progresses, negative wall charges are accumulated in the protective film 11 on the X electrode 2 of the selection line, for example, the MgO film, and the positive wall is accumulated in the MgO film on the Y electrode of the selection line. Electric charges are accumulated, but since the wall charges have a polarity that reduces the electric field in the discharge space, the discharge immediately converges and is terminated in about 1 μS. Next, the sustain discharge pulses 20 and 21 are alternately applied to the X electrode 2 and the Y electrode of the selected line, the accumulated wall charges are added to the voltage applied to the electrode, and the lighting ( Sustaining discharge is repeated except for the cells that do not emit light.

For cells that are not to be lit, the sustain discharge pulse 20a is first applied to the X electrode 2, and positive wall charges are accumulated in the MgO film on the X electrode 2 of the selected line, so that the selected line is charged. After the negative wall charges are accumulated in the MgO film on the Y electrode, the positive voltage Va is applied to the address electrode corresponding to the cell not to be lit in synchronization with the sustain discharge pulse 21a first applied to the Y electrode of the selected line. The address pulse (erase pulse) 22 is selectively applied.

In this case, a sustain discharge is generated in all cells on the selected line. Particularly, in a cell in which the positive address pulse 22 is applied to the address electrode, discharge between the address electrode and the Y electrode is generated at the same time. Excessive positive wall charges are accumulated in the MgO film on the Y electrode. If the voltage Va is set to a value such that the generated wall charges themselves exceed the discharge start voltage, when the external voltage is removed, that is, the X electrodes and the Y electrodes are at the Vs level, and the address electrodes are at the GND level. When the level is set, discharge occurs due to the voltage of the wall charges themselves, which becomes self-erasing discharge and extinguishes the wall charges. Therefore, after that, the sustain discharge does not occur with the sustain discharge pulses 20 and 21.

Since the erase pulse (address pulse) 22 is not applied to the corresponding address electrode for the cell to be turned on, self-erase discharge does not occur. Therefore, the sustain discharge is repeated by the sustain discharge pulses 20 and 21 applied thereafter. In addition, 23 is Y of the non-selected line
This is a sustain discharge pulse applied to the electrodes. In this way, the display data is written in the selected line in one driving cycle, but in this example, the writing is performed for each display line. FIG. 43 is a time chart showing this state. In the figure, “W” is a drive cycle for writing, “S” is a drive cycle for only sustain discharge,
“S” is a drive cycle of only the sustain discharge of the previous frame (field).

[0012] Figure 44 is a conventional PD shown in FIG. 39
FIG. 9 is a waveform diagram showing a second example of a conventional method of driving P, showing one frame period in a so-called conventional “address / sustain discharge separated type / self-erasing address method”. In this example, one frame is divided into a full address period, an address period and a sustain discharge period. In the full address period, first, the Y electrodes 3 _{1 to} 3 ₁₀₀₀ are G
The write pulse 24 having the voltage Vw is applied to the X electrode 2 at the ND level, and discharge is performed in all cells on all display lines. Then, the potential of the Y electrodes 3 _{1 to} 3 ₁₀₀₀ is the voltage V.
While being returned to s, the sustain discharge pulse 25 is applied to the X electrode 2, and the sustain discharge is performed in all the cells.

Next, in the address period, writing is sequentially performed from the display line 7 _1. This is performed as follows. First, while the GND level address pulse 26 ₁ is applied to the Y electrode 3 ₁ , the address electrode 4 ₁
During 4 _M , the address pulse 27 of the voltage Va is selectively applied to the address electrodes corresponding to the cells that are not to be sustain-discharged, that is, the cells that are not to be lit, and the self-erase discharge of the cells that are not to be lit is performed. This allows the display line 7
Writing ₁ ends.

Hereinafter, the display line 7_Two~ 7₁₀₀₀about
, The same operation is performed in order, and all display lines 7₁~ 7
₁₀₀₀In, new data is written. 26
_Two, 26 _Three, ……, 26₁₀₀₀Is the Y electrode 3_Two, 3_Three,…
…, 3₁₀₀₀Is an address pulse applied in sequence. So
Then, in the sustain discharge period, the Y electrode 3₁~ 3₁₀₀₀When,
Sustaining discharge pulses 28 and 29 are alternately applied to the X electrode 2.
And sustain discharge is performed, and one frame image is displayed.
You. In addition, such "address / sustain discharge separate type self-extinguishing
In this case, the sustain discharge period is
Determines the brightness.

Therefore, this "address / sustain discharge separate type self-erasing address method" is used when there are many scan lines or when multi-gradation display is performed for full-color display. -195188. More specifically, FIG. 45 shows a driving method when 16-gradation display is performed as an example of multi-gradation display. In this example, one frame includes four subframes (subfields) SF1, SF2, SF.
3 and SF4.

Then, these sub-frames SF1 and SF
2, SF3, SF4, full write period Tw
_1,Tw_2,Tw_3,Tw_FourAnd address period Ta
_1,Ta _2,Ta_3,Ta_FourAre the same length
And sustain discharge (light emission) period Td_1,Td_2,Td
_3,Td_FourHas a length of 1: 2: 4: 8. But
Select the subframe that should light up the cell
16 gradations can be displayed by combining
You.

FIG. 46 shows a conventional PD shown in FIG.
It is a wave form diagram which shows the 3rd example of the conventional method of driving P, and has shown 1 drive cycle in what is called the conventional "line sequential drive and selective write address system." In this method, first, a narrow erase pulse 30 is applied to the Y electrode of the selected line.
Is applied to erase the lighting of the cell that has been lit, and thereafter, the GND level address pulse (write pulse) 31 is applied to the Y electrode of the selected line, and the Y of the non-selected line is
The potential of the electrode is held at the Vs level, the address pulse (writing pulse) 32 of the potential Va is applied to the address electrode corresponding to the cell to be lit, and the selected cell is discharged. In the selective write address method,
It is common to use a negative power supply (-Vs) for the X and Y electrodes. Therefore, the potentials of the X and Y electrodes in FIG. 46 are set to GND or −Vs.

Next, sustain discharge pulses 33 and 34 are alternately applied to the X electrode and the selected Y electrode, whereby the sustain discharge is repeated to write the display. Reference numeral 35 is a sustain discharge pulse applied to the Y electrode of the non-selected line.

[0019]

First Problem In the driving method of FIG. 42 (line-sequential driving / self-erasing address method) and the driving method of FIG. 44 (address / sustain discharge separated type / self-erasing address method), Although the display data is written by self-erase discharge, the self-erase discharge first occurs in the vicinity of the X electrode and the Y electrode of the target cell, and gradually shifts to the outside and expands. Go.
At this time, in a cell having a high discharge start voltage, the wall charge accumulation becomes relatively insufficient, sufficient self-erase discharge is not performed, and there is a problem that a display write error may occur due to an erase error. there were.

Second Problem In the driving method (line-sequential driving / selective write address method) of FIG. 46, the cell immediately after neutralization of the wall charges by the erase discharge by the narrow erase pulse 30 and the previous screen. The remaining amount of wall charges in the cell may be different from that of the cell that has not been turned on.

That is, the neutralization of the wall charges by the erase discharge using the narrow erase pulse 30 does not erase all the wall charges in the cell, but the sum of the remaining wall charges and the sustain discharge pulse starts the discharge. If the voltage is not exceeded, it will be erased. For this reason, the wall charge may be left in the cell to some extent for erasing. Therefore, the cell immediately after neutralization of the wall charge by the erase discharge by the narrow erase pulse 30 and the previous screen are lit. The residual amount of wall charges in the cell may be different from that of the cell that did not exist.

Further, when adjacent cells continue to discharge, space charges generated by the discharge fly and recombine with the residual wall charges of the erased cells to create a state in which the wall charges are close to zero. Can also be considered. In this case, unlike the residual wall charge immediately after the application of the narrow erase pulse 30,
When starting the discharge, a sufficient write voltage (Vw> V
f, Vw = Va + Vs) must be applied. On the other hand, when writing is performed in a state where there is residual wall charge immediately after the application of the narrow erase pulse 30, when a pulse is applied with a polarity in which the wall charges are overlapped, a voltage (Vw = Vf) lower than the former is applied. , Vw> Vf), discharge may occur.

As described above, in the conventional PDP drive system,
The writing voltage varies depending on the cells, and there are cells that can be written correctly and cells that cannot be written with the same voltage, which may cause a writing error. Third Problem Since a parallel type display panel such as a PDP is mostly digitally controlled, it is desirable that the brightness can be controlled by a digital method. However, in the case of performing the brightness adjustment by the multi-gradation display control method in which the address period and the sustain discharge period are separated from each other, assuming that the maximum sustain discharge frequency is around 30 kHz, for example, each sub-frame at 256 gray levels As for the number of sustain discharge cycles, discharge is always performed twice in one cycle.
This is 16 times, 32 times, 64 times, 128 times and 256 times. That is, the total number of cycles of sustain discharge is 510, and when one frame is 60 Hz, the maximum frequency of sustain discharge is 30.6 kHz. With respect to the number of sustain discharges in such a sub-frame, the number of cycles of sustain discharge in the minimum (LSB) sub-frame is 2. Therefore, the brightness adjustment can be performed only in two stages of the maximum and 1/2 thereof. It is extremely inconvenient to realize fine brightness adjustment. That is, in order to realize a display closer to a CRT in the PDP drive system, it is indispensable to have a function capable of adjusting the brightness linearly or in multiple stages, and there is a major problem in terms of function.

Since full-color display data is often an analog signal, a display based on digital control such as a PDP converts the analog signal into a digital signal for processing. In this case, the brightness can be adjusted by amplifying the analog signal in the range of 0 to 100%. However, analog signal processing may impair the quality of the original signal, so we want to avoid it as much as possible.

Further, in the brightness adjustment by such a method, the number of sustain discharge cycles is always constant even when the brightness is adjusted, and therefore many unnecessary sustain discharge pulses that do not actually discharge are applied. Therefore, it becomes impossible to reduce the reactive power. Further, the number of pulses for actually performing sustain discharge is reduced, while the number of full-scale writing is constant. As a result, there is a disadvantage that the brightness ratio of the entire lighting is increased, and when low brightness display is performed, the contrast is lowered.

The present invention has been made in view of the above problems, and it is possible to avoid writing mistakes due to insufficient self-erase discharge and to perform good image display.
It is a first object to provide a driving method and apparatus for a display panel such as P. Further, the present invention provides a display panel driving method and apparatus using a novel three-electrode / surface-discharge type AC PDP capable of avoiding the above-mentioned writing error and performing good image display. The second
It is the purpose of.

Furthermore, according to the present invention, when the multi-step brightness adjustment is performed by the three-electrode / surface-discharge AC PDP drive, which is convenient for multi-gradation display, the reactive power is reduced and the contrast is prevented from being lowered. A third object is to provide a display panel driving method and device that can be realized.

[0028]

According to the present invention, a first electrode (for example, an X electrode) and a second electrode (for example, a Y electrode) are arranged in parallel on each display line on a first substrate, and A third electrode (for example, an address electrode) is arranged on the second substrate opposite to the first substrate so as to intersect (for example, orthogonally) the first and second electrodes, and , Above first
And the display data for at least one display line cell selected by one of the second electrodes and the third electrode.
Writing discharge for writing data, and the writing discharge
Maintain discharge based on display data written by
AC type plasma display that repeats sustain discharge
The present invention relates to a method and apparatus for driving a display panel including a panel.

According to the display panel driving method of the present invention, before the address discharge, the first step of performing the address discharge of all cells in all the cells of at least one display line and the address discharge of all cells are performed. in all cells of the display line, and a second step of the all-cell erasure discharge, the second
Apply to the cell at the time of the address discharge
Electrode wall charges have the same polarity as the write pulses
The wall that is to be left over and thus left over
The electric charge is superimposed on the write pulse during the write discharge.
Cause the write discharge and the sustain discharge.
When applying a sustain discharge pulse to the above cell,
The sustain discharge is generated except for the cells that have undergone the address discharge.
It characterized in that it is a quantity such that no Flip. All here
In the cell erase discharge, the erase pulse is
The erase discharge is applied to all the applied cells.
Has the same polarity as the pulse
This is an erasing discharge for leaving an undesired amount of wall charges. one
In general, erasing discharge in the normal sense ends sustaining discharge.
Erase pulse is applied at the time of
Erasing discharge occurs only in the cell that was
All-cell erasing discharge of the present invention is for erasing electric charge.
Note that it is different from.

More preferably, in the display panel driving method of the present invention , the above plasma display panel is used.
At least the second electrode is provided for each display line.
To be independent and selected in the first step above
The all-cell write discharge using the first and second electrodes is performed in all the cells of one display line, and the second cell is discharged .
Step In, depending on applying an erase pulse to the second electrode or the first electrode of the selected one of the display lines, said all cells erased by the selected one display all the cells of the line discharge was performed, then every to emit light cell to perform the <br/> address discharge using the second and third electrodes are configured to perform the writing of the display data.

[0031] More preferably, in the driving how the display panel of the present invention, the plasma display panel
At least the second electrode is provided for each display line.
Independently becomes, in the first step, to perform the all-cell write discharge in all the cells utilizing the first and second electrodes of the selected <br/> plurality of display lines, said first 2's
Step In, depending on applying an erase pulse to the second electrode or the first electrode of the selected plurality of display lines, said total cell erase discharge in all cells of the plurality of display lines which are the selected was performed, then every to emit light cell to perform the above manual <br/> inclusive discharge using the second and third electrodes are configured to perform the writing of the display data.

More preferably, in the display panel driving method of the present invention , the above plasma display panel is used.
At least the second electrode is provided for each display line.
Independently becomes, in the first step, in all cells of all display lines to perform the above <br/> total cell write discharge using the first and second electrodes, in the above second step ,
In applying an erase pulse to the second electrode or the first electrode of the more lines Therefore, to perform the all-cell erase discharge in all cells of the whole display lines, then, the one selected for each display line sequentially, with to emit light cell to perform the write discharge using the second and third electrodes to perform a write of the display data, writing of the display data is terminated per more lines after, and to perform the sustain discharge in the cell to emit light in all the display lines using the said first and second electrodes.

More preferably, in the display panel driving method of the present invention , the above plasma display panel is used.
At least the second electrode is provided for each display line.
Independently becomes, in the first step, in all cells of all display lines to perform the utilization was the all-cell write discharge the first and second electrodes, in the second step,
In applying an erase pulse to the second electrode or the first electrode of the more lines Therefore, to perform the all-cell erase discharge in all cells of the whole display lines, then, the one selected for each display line sequentially, with to emit light cell to perform the write discharge using the second and third electrodes and executes the writing of the display data,
Then, immediately, the to perform the sustain discharge for the wall charge stability by applying the sustain pulse to the first electrode, after the writing of the display data is completed per more lines, emit light of all the display lines First in above cell
And the above-mentioned sustain discharge utilizing the second electrode is performed.

More preferably, in the display panel driving method of the present invention, the first electrode is commonly connected to each block formed by dividing the display line into a plurality of blocks, and the second electrode is In a display panel composed of a plasma display panel or the like which is independent for each display line, after all cells address discharge using the first and second electrodes in all cells of all display lines, All cells are erase-discharged in all cells of all display lines by applying an erase pulse to the second electrode or the first electrode of all display lines with or without sustain discharge, and then select For each of the displayed display lines,
Writing discharge using the second and third electrodes is performed in the cells to emit light to write display data, and immediately thereafter, a sustain discharge pulse is applied to the first electrode of the block including the cells to emit light. After the display data has been written to all the display lines, the sustain discharge for stabilizing the wall charges is performed by applying the voltage. Then, the cells using the first and second electrodes are maintained in the cells to emit light in all the display lines. I am trying to discharge.

More preferably, in the display panel driving method of the present invention, two adjacent two electrodes out of a plurality of second electrodes that are continuously selected and driven for writing display data. electrodes, in the display panel of a plasma display panel or the like constituting disposed so as to sandwich between the plurality of first electrodes which are driven by a single driver circuit, a second non-selected display lines The voltage applied to the electrodes is set lower than the potential of the sustain discharge pulse or equal to the address voltage.

More preferably, in the display panel driving method of the present invention, the erase discharge using the first and second electrodes is performed immediately before the all-cell write discharge is performed . More preferably, in the display panel driving method of the present invention, the sustain discharge is performed immediately after the all-cell write discharge is performed by applying a narrow pulse that does not result in the erase discharge.

On the other hand, in the display panel driving device of the present invention, the first and second electrodes are arranged in parallel on each display line on the first substrate, and the second electrode facing the first substrate is provided. A third electrode on the substrate of the second electrode so as to intersect the first and second electrodes, and at least one display selected by one of the first and second electrodes and the third electrode. A display panel comprising an AC plasma display panel, which repeatedly performs a write discharge for writing display data to cells of a line and a sustain discharge for maintaining a discharge based on the display data written by the write discharge, A drive means for supplying a plurality of types of drive voltage pulses to the first electrode, the second electrode, and the third electrode, and an order for supplying the plurality of types of drive voltage pulses are provided. Control means for controlling all of the cells in at least one display line to perform all-cell write discharge by the driving means, and then perform all-cell write discharge by the driving means. All cells of the display line are erased by all cells, so that the write pulse applied to the cells at the time of the address discharge is applied.
Scan is by <br/> urchin configured to leave wall charges perforated on the electrode of the same polarity and, in this way residual wall charge, the
When writing discharge, the writing pulse is superimposed on the writing pulse.
Discharge for the above sustain discharge.
When the sustained discharge pulse is applied to the cell,
The above-mentioned sustain discharge does not occur except for the charged cells.
It characterized in that an amount.

Preferably , in the display panel drive device of the present invention , the control means is selected by the drive means.
A write pulse for in-option has been one of all cells of the display lines perform utilizing the aforementioned all-cell write discharge the first and second electrode is applied, then one <br/> selected display of the the erase pulse for performing the all-cell erasure discharge on the second electrode or the first electrode line is applied, then
In, and to perform the write discharge using the second and third electrodes per to emit light cell control to apply a write pulse for writing the display data
Gyosu that.

More preferably, in the display panel drive device of the present invention , the control means is the drive means.
Ri, application of address pulse for performing the all-cell write discharge in all the cells utilizing the first and second electrodes of the plurality of display lines which is selected, then the selection of the
On the second electrode or the first electrode of the plurality of display lines
Serial and applying an erase pulse for the all-cell erase discharge, its
After the above, the second and third cells to be made to emit light are
The display de made to perform the above address discharge using an electrode
To apply a write pulse to write data
Control to. More preferably, in the driving device for a display panel of the present invention, the control means, by the drive means, for performing the all-cell write discharge in all the cells utilizing the first and second electrodes of all the display lines of the write pulse is applied, then applying the erase pulse for performing the all-cell erasure discharge on the second electrode or the first electrode of the more lines, then, for each one display line selected to sequentially, the second per cell to emit light
And the address discharge using a third electrode Te row Align
The writing of the display data by applying a write pulse of the line Utame, writing of the display data per all the display lines is final
After completing the above, in the cells that should emit light in all display lines,
1 and that controls so as to apply the sustain pulses for performing the sustain discharge using the second electrode.

More preferably, in the display panel of the present invention, an insulating layer for isolating the third electrode from the discharge space formed between the third electrode and the first and second electrodes. Is provided so that the wall charges are accumulated on the insulating layer. On the other hand, the plasma display of the present invention
Display panel such as display panel can be driven by 1 screen
Each frame constituting the surface has a predetermined brightness.
It consists of multiple subframes, each subframe
The above first step of performing all-cell write discharge
Second step of performing cell erasing discharge and display data
The above-mentioned address discharge is executed for each display line.
Based on the display data above
There is a sustain discharge period in which sustain discharge is performed to maintain discharge.
However, it is applied to a case where gradation display is performed by selecting an arbitrary subframe . In this case, preferably, the number of sustain discharges in each of the subframes is increased / decreased at the same ratio to control the luminance over the entire screen.

More preferably, when driving for gradation display is performed by the driving method of the present invention, the number of sustain discharges in the sub-frame having the maximum luminance weight is determined, and the next number is determined based on the determined number. Then, the number of sustain discharges in a subframe having a large luminance weight is determined, and thereafter, based on the number of sustain discharges in a subframe whose luminance weight is one rank higher, the number of sustain discharges in that subframe is determined. I try to determine the number of times.

More preferably, when driving for gradation display is performed by the driving method of the present invention, the number of sustain discharges in the subframe is maintained in the subframe in which the magnitude of the luminance weight is one rank higher. 1/2 the number of discharges
Is set to More preferably, when the number of sustain discharges is determined by the driving method of the present invention, if the fraction is set by setting the above-mentioned 1/2, the fraction is rounded down or rounded up. .

Further, the plasma display of the present invention
・ Driving devices for display panels such as panels compose one screen
One frame has a plurality of sub
Each sub-frame consists of a frame
Full write / erase that only discharges and erases all cells
The above-mentioned writing discharge for writing the period and display data
Address period for each display line, and
Perform sustain discharge that maintains discharge based on display data
Has a sustain discharge period and selects any subframe
This is applied to the case where gradation display is performed. in this case,
Preferably, the first means for determining the number of sustain discharges in the subframe having the maximum luminance weight, and the number of sustain discharges in the subframe having the next largest luminance weight are determined based on the determined number. Second means are provided.

More preferably, when the number of sustain discharges in a subframe becomes 0 when the brightness adjustment is performed using the first and second means, the operation to be performed in the subframe is stopped. It further comprises means for More preferably, when performing the brightness adjustment in the driving apparatus of the present invention, a means for holding data for determining the number of sustain discharges in the next subframe of the subframe, and the number of sustain discharges in the subframe are counted. It further comprises means, means for comparing the counted value with the held data, and means for instructing the transition to the next subframe when the two match based on this comparison.

More preferably, when adjusting the brightness in the driving apparatus of the present invention, the first means has means for arbitrarily setting the number of sustain discharges in the sub-frame having the maximum brightness weight. There is.

[0046]

In order to make the characteristics of driving the display panel of the present invention more understandable, the operation principle of the present invention will be described with reference to the drive model of FIG. Note that the AC PDP will be described as a typical example here. For comparison with the present invention, the drive model and drive waveform of the conventional 2-electrode PDP are shown in FIG. 2, and the drive model and drive waveform of the conventional 3-electrode / self-erase address PDP are shown in FIG. Shown, conventional 3
FIG. 4 shows the drive model and drive waveform of the electrode / selective write address type PDP.

In FIG. 1, a first electrode (X electrode 2 in FIG. 1) and a second electrode (Y electrode 3 _{k in} FIG. 1) are provided on a first substrate (omitted in FIG. 1) for each display line. A second substrate (see FIG. 1) that is arranged in parallel and faces the first substrate.
The third electrode (address electrode 4 _{k in} FIG. 1)
Are arranged so as to be orthogonal to the first and second electrodes. Further, in the discharge space of each cell formed between the first and second electrodes and the third electrode, light emission display is performed by address discharge using a memory function. Further, in order to accumulate the charges generated in the discharge space by the address discharge as wall charges on the electrode side, an insulating layer for isolating the address electrode 4 _k from the discharge space (in FIG. 1,
Phosphor 12 or dielectric layer) and an insulating layer (protective film 11 or dielectric layer in FIG. 1) for isolating the X electrode 2 and the Y electrode 3 _k from the discharge space. There is.

Here, the Y electrode 3 _k and the address electrode 4
_{When a} cell is selected by _k to perform address discharge, first, as a first step, an address pulse having a voltage Vw is applied to the X electrode 2 to correspond to the ground potential (equivalent to GND potential: 0).
The address discharge is generated between the Y electrode _{3k of} V). That is, all-cell write discharge is performed on all cells on the selected display line, and positive charges (ions) are accumulated on the address electrode 4 _K side. As the second stage, the voltage Vs (Vs <
A sustain discharge pulse consisting of Vw) is applied to the Y electrode 3 _k ,
All cells of the selected display line are sustain-discharged. In the third step, an erase pulse having a voltage of Vs (or Vs or less) is applied to the X electrode 2 to cause all cells of the selected display line to be erase-discharged. That is, the wall charges on the sustain discharge electrode side (the discharge surfaces on the Y electrode side and the X electrode side) are reduced until the potential difference is such that no discharge occurs even when the sustain discharge pulse is applied. At this stage, if negative wall charges (electrons) can be left on the Y electrode side, it effectively acts on the selective write discharge in the next stage.
As a fourth step, an address pulse having a voltage Va is applied to the address electrode 4 _k by utilizing the wall charges on the address electrode side, and selective write discharge (address discharge) of cells is performed.

That is, the driving method of the present invention is characterized in that the wall charges that effectively act on the selective write discharge are accumulated on the address electrode side (phosphor 12 or dielectric layer) before the selective write discharge is performed. To do. Further, by accumulating charges having the opposite polarity to the address electrode side on the sustain discharge electrode side involved in the selective write discharge, it becomes more effective for the selective write discharge. As a means for realizing this wall charge storage operation, at least two steps of the above all-cell write discharge and all-cell erase discharge are required.

On the other hand, the conventional two-electrode type P shown in FIG.
In a driving method of a DP (for example, a neon orange monochrome PDP), first, a first stage is an all-cell write discharge, and then a second stage is an all-cell sustain discharge. Further, as a third step, a narrow erase pulse is applied to the selected cell to perform selective erase discharge. The non-selected cells (lighted cells) prevent the erase discharge by inserting a cancel pulse of the voltage Vs into the X electrodes. Here, it is utilized that electrons and ions generated in the lighting state of the first stage remain as a residual space charge for a relatively long time after the end of discharge. However, in this case, unlike the present invention, no operation of accumulating wall charges is performed before the selective erase discharge (selective write discharge) is performed.

Further, in the conventional method of driving the three-electrode / self-erasing address type PDP shown in FIG. 3, first, the first step is all-cell write discharge, and then the second step is all-cell sustain discharge. To perform. Furthermore, as a third step, a sustain discharge is generated between the X electrode and the Y electrode, and at the same time, a selective write discharge is generated between the address electrode and the Y electrode. A large amount of wall charges are generated by this selective writing discharge. Further, as the fourth step, when the potential difference between the X electrode and the Y electrode is set to 0, the discharge is started with the voltage of only the wall charges. In this case, since there is no potential difference between the X electrode and the Y electrode, the space charge generated by the discharge neutralizes and disappears without becoming wall charge. The selective erase discharge (self-erase discharge) is completed here. Again, no operation of accumulating wall charges on the address electrode side is performed before the selective erasing discharge is performed.

Further, in the conventional method of driving the three-electrode / selective-write address type PDP shown in FIG.
In a step, all cells of the selected display line are subjected to all-cell erasing discharge to surely erase the wall charges. Next, as a second step, an address pulse is applied to the address electrode side to perform selective address discharge (address discharge) of cells. In this case as well, the operation of accumulating wall charges on the address electrode side is not performed at all before the selective write discharge is performed.

As described above, none of the conventional techniques utilize the feature of the present invention that the effective charges for the selective address discharge are stored in advance by performing the all-cell address discharge and the all-cell erase discharge. More specifically, in the present invention, before the display data is written, all the cells of the selected one display line are written, and then the erase discharge is performed in all the cells of the selected one display line. Therefore, the states of all the cells of one selected display line can be made uniform, and a writing error can be avoided in the line-sequential driving method.

More specifically, in the present invention, before writing the display data, writing is performed to all the cells of the plurality of selected display lines, and then the erasing is performed in all the cells of the plurality of selected display lines. Since the discharge is performed, the states of all the cells of the plurality of selected display lines can be made uniform, and a writing error can be avoided in the multiple line sequential driving method.

More specifically, in the present invention, before writing the display data, after writing all the cells of all the display lines, erasing discharge is performed in all the cells of all the display lines. In addition, the states of all cells on all display lines can be made uniform, and writing mistakes can be avoided especially in the address / sustain discharge separation drive method.

More specifically, in the present invention, before writing the display data, after writing all the cells of all the display lines, the erase discharge is performed in all the cells of all the display lines. , It is possible to make the state of all cells of all display lines uniform, avoid writing mistakes in the address / sustain discharge separate drive method, and sequentially turn on each selected display line. After the display discharge is written by performing the write discharge using the Y electrode and the address electrode in the cell to be caused, the sustain discharge is immediately applied to the X electrode to perform the sustain discharge for stabilizing the wall charges. Therefore, the wall charges can be stabilized until the sustain discharge period.

More specifically, in the present invention, the X electrodes are commonly connected to each block formed by dividing the display line into a plurality of blocks.
Writing errors can be avoided, wall charges can be stabilized until the sustain discharge period, and power consumption can be reduced by sustain discharge pulses for wall charge stabilization in the address period. be able to.

That is, in this case, during the address period for writing the display data, the sustain discharge pulse for stabilizing the wall charges is applied only to the X electrodes of the block including the display line for writing the display data. However, it is not necessary to apply the sustain discharge pulse for stabilizing the wall charges to the X electrodes of the block that does not include the display line for writing.

More specifically, in the present invention, the voltage applied to the Y electrode of the non-selected line is set to a low potential,
Abnormal discharge between adjacent Y electrodes in the XY-Y-X arrangement is avoided. Here, the abnormal discharge will be described in detail. The present applicant has previously devised the arrangement of the Y electrodes and the X electrodes so as to suppress the reactive power due to the parasitic capacitance between the two electrodes (Japanese Patent Application No. 4-3234, 1992). January 10
Japanese application).

[0060] This is because, as shown in FIG. 47, the address electrodes A _1, A _2, ......, between X electrodes orthogonal to A _M, 2
Book Y electrodes (eg Y ₁ and Y ₂ , Y ₃ and Y ₄ , ...,
Y _{N- 1} and Y _N ) are sandwiched between them, and XY-
It is a Y-X array. According to this, the facing distance between the X electrode and the Y electrode can be halved as compared with a general X, Y electrode arrangement (X-Y-X-Y arrangement), and parasitic capacitance can be suppressed to reduce reactive power. However, the following inconvenience may occur depending on the driving method. In FIG. 48, a range surrounded by a broken line is a schematic representation of a cross section of two discharge cells included in one unit of the XY-Y-X arrangement. Now, as shown in (a) of the same figure, GND (0 V) is applied to the address electrode, and XY-Y-X is also applied.
After applying Vs to the electrodes, as shown in FIG.
Va for the address electrode and the Y electrode (Y
_When GND (selection pulse) is applied to ₁ ), discharge occurs in the cell of Y ₁ and positive wall charges are formed. In this state, as shown in FIG. 49A, the adjacent Y electrode (Y ₂ )
When a GND (selection pulse) is applied to Y, as shown in (b) of FIG.
An abnormal discharge occurs between the cell of the electrode (Y ₁ ) and the cell of the Y electrode (Y ₂ ), and as a result, the negative wall charges are excessively accumulated in the cell of the Y electrode (Y ₁ ) and are maintained thereafter. This causes an inconvenience that discharge cannot be performed. Although the above description is for the write address type PDP, the erase address type PDP
The same applies to the case of P.

That is, as shown in FIG.
After applying GND to the address electrode and the X electrode and Vs to the Y electrode, as shown in FIG. 7B, Va is applied to the address electrode and the Y electrode (Y ₁ ) of the selection line. When a GND (selection pulse) is applied to, a discharge is generated in the cell of the Y electrode (Y ₁ ) and a positive wall charge is formed. In this state, when a GND (selection pulse) is applied to the adjacent Y electrode (Y ₂ ) as shown in FIG. 51A, the address discharge has already been performed as shown in FIG. An abnormal discharge occurs between the cell of the Y electrode (Y ₁ ) and the cell of the Y electrode (Y ₂ ) in which the wall charge is formed. As a result, the cells of the Y electrode (Y ₁ ) are ready for sustain discharge, but the Y electrode (Y ₂ )
In this case, the sustain discharge becomes impossible (erased state).

The abnormal discharge in the XY-Y-X array is caused by applying a low potential to the voltage applied to the Y electrode of the non-selected line,
For example, it can be avoided by lowering the potential of the sustain discharge pulse or by making it equal to the address voltage. This is because the effective voltage applied to the discharge space between the adjacent Y electrodes can be suppressed below the discharge start voltage. On the other hand, when performing driving for gradation display by the driving method of the present invention, the number of sustain discharges in the sub-frame having the maximum luminance weight is determined, and next, based on the determined number, the luminance The number of sustain discharges in a subframe having a large weight is determined, and thereafter, the magnitude of the luminance weight is 1 in the same manner.
The number of sustain discharges in the sub-frame on the rank is determined based on the number of sustain discharges in the sub-frame.

According to the above configuration, when the number of sustain discharges in each subframe is determined, the number of sustain discharges is increased / decreased by the same ratio. Therefore, for example, in a device of 64 to 256 gradation display, digital control is performed. High-precision multi-step brightness adjustment without writing errors is possible, and CR
A display form closer to T can be realized. Also,
In the case where a subframe that does not perform sustain discharge is further provided with means for stopping the operation that should be originally performed (for example, means for interrupting the application of the high voltage pulse), useless power consumption can be eliminated, and wall charge accumulation can be achieved. With the effect of, it becomes possible to drive with much smaller power consumption than the conventional one. Further, in the sub-frame in which the sustain discharge is not performed, neither full writing nor full erasing is performed, so that the number of background points is reduced, so that it is possible to prevent the deterioration of contrast and to obtain high contrast even at low brightness. Good display is possible.

[0064]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will now be described with reference to FIGS.
Examples to 13th examples will be described. First Embodiment FIG. 5 FIG. 5 is a waveform diagram showing a first embodiment of the present invention, showing one drive cycle. The first embodiment is a method for driving the PDP shown in FIG. 39 and is a case where line sequential driving is performed.

In this embodiment, first, the Y electrode of the selected line is set to the GND level, the potential of the Y electrode of the non-selected line is held at the Vs level, and the write pulse 36 having the potential Vw is applied to the X electrode 2. , All cells on the selected line are discharged. Subsequently, the potential of the Y electrode of the selection line is returned to the voltage Vs, and the sustain discharge pulse 37 is applied to the X electrode 2.
Is applied and sustain discharge is performed, then a narrow erase pulse 38 is applied to the Y electrode of the selected line, and erase discharge is performed in all cells of the selected line.

Next, a GND level address pulse (write pulse) 39 is applied to the Y electrode of the selected line, the potential of the Y electrode of the non-selected line is held at the Vs level, and the address corresponding to the cell to be lit is held. An address pulse (writing pulse) 40 having a voltage Va is applied to the electrodes, and the cells selected as the cells to be lighted are discharged.

Next, sustain discharge pulses 41 and 42 are alternately applied to the X electrode 2 and the Y electrode of the selected line, whereby the sustain discharge is repeated. In this way, the display data is written to the selected line. In addition, 4
Reference numeral 3 is a sustain discharge pulse applied to the Y electrode of the non-selected line. In the first embodiment, the write discharge is performed in all the cells of the selected line before the display data is written in the selected line, and then the erase discharge is performed in all the cells of the selected line. The state of all cells on the selected line can be made uniform, and in the line-sequential driving method, writing error can be avoided and good image display can be performed.

Second Embodiment FIG. 6 FIG. 6 is a waveform diagram showing a second embodiment of the present invention, showing one driving cycle. This second embodiment is also a method for driving the PDP shown in FIG. 39 , similarly to the first embodiment.
This is a case where line-sequential driving is performed. In the second embodiment, a wide erase pulse (a pulse having a small voltage value) 44 is applied as an erase pulse to be applied to the Y electrode of the selected line, and the others are driven similarly to the first embodiment. It is a thing.

In the second embodiment as well, the state of all cells on the selected line can be made uniform before the display data is written to the selected line. Therefore, as in the first embodiment, In the line-sequential driving method, writing error can be avoided and good image display can be performed. Third Embodiment FIG. 7 FIG. 7 is a waveform diagram showing a third embodiment of the present invention, showing one driving cycle. This third embodiment is also a method for driving the PDP shown in FIG. 39 similarly to the first embodiment.
This is a case where line-sequential driving is performed.

In the third embodiment, instead of the narrow erase pulse 38 shown in FIG. 5, a narrow erase pulse 45 is applied to the X electrode 2. Therefore, before applying the narrow erase pulse 45 to the X electrode 2, the sustain discharge pulse 46 is applied to the Y electrode of the selected line to accumulate negative wall charges in the MgO film on the X electrode of the selected line. , To store positive wall charges in the MgO film on the Y electrode of the selected line,
An erase discharge is generated by the narrow erase pulse 45. Others are the same as those in the first embodiment.

In the third embodiment as well, it is possible to make the state of all cells on the selected line uniform before writing the display data to the selected line. Therefore, similar to the first embodiment. In the line-sequential driving method, writing error can be avoided and good image display can be performed. Fourth Embodiment FIG. 8 and FIG. 9 FIG. 8 is a waveform diagram showing a fourth embodiment of the present invention, showing one driving cycle. Like the first embodiment, the fourth embodiment is also a method of driving the PDP shown in FIG. 39. However, unlike the first embodiment, it is a case of performing multiple line sequential driving.

In this fourth embodiment, two display lines 7 are provided.
m and 7n are selected, the Y electrodes of the selected lines 7m and 7n are set to the GND level, and the potential of the Y electrodes of the non-selected lines is V
The write pulse 47 having the voltage Vw is applied to the X electrode 2 while being held at the s level, and the discharge is performed in all the cells of the select lines 7m and 7n. Then, the potentials of the Y electrodes of the selection lines 7m and 7n are returned to the voltage Vs, and the sustain discharge pulse 48 is applied to the X electrodes 2 to perform the sustain discharge, and then to the Y electrodes of the selection lines 7m and 7n. Narrow erase pulse 4
9, 50 are applied, and the erase discharge is performed in all the cells of the selection lines 7m, 7n.

Next, G is applied to the Y electrode of one selection line 7m.
An address pulse (write pulse) 51 of ND level is applied, the potential is held at the Vs level on the Y electrode of the other selected line 7n and the Y electrode of the non-selected line, and the address electrode arranged in the cell to be lit. An address pulse (writing pulse) 52 having a voltage Va is applied to the discharge cell 7 to discharge the selected cell on the one selection line 7m.

Subsequently, a GND level address pulse (writing pulse) 53 is applied to the Y electrode of the other selected line 7n, and the potentials of the Y electrode of the one selected line 7m and the Y electrode of the non-selected line are set to the Vs level. The address pulse (writing pulse) 54 of the voltage Va is applied to the address electrode arranged in the cell to be held and lit, and the cell selected in the other select line 7n is discharged.

Next, the X electrode 2 and the selection lines 7m and 7n
The sustain discharge pulses 55 and 56 are alternately applied to the Y electrodes of the above, and thereby the sustain discharge is repeated. In this way, the display data is written to the selected lines 7m and 7n. Reference numeral 57 is a sustain discharge pulse applied to the Y electrode of the non-selected line. In addition, in FIG.
It is a time chart showing how selected lines are selected,
In the figure, "W" is the drive cycle for writing the current frame,
“S” is a drive cycle of only the sustain discharge of the current frame,
“W” is a drive cycle for writing in the previous frame, and “s” is a drive cycle for only sustain discharge in the previous frame.

Also in the fourth embodiment, in the multiple line sequential driving method, the state of all cells on the selected line can be made uniform before the display data is written to the selected line. In the line-sequential driving method, writing error can be avoided and good image display can be performed. In the fourth embodiment, as the erase pulse, the narrow erase pulse 4 is applied to the Y electrodes of the selection lines 7m and 7n.
I am trying to apply 9,50, but instead of this,
A wide erase pulse is applied to the Y electrode of the selected line, and
A narrow erase pulse may be applied to the X electrode.

Fifth Embodiment FIG. 10 FIG. 10 is a waveform diagram showing a fifth embodiment of the present invention, showing one driving cycle. Like the first embodiment, the fifth embodiment is also a method of driving the PDP shown in FIG. 39, but is different from the first embodiment in the case of address / sustain discharge separation driving. In the fifth embodiment, one frame is divided into a full-face write / erase period, an address period, and a sustain discharge period. In the entire address erase period, considering the case where there are discharge cells that are lit and discharge cells that are not lit in the previous frame, the state of all discharge cells is made uniform, that is, wall charge is applied to all discharge cells. It is a period for creating a state that does not remain.

Here, in the entire program erase period,
First, the Y electrodes 3 _{1 to} 3 ₁₀₀₀ are set to the GND level, the write pulse 58 having the voltage Vw is applied to the X electrode 2,
All cells are discharged. Then, the Y electrodes 3 _{1 to} 3 ₁₀₀₀
After the sustain discharge pulse 59 is applied to the X electrode 2 and the sustain discharge is performed, the narrow erase pulse 60 is applied to the Y electrodes 3 _{1 to} 3 ₁₀₀₀ to erase the discharge. Done. In this way, the full-face write / erase is completed.

Next, in the address period, the display data is written in order from the display line 7 _1. This is done as follows. First, the Y electrode 3 address pulse 61 _first GND level ₁ is applied, 4 ₁ in to 4 _M address electrodes, selectively address pulse 62 of the voltage Va to the address electrodes are arranged in the cell to be lighted is Is applied to discharge the cells to be lit. Thus, writing of the display data is completed with respect to the display line _71.

Hereinafter, the display line 7_Two~ 7₁₀₀₀Also about
The same operation is performed in order, and all display lines 7₁~ 7₁₀₀₀To
Then, the display data is written. 61_2,
61 _Three, ……, 61₁₀₀₀Is the Y electrode 3_2,3_Three, ……,
3₁₀₀₀Is an address pulse applied in sequence. next,
In the sustain discharge period, the Y electrode 3₁~ 3₁₀₀₀And the X electrode
The sustain discharge pulses 63 and 64 are alternately applied to 2 and
Sustaining discharge is performed and image display of one frame is performed.

According to the fifth embodiment, the erase discharge is performed in all the cells in all the display lines after writing in all the cells in all the display lines before writing the display data. The state of all cells on all display lines can be made uniform, and writing errors can be avoided in the address / sustain discharge separation driving method, and good image display can be performed.

Sixth Embodiment FIG. 11 FIG. 11 is a waveform diagram showing a sixth embodiment of the present invention, showing one driving cycle. Like the first embodiment, the sixth embodiment is also a method of driving the PDP shown in FIG. 39, but is different from the first embodiment in the case of address / sustain discharge separation driving. Here, in the fifth embodiment described above (FIG. 10), the address pulse 61 _{1-61 1000} applied to the Y electrodes 3 ₁ to 3 _1000, for display data written by the address pulse 62 is applied to the address electrodes I am trying to cause a discharge.

When discharge is generated in this manner, excessive wall charge is generated.
Address pulse 61₁Direct application of
After that, the wall charge becomes unstable, and the address pulse 61₁Sign of
Immediately after the addition was completed, discharge was generated only by the voltage due to the wall charges.
In some cases, the wall charges are neutralized. Sixth
The example is a driving method that solves this problem.
Respulse 61_{1 ,}61_Two, ……, 61₁₀₀₀Direct application of
After that, a sustain discharge pulse 65 is applied to the X electrode 2._1,65 _Two, ……,
65₁₀₀₀Is applied to keep the wall charge stable until the sustain discharge period.
I try to maintain it.

According to the sixth embodiment, similar to the fifth embodiment, in the address / sustain discharge separation driving method, writing error can be avoided, good image display can be performed, and display data writing can be performed. After that, the wall charges can be maintained in a stable state until the sustain discharge period. However, according to the sixth embodiment, during the address period, sustain discharge pulses 65 _{1 to} 65 applied to the X electrode 2 after address writing.
₁₀₀₀ is applied even to the cells of the display line which are not the target of writing the display data.

For example, when the display data is written to the display line 7 ₁ , the sustain discharge pulse 65 ₁ is also applied to the display lines 7 _{2 to} 7 ₁₀₀₀ which are not the target of the display data writing. Further, when the display data is written to the display line 7 ₂ , the sustain discharge pulse 65 ₂ is not the target of the display data writing, the display lines 7 _1, 7 ₃ , ...,
7 ₁₀₀₀ is also applied.

Here, as shown in FIG. 12, between the X electrode 2 and the Y electrode 3 _K , the capacitance 66 of the dielectric layer between the X electrode 2 and the discharge space and the dielectric on the X electrode 2 are provided. Capacity 67, Y of discharge space between body layer surface and dielectric layer surface on Y electrode 3 _K
There is a dielectric layer capacitance 68 between the electrode 3 _K and the discharge space. Further, since the X electrode 2 and the Y electrode 3 _K are formed on the same substrate, there is a capacitance Cx between both electrodes without a discharge space.

As a result, during the address period, applying the sustain discharge pulse to the discharge cells of the display lines which are not the target of writing the display data means that the capacity of the cells of the display lines which are not the target of the writing of display data (the discharge space is A charging / discharging current also flows through the non-intermediate capacity Cx), which causes an increase in power consumption. The seventh embodiment described below is intended to reduce the power consumption.

Seventh Embodiment FIG. 13 to FIG. 16 FIG. 13 is a schematic plan view showing a seventh embodiment of the present invention, in which 69 is a panel body, 70 _1, 70 ₂ , 70 ₃
And 70 ₄ are X electrodes, 71 ₁ , 71 ₂ , ..., 71
₁₀₀₀ is a Y electrode. In addition, 72 ₁ , 72 ₂ , ..., 7
2 _M is an address electrode, and a pair of X electrode, Y electrode and 1
M × 1000 cells 73 are formed at the intersections with the address electrodes of the book. In addition, 74 is a wall which partitions the cell 73, and 75 ₁ , 75 ₂ , ..., 75 ₁₀₀₀ are display lines.

That is, in the seventh embodiment, the table
Line 75₁~ 75₁₀₀₀Is a display of 250 consecutive lines
Line 75₁~ 75_250,75₂₅₁~ 75₅₀₀, 75
₅₀₁~ 75_750,75₇₅₁~ 75₁₀₀₀4 blocks each
Ku 76₁~ 76_FourBlocked into these blocks 7
6₁~ 76_FourX electrodes 70 commonly connected to each₁~ 70
_FourIs provided.

FIG. 14 shows the PDP of the seventh embodiment and its peripheral circuits. In the figure, 77 ₁ , 77 ₂ ,
77 ₃ and 77 ₄ are the X electrodes 70 ₁ and 70 ₄ , respectively.
X-side driver circuit for supplying address pulses and sustain discharge pulses to ₂ , 70 ₃ and 70 ₄ , 78 ₁ is Y electrode 7
Y-side driver IC supplying address pulses to 1 _{1 to} 71 ₂₅₀ , 78 ₂ Y-side driver IC supplying address pulses to Y electrodes 71 _{251 to} 71 ₅₀₀ , 78 ₃ Y-electrode 7
1 _{501-71 750} Y-side driver IC supplies an address pulse, 78 ₄ Y-side driver IC supplies an address pulse to the Y electrode 71 _{751-71 1000,} 79 Y electrodes 7
Y-side driver circuit for supplying pulses other than address pulses to 1 _{1 to} 71 ₁₀₀₀ , and 80 ₁ to 80 ₅ are address electrodes 7
An address driver IC for supplying address pulses to 2 _{1 to} 72 _M , 81 is an X side driver circuit 77 _{1 to} 77 ₄ , Y
Side driver ICs 78 _{1 to} 78 ₄ and Y side driver circuit 79
And a control circuit for controlling the address driver ICs 80 ₁ to 80 ₅ .

FIGS. 15 and 16 are waveform charts showing a method of driving the PDP of the seventh embodiment. In this example, one frame is divided into a full write and erase period, an address period, and a sustain discharge period, and the address period is further divided into first to fourth address periods. In the whole area write / erase period, first, the Y electrodes 71 _{1 to} 71 _1
1000 is set to the GND level, the write pulse 82 having the voltage Vw is applied to the X electrodes 70 ₁ to 70 ₄ , and the discharge is performed in all the cells of all the display lines 75 ₁ to 75 ₁₀₀₀ .

Then, the potentials of the Y electrodes 71 _{1 to} 71 ₁₀₀₀ are returned to the voltage Vs, and the sustain discharge pulse 83 is applied to the X electrodes 70 ₁ to 70 ₄ to carry out the sustain discharge.
A narrow erase pulse 84 is applied to the Y electrodes 71 _{1 to} 71 ₁₀₀₀ to cause erase discharge. In this way, the entire write / erase operation is completed. Next, in the address period, writing is sequentially performed from the display line 75 ₁ and this is performed as follows. First, in the first address period, the GND level address pulse 85 ₁ is applied to the Y electrode 71 ₁ and the address electrodes 72 _{1 to} 72 _{1
During M} , the address pulse 86 of the voltage Va is selectively applied to the address electrode corresponding to the cell to be lighted, and the cell to be lighted is discharged.

Immediately thereafter, the sustain discharge pulse 87 ₁ is applied to the X electrode 70 _1, and the sustain discharge for maintaining the wall charges in the stable state until the sustain discharge period is performed, whereby the display line 75 ₁ is discharged. Writing of display data is completed. Hereinafter, the display line 75 _{2-75 250} also sequentially, the same operation is performed, the writing of the display data for all the display lines 75 ₁ to 75 ₂₅₀ of block ₇₆₁ is performed.

In addition, 85 _{2 to} 85 ₂₅₀ are Y electrodes 71 ₂ to
71 ₂₅₀ , address pulses sequentially applied to ₂₅₀ , 87 ₂ to 8
7 ₂₅₀ is a sustain discharge pulse applied to the X electrode 70 ₁ following the address pulses 85 _{2 to} 85 ₂₅₀ . Next, in the second address period, the GND level address pulse 85 ₂₅₁ is applied to the Y electrode 71 ₂₅₁ and the voltage Va applied to the address electrode corresponding to the discharge cell to be lit among the address electrodes 72 _{1 to} 72 _M. Address pulse 86
Is selectively applied to discharge the cells to be lit.

Immediately thereafter, the sustain discharge pulse 87 ₂₅₁ is applied to the X electrode 70 _2, and the sustain discharge for maintaining the wall charges in a stable state until the sustain discharge period is performed, thereby displaying on the display line 75 ₂₅₁ . Data writing is complete. Hereinafter, the display line 75 _{252-75 500} also sequentially the same operation is performed, the writing of the display line is performed for all the display lines 75 _{252-75 500} block 76 _2.

85 _{252 to} 85 ₅₀₀ are Y electrodes 71.
Address pulse sequentially applied to _{252 to} 71 ₅₀₀ , 87
_{252-87 500} is sustain discharge pulse applied to the X electrode 70 ₂ Following the address pulse 85 _{252-85 500.} Next, in the third address period, the Y electrode 71 ₅₀₁
Together with the address pulses 85 ₅₀₁ of the GND level is applied to, in the address electrodes 72 ₁ to 72 _M, the address pulse 86 of the voltage Va is selectively applied to the address electrodes corresponding to cells to be lit, the cell to be lighted Is discharged.

Immediately thereafter, the sustain discharge pulse 87 ₅₀₁ is applied to the X electrode 70 _3, and the sustain discharge for maintaining the wall charges in a stable state until the sustain discharge period is performed, whereby the display line 75 _{501 is} displayed. Data writing is complete. Hereinafter, the display line 75 _{502-75 750} also sequentially the same operation is performed, the writing of the display data in all the display lines 75 _{502-75 750} block ₇₆₃ is performed.

85 _{502 to} 85 ₇₅₀ are Y electrodes 71.
_{502 to} 71 ₇₅₀ address pulses sequentially applied, 87
_{502 to} 87 ₇₅₀ are sustain discharge pulses applied to the X electrode 70 ₃ after the address pulses 85 _{502 to} 85 ₇₅₀ . Next, in the fourth address period, the Y electrode 71 ₇₅₁
Together with the address pulses 85 ₇₅₁ of the GND level is applied to, in the address electrodes 72 ₁ to 72 _M, the address pulse 86 of the voltage Va is selectively applied to the address electrodes corresponding to cells to be lit, the cell to be lighted Is discharged.

[0099] Then, immediately, the sustain discharge pulses 87 ₇₅₁ to the X electrode 70 ₄ is applied, the sustain discharge for maintaining in a stable state wall charge to sustain discharge period is performed, displayed on the display line 75 ₇₅₁ by this Data writing is complete. Hereinafter, the display line 75 _{752-75 1000} also sequentially the same operation is performed, the writing of the display data for all the display lines 75 _{752-75 1000} block ₇₆₄ is performed.

It should be noted that 85₇₅₂~ 85₁₀₀₀Is the Y electrode 71
₇₅₂~ 71₁₀₀₀Address pulse sequentially applied to
₇₅₂~ 87₁₀₀₀Is the address pulse 85₇₅₂~ 85₁₀₀₀To
Then, the X electrode 70_FourThe sustain discharge pulse applied to
You. Next, in the sustain discharge period, the Y electrode 71₁~ 71
₁₀₀₀And X electrode 70₁~ 70 _FourAlternately to the GND level
Sustain discharge pulses 88 and 89 are applied to perform sustain discharge.
Then, the image display of one frame is performed.

According to the seventh embodiment, the erase discharge is performed in all the cells in all the display lines after writing in all the cells in all the display lines before writing the display data. , It is possible to achieve a uniform state of all cells on all display lines, avoid writing mistakes in the address / sustain discharge separation drive method, and perform good image display, and after writing display data, The wall charge can be maintained in a stable state until the sustain discharge period.

Here, in the seventh embodiment, the display lines 75 ₁ to 75 ₁₀₀₀ are connected to 250 consecutive display lines 75 ₁ to 75 _250, 75 ₂₅₁ to 75 _500, 75 _501.
By 75 _750, 75 ₇₅₁ to 75 _1000, and blocked into four blocks 76 ₁ to 76 _4, these blocks 76 ₁
To 76 ₄ X electrodes 70 ₁ to 70 ₄ which are commonly connected to a provided each, at the address period, sustain discharge for stabilizing the only wall charges the X electrodes of the block including the display line for writing display data A pulse is applied.

Therefore, during the first address period, sustain discharge pulses 87 _{1 to} 87 ₁ applied to the X electrode 70 ₁ are applied.
₂₅₀ display lines 75 ₁ to 75 ₂₅₀ of the block 76 ₁
Is applied to the cell only, not applied to the other blocks _{762, 763} and ₇₆₄ of the display line 75 _{251-75 1000} cells. Also, during the second address period, the X electrode 70 ₂
The sustain discharge pulses 87 _{25 1 to} 87 ₅₀₀ applied to the display lines 75 ₂₅₁ to 75 ₅₀₀ of the block 76 ₂ are applied only to the cells of the other blocks 76 ₁ , 76 ₃ and 76 _4.
Display line 75 _{1-75 25 0,} the 75 _{501-75 1000} cells not applied.

Also, during the third address period, the X electrode 70 ₃
The sustain discharge pulses 87 _{50 1 to} 87 ₇₅₀ applied to the cells are applied only to the cells of the display lines 75 ₅₀₁ to 75 ₇₅₀ of the block 76 ₃ and the other blocks 76 ₁ , 76 ₂ and 76 ₄ are applied.
Is not applied to the cells of the display lines 75 ₁ to 75 _{50 0} and 75 ₇₅₁ to 75 ₁₀₀₀ . Also, during the fourth address period, X
Sustain discharge pulse 87 _{75 1 to} 87 applied to the electrode 70 _4.
1000 display lines 75 _751-75 block ₇₆₄
It is applied to only ₁₀₀₀ cells and the other blocks 76 ₁ , 76
The ₂ and 76 ₃ of the display line 75 _{1-75 75 0} of the discharge cells not applied.

That is, in the seventh embodiment,
X electrode 70 during dressing period₁~ 70 _FourApplied to
Discharge pulse 87₁~ 87₁₀₀₀Has 250 display lines
Since it is applied only to the cell of
In comparison with the case of the sixth embodiment in which the
1/4 of the power consumption due to the sustain discharge pulse that should be applied to the pole
Can be

In the seventh embodiment, the display line is divided into four blocks, and the X electrodes commonly connected to each block are provided. However, the present invention is not limited to this. This can be generally applied to the case where the block is divided into arbitrary n blocks and the X electrodes commonly connected to each block are provided. In this case, the sustain discharge pulse to be applied to the X electrodes during the address period. The power consumption due to can be reduced to 1 / n of that in the sixth embodiment.

When performing multi-gradation display, for example, 16-gradation display, one frame is divided into four as shown in FIG.
The subframes SF1, SF2, SF3, SF4 are divided into subframes SF1, SF2, SF3, SF4.
In the above, the above operation may be performed. In this case, since the number of sustain discharge pulses supplied to the X electrodes during the address period is larger than that in the case of single gradation, the effect of reducing the power consumption is larger than in the case of single gradation.

Eighth Embodiment ... FIGS. 17 to 31 FIGS. 17 to 30 are views showing an eighth embodiment of the present invention. This embodiment is an example of application to a three-electrode / surface-discharge AC PDP (that is, the configuration of FIG. 47) in which the sustain discharge electrodes are in the XY-Y-X arrangement, and the driving method is full lighting. , Whole surface erasing, and further application to a drive sequence in which a write address is applied and an address period and a sustain discharge period are separated.

FIG. 17 is a waveform diagram of this embodiment, showing one drive cycle in the "write address system". One frame is divided into a full-face write / erase period, an address period, and a sustain discharge period. Considering the case where there are discharge cells that are lit and discharge cells that are not lit in the previous frame, the entire address erase period is made uniform in the state of all discharge cells, that is, all discharge cells have wall charges. A period to create a non-remaining state, or
Even if the wall charges remain in all the discharge cells, this is a period for making the remaining state uniform over all the discharge cells.

Here, in the full-program write / erase period,
First, the Y electrodes Y _{1 to} Y _N are set to the GND level, the write pulse 90 having the voltage Vw is applied to the X electrodes, and all the cells are discharged. Subsequently, the potential of the Y electrode Y ₁ to Y _N are returned to the voltage Vs, is applied sustain pulses 91 to the X electrode, after the sustain discharge is performed, the Y electrodes Y ₁ ~
A narrow erase pulse 92 is applied to Y _N to cause erase discharge. In this way, the full-face write / erase is completed.

Next, in the address period, the display line
The display data is written in sequence for each
It is done like this. First, the Y electrode Y₁, Y_Two,…
…, Y _NGND level address pulse 93₁, 93
_Two, ……, 93_NAre sequentially applied and the address
Electrode A₁~ A_MInside, it is arranged in the cell that should be lit
Address pulse 94 of voltage Va is selectively applied to the address electrode
Is applied to discharge the cells to be lit. This
By this, writing of display data to each display line
Ends. In the sustain discharge period, the Y electrode Y₁~
Y_NAnd sustain discharge pulses 95 and 96 are alternately applied to the X electrode.
It is applied and sustain discharge is performed, and one frame image is displayed.
Done.

In this embodiment, the voltage applied to the Y electrodes Y _{1 to} Y _N in the address period is set to the address pulse 9
3 _{1 to} 93 _N potential (GND), this GND and voltage V
The voltage is switched to an almost intermediate potential Vy of s (preferably Vy = Va). That is, the address pulse of the GND potential is applied to the Y electrode of the selected line, while the voltage Vy is applied to the Y electrodes of the other non-selected lines.

FIG. 18 is a diagram showing a drive model of the drive method (write address method) of FIG. In this figure, (a) shows a state after full writing and full erasing, and the states of all cells are made uniform. In this state, the address electrode is at the GND potential, and the two Y electrodes (Y ₁ , Y ₂ ) adjacent to the X electrode are at the Vs potential. (B)
Indicates a state in which an address pulse 93 ₁ (GND) is applied to the Y ₁ electrode to cause address discharge. The address electrode is at the voltage Va, and the Y ₁ electrode is at the GND potential. In this state, positive wall charges (charge amount is V _WY1 for convenience) are formed on the Y ₁ electrode by the address discharge. In (3), the address pulse 93 ₂ (GND) is applied to the adjacent Y electrodes (Y ₂ ). In this state, the applied voltage of the Y ₁ electrode is Vy (= Va), and the Y ₁ electrode is Since the positive wall charges V _WY1 are accumulated on the side, the effective voltage applied to the discharge space between the Y ₁ electrode and the Y ₂ electrode is in the state where no write discharge occurs between the Y ₂ electrode and the address electrode. It is given by Va + V _WY1 (in this case,
The wall charge on the Y ₂ electrode is small and will be ignored). In general, since Va + V _WY1 <Vf (Vf: discharge start voltage), two adjacent Y electrodes (Y ₁ , Y ₂ )
It is possible to avoid abnormal discharge in the discharge space between
The wall charge V _WY1 on the Y ₁ electrode side can be retained as it is.

FIG. 19 is another waveform diagram of this embodiment, showing one drive cycle in the "erase address system". As in the case of FIG. 17, one frame is divided into a full write / erase period, an address period and a sustain discharge period. In the full-face write period (corresponding to the full-face write / erase period in FIG. 17), first, the Y electrodes Y _{1 to} Y _N are set to the GND level, and the write pulse 97 having the voltage Vw is applied to the X electrode.
Is applied, and discharge is performed in all cells on all display lines.
Subsequently, the potentials of the Y electrodes Y _{1 to} Y _N are returned to the voltage Vs, and the same level (GN) as the sustain discharge pulse 98 is applied to the X electrodes.
(D level) is applied, and sustain discharge is performed in all cells.

Next, in the address period, writing is sequentially performed for each display line, which is performed as follows. First, Y electrodes Y _1, Y _2, ......, address pulse 99 _first sequentially GND level to Y _N, 99 _2, ...
, 99 _N is applied and address electrodes A _{1 to} A
_{During M} , the address pulse 100 of the voltage Va is selectively applied to the address electrodes corresponding to the cells that do not perform the sustain discharge, that is, the cells that do not light up, and the erase discharge of the cells that do not light up is performed. This completes the writing of each display line. In the sustain discharge period, the Y electrode Y
Sustaining discharge pulses 98, ₁ are alternately applied to _{1 to} Y _N and the X electrode.
01 is applied, sustaining discharge is performed, and image display of one frame is performed.

FIG. 20 is a diagram showing a drive model of the drive method (erase address system) of FIG. In this figure,
(A) is a state after wall charges are formed in all cells by whole-area writing and then sustain discharge is performed. The address electrodes are at the GND potential, and the two Y electrodes (Y ₁ , Y ₂ ) adjacent to the X electrodes are at the Vs potential. (B)
Shows a state in which an address pulse 99 ₁ (GND) is applied to the Y ₁ electrode to cause erase discharge (address discharge). The address electrode is at the voltage Va, and the Y ₂ electrode is also at the Va potential. Positive wall charges are accumulated on the insulating layer near the Y ₁ electrode by discharge. Since positive wall charges have already been accumulated on the X electrode side, this address discharge causes the wall charges on both the X electrode and the Y ₁ electrode to become positive. Absent.
(C) address pulses to the Y ₂ electrode adjacent 99 ₂ (G
ND) is applied. In this state, the voltage Vy (= Va) is applied to the Y ₁ electrode, GND is applied to the Y ₂ electrode. Y ₁ is the electrode side positive wall charges (for convenience V
_WY1 ) is accumulated, but when address discharge is not _generated between the Y ₂ electrode and the address electrode, two adjacent Y
Since the effective voltage (Va + V _WY1 ) applied to the discharge space between the electrodes (Y ₁ , Y ₂ ) does not exceed the discharge start voltage Vf,
As with the write address method, Y ₁
The wall charges on the electrode side can be retained as they are.

FIG. 21 is a block diagram of the PDP of the eighth embodiment. In this figure, 102 is a control unit, and the control unit 102 is a display data control unit 1 including a frame memory F.
02a, a panel drive control unit 102d including a scan driver control unit 102b and a common driver control unit 102c.
Is provided. 103 is an address driver, 104 is a Y scan driver, 105 is a Y driver, 106 is an X driver, 107 is a display panel, and the address driver 10
3, the display data A-DATA and transfer clock A-CLOCK from the control circuit 102, and further, is one that confers a sequentially selected voltage Va to the address electrodes A ₁ to A _M according to the latch clock A-LATCH.

Further, the Y scan driver 104, the Y driver 105 and the X driver 106 are provided with scan data Y-DATA and Y clock Y-CL from the control circuit 102.
OCK, first Y strobe Y-STB1, second Y strobe Y-STB2, Y up drive signal Y-UD, Y
Down drive signal Y-DD, X Up drive signal X
-UD and X down drive signal X-DD according to the Y electrodes Y ₁ to Y _N and X electrodes a predetermined voltage (Vs, Va, V
w).

FIG. 22 shows the Y scan driver 104 and Y
3 is a configuration diagram of a driver 105. FIG. Y scan driver 1
04, Y electrode selection for each electrode circuit M ₁ ~M _n and the electrode selection circuit M ₁ ~M signals _{for n} sequentially specify Q ₁
, Q _n , and the electrode selection circuit (typically M ₁ ) is composed of three AND gates G _{1 to} G ₃ and one inverter gate G ₄ during the address period. The output of the circuit complementarily controls ON / OFF of the two MOS transistors T ₁ and T ₂ (a relationship in which when one is on, the other is off).

T₁Is on, a predetermined voltage Vy (blocking
Stop diode D_ThreeOutput Va) given via₁
And T_TwoIs on, the ground potential (GN
Output D)₁Show up in. That is, the Y scan driver
In the address period, the aver 104 is provided with each Y
Turn on / off the pulse (address pulse) for selecting the pole
It is turned off (on = GND, off = Vf). However
And output O₁Is the diode D₁And D_TwoThrough Y
Two MOS transistors T of driver 105 _Three, T_Four
Connected to these transistors T_Three, T
_FourIs applied to all Y electrodes according to the signals Y-UD and T-DD.
Turn on / off the commonly applied pulse (sustain discharge pulse).
(ON = GND, OFF = Vs).

FIG. 23 is an operation waveform diagram of FIG. In this figure, when the signal Y-UD is at the H level, the voltage Vs is applied to all the Y electrodes because the transistor T ₃ of the Y driver 105 is turned on, and the signal Y-DD is at the H level.
At the level, similarly, the transistor T ₄ of the Y driver 105 is turned on, so that GND is given to all the Y electrodes.

On the other hand, in the address period, the Y driver 10
The two transistors T ₃ and T _{4 of 5} are both turned off,
Instead, the electrode selection circuit M of the Y scan driver 104 is used.
Two transistors T ₁ and T ₂ provided in _{1 to} M _n are turned on / off at a predetermined timing. Now, focusing on the electrode selection circuit M ₁ corresponding to the Y ₁ electrode, this selection circuit M 1
_The transistor T ₂ provided in ₁ is provided with a signal Q ₁ and Y-S generated by the shift register R in synchronization with Y-CLOCK.
Logical product of TB1 and Y-STB 2 is only ON period becomes "1", the level is applied to the Y ₁ electrode output O ₁ becomes the GND level.

[0123] In addition, the transistor T ₁ of the same selection circuit M ₁
Is on only during a period in which the logical product of the signal Q ₁ and Y-STB1 is “0” and during a period in which Y-STB2 is at H level, and the voltage Vy is applied to the Y ₁ electrode. That is, as shown in the simplified view of FIG. 22 in FIG. 24, the selection circuit M _i (i is 1, 2, ..., N) with the two transistors T ₃ and T ₄ of the Y driver 105 kept off. by turning on / off the two transistors T _1, T _2, can be secured address discharge pulse required current path formation (see white arrow), also in the reverse, the second selection circuit M _i
By turning on / off the two transistors T ₃ and T ₄ of the Y driver 105 while keeping the transistors T ₁ and T ₂ off, the current path necessary for forming the sustain discharge pulse (see black arrow). Can be secured.

[0124] As described above, in the address period of the embodiment, Y ₁ to Y electrodes up to Y _N it is possible to provide successively a GND level of the address pulses 106 ₁ - 106 _N, other than the address pulses In the period, that is, in the period of the non-selected line, the voltage Vy (= Va) corresponding to an approximately intermediate level between the GND level and the voltage Vs can be given, so that the effective voltage including the positive wall charge accumulated by the write discharge is changed. It can be reduced (compared to the case where the voltage Vs is applied), and adjacent Y electrodes are selected (G
It is possible to avoid abnormal discharge between the adjacent Y electrodes when the ND level). As a result, the wall charges can be stably held until the sustain discharge period.

In the eighth embodiment, the voltage range handled by the Y scan driver 104 is GND to Vy, which is the voltage range of the Y driver 105 (GND to Vy).
Since it is approximately 1/2 of s), the withstand voltage of the Y scan driver 104, which is increased in scale in proportion to the number of Y electrodes, can be lowered, and integration (LSI integration) is facilitated, which is preferable.

Further, the X driver 106 in FIG.
A detailed circuit diagram of the above is shown in FIG. This X driver 106
Uses transistors T ₅ and T ₆ capable of high power switching so that a relatively high voltage (Vw) address pulse and sustain discharge pulse (Vs) can be supplied. Basically, the transistor T ₅ to which the updrive signal X-UD for setting the voltage of the X electrode to Vw or Vs is input, and the voltage of the X electrode to the ground potential (0V).
The transistor T ₆ to which the down drive signal X-DD for inputting is input is paired. In FIG. 25, the transistors T ₅ and T ₆ are composed of a pair of complementary MOS transistors. For example, the updrive signal X-UD
Is supplied from a P-channel MOS, and the side supplied with the downdrive signal X-DD is an N-channel MOS.
But vice versa. Where, for example,
When the write pulse of the voltage Vw is applied to the X electrode, the power supply voltage of the transistor T ₅ on the updrive signal side is set to
Vw at the timing of the updrive signal X-UD
Switch to.

Further, FIG. 26 shows a detailed circuit block diagram of the address driver 103 in FIG. Here, the address driver 103 uses the display data A-DATA and the transfer clock A-CLO from the control circuit 402.
N-bit shift register 407 that transfers N-bit display data according to CK, and latch clock A-LA
And N-bit latch unit 408 sequentially selects the address electrodes A ₁ to A _M according to TCH, a high pressure section 409 supplies a high voltage Va to the address electrode selected in accordance with the output signal from the N-bit latch 408 Is equipped with. Further, the high-voltage unit 409 has N bits, and these N
Each of the pieces of the high pressure section 409 includes a logic circuit 409a consisting of AND gates and the like, and a pair of transistors T _7, T _8. In this case, only when the data latched by the N-bit latch unit 408 is "1" and the address strobe A-STB is turned on, the address pulse (output 1 to output 1) of the voltage V _a is applied to the corresponding address electrode. N)
Is output.

FIG. 27 is another configuration diagram of the Y scan driver and the Y driver. The difference from FIG. 22 is that the Y scan driver is in a floating state. That is,
The two transistors T ₁ ′ and T ₂ ′ of the Y scan driver 104 ′ have a voltage Vy (= Va) applied through the blocking diode D ₃ and the two transistors T ₃ ′ and T of the Y driver 105 ′. The output O _i of the selection circuit M _i , which is connected to the voltage (Vs or GND) extracted from ₄ ′, is connected to the transistors T ₁ ′, T ₂ ′, T.
_By selectively turning on / off 3'and T ₄ ', GN
It is set to one potential of D, Vs or Vy. In addition,
108 is a photocoupler for isolation, G _11,
G ₁₂ is an AND gate, G _{13 and} G ₁₄ are inverter gates,
G ₁₅ is an OR gate.

FIG. 28 is an operation waveform diagram of FIG. In this figure, signal when Y-UD is at H level, given the voltage Vs to all of the Y electrodes in order to turn on 'the transistor T ₃ of the' Y driver 105, also the signal Y-DD
Is at the H level, the transistor T ₄ ′ of the Y driver 105 ′ is also turned on, so that all the Y electrodes are GND.
Is given.

On the other hand, in the address period, the Y driver 10
5 'transistor T ₄ the' continues the on-state to fix the floating potential of the Y scan driver 104 'to the ground level. In this state, when the transistor T ₂ ′ provided in the selection circuit M ₁ ′ is turned on, the output O ₁ becomes the GND level, the level is given to the Y ₁ electrode, and the transistor T ₁ ′ is turned on. Then, the voltage Vy is applied to the Y ₁ electrode through the transistor T ₁ ′.

That is, as shown in the simplified diagram of FIG. 27 in FIG. 29, the two transistors T of the selection circuit M _i ′ are kept with the transistor T ₄ ′ of the Y driver 105 ′ turned on.
By turning on / off ₁ ′ and T ₂ ′, a current path necessary for forming an address discharge pulse (see a white arrow) can be secured, and the transistor T ₂ ′ of the selection circuit M _i ′ can be secured.
By turning on / off the two transistors T ₃ ′ and T ₄ ′ of the Y driver 105 ′ while keeping ON, the current path (see the black arrow) necessary for forming the sustain discharge pulse can be secured.

[0132] Incidentally, FIG. 30 is a modified example of FIG. 2 2,
The switch 109 switches between the two voltages Va and Vs. Va is selected during the address period, but Vs is selected outside the address period. FIG.
It is a cell sectional view of a PDP which is preferably applied to each of the above embodiments. In this PDP cell, by devising the structure in the vicinity of the address electrode, wall charges can be positively accumulated on the insulating layer on the address electrode side, so that the voltage applied between the address electrode and the Y electrode during address discharge. It is intended to increase the voltage margin and reduce the voltage applied between the address electrode and the Y electrode during selective discharge.

That is, in this example, as shown in FIG. 31, in order to isolate the address electrode 310 and the discharge space 311, the dielectric layer 313 is provided between the walls 312a and 312b.
And the phosphors 314a and 314b are completely filled. As a material for the phosphors 314a and 314b, for example, a ceramic such as (green) Zn ₂ SiO ₄ : Mn (red) Y ₂ O ₃ : Eu (blue) BaMgAl ₁₄ 4O ₂₃ : Eu ²⁺ is used, and By making the film thickness sufficient to block the address electrode from the discharge space, charges can be accumulated. Further, in such a state, it is possible to accumulate charges even if a phosphor is placed at the position of the dielectric layer 313.

When line-sequential driving is performed on the PDP having such a structure, first, a write discharge is generated between the X electrode and the selected Y electrode to promote the discharge between the address electrode and the X electrode to generate space charge. Let it form. The polarities of this space charge are negative on the X electrode side and positive on the address electrode and Y electrode side, and electrons (negative charge) accumulate on the X electrode side and ions (positive charge) accumulate on the address electrode and Y electrode side, respectively. To be done. Next, when the sustain discharge is generated in all cells by the sustain discharge pulse, the wall charges whose polarities are inverted are accumulated, and the erase pulse applied to the Y electrode thereafter causes the erase discharge in all cells. After the erasing discharge, the wall charges are reduced, so that even if the sustain discharge pulse is applied, a sufficient effective voltage is not applied, so that the sustain discharge does not occur. Here, the effective voltage of the discharge when the write discharge is generated between the selective Y electrode and the address electrode is
Since it is given by the sum of the wall charges accumulated on the address electrode side and the applied voltage (address voltage) of the address electrode,
It is possible to reliably generate the address discharge even with a low address voltage.

32. Ninth Embodiment FIG . 32 is a diagram showing drive waveforms according to the ninth embodiment of the present invention. In the driving methods in the above-described first to eighth embodiments, the wall charges are accumulated on the insulating layer on the address electrode side by the first-stage all-cell write discharge. This wall charge effectively works in the form of being added to the voltage applied to the address electrode in the selective write discharge when selecting a cell, and thus it was possible to drive at a low address voltage.

However, in this all-cell write discharge, when excessive wall charges are formed on the insulating layer on the address electrode side, a large-scale discharge occurs in the selective write discharge, and writing is performed up to non-selected cells. There is a possibility that a large amount of wall charges generated by selective write discharge will start discharge again with the voltage of the wall charges themselves immediately after the address pulse is applied, and it will become self-disappearing (self-erasing) discharge. is there.

In this all-cell write discharge, the formation of excessive wall charges on the insulating layer on the address electrode side can be considered in the following cases. All-cell write pulse (X electrode) applied when the previous frame was in the lighting state
In addition, the wall charges remaining in the previous frame are added and contribute to the discharge. That is, the effective voltage applied to the discharge space is the sum of the applied voltage and the wall charges, and has a large value. Therefore, the discharge that occurs is naturally large-scale. In this case, even if the all-cell erase discharge is performed after the all-cell write discharge, the above large-scale influence may not be negligible. Further, when the insulating layer on the address electrode side is formed of a phosphor, the phosphor is exposed to positive charges, that is, ions. As described above, the phosphor is weak against the collision of ions, the composition is changed, and it may not be possible to obtain satisfactory emission characteristics.

As a countermeasure against this, as shown in FIG. 32, all cells are subjected to write discharge after erasing discharge for extinguishing or reducing the wall charges of the cells in the lighting state in the previous frame. It is effective to do. By doing this, it is possible to carry out a constant scale all-cell write discharge regardless of the lighting state in the previous frame, and the mis-address (writing to the adjacent cell, self-erasing) or the fluorescent substance caused by the large-scale discharge is generated. Can be prevented from deteriorating.

More specifically, in FIG. 32, immediately before the all-cell write pulse applied from the X electrode,
An erase pulse (narrow erase pulse) for performing erase discharge is applied to all cells of the selected display line. By this erase pulse, the wall charges of the cells that were lit in the previous frame are extinguished or reduced, so that large-scale all-cell write discharge does not occur.

10th Embodiment FIG . 33 is a diagram showing drive waveforms according to the 10th embodiment of the present invention. In FIG. 33, immediately before the all-cell write pulse applied from the X electrode, an erase pulse (narrow erase pulse) for performing erase discharge to all cells of all display lines is applied. Also in this case, since the erase pulse is inserted immediately before the all-cell write discharge, a large-scale all-cell write discharge does not occur, as in the ninth embodiment.

According to the above ninth and tenth embodiments,
By inserting the erase pulse immediately before writing all cells, a large-scale all-cell write discharge is prevented, and a great effect is provided in avoiding a misaddress and extending the life of the phosphor. Eleventh Embodiment FIG. 34 and FIG. 35 FIG. 34 is a diagram showing drive waveforms of the eleventh embodiment of the present invention. Here, during the all-cell write discharge that is performed first,
The voltage Va of the address pulse can be further reduced by accumulating the charge that works favorably at the next selective write discharge in the insulating layer (for example, phosphor) that covers the address electrode.

The new means used here is to accumulate the charge that works favorably during the address write discharge even during the sustain discharge that is performed after the all-cell write discharge, which enables further low voltage driving. Becomes By lowering the voltage of the address pulse as described above, multi-gradation display and low power consumption are realized in accordance with the integration of the address side driver and full colorization.

More specifically, according to FIG. 34, immediately after the all-cell write pulse applied from the X electrode,
The purpose is to make the sustain discharge pulse applied to all the cells of the selected display line narrow. FIG. 35 shows a drive model in the case where the narrow sustain pulse is generated. In the first-stage all-cell write discharge, positive charges are accumulated on the insulating layer on the address electrode side. Here, the accumulated position is accumulated on the address insulating layer near the X electrode. Since selective address discharge by the address electrode occurs between the address electrode and the Y electrode, it is preferable to accumulate it on the address insulating layer near the Y electrode. Therefore, in the next second step, when a sustain pulse is applied by applying a narrow pulse, the X electrode is at the ground potential (0 V).
And discharge occurs. Immediately after that, that is, since the space charges generated by the discharge are all accumulated as wall charges on the X electrode and Y electrode sides and before the space charges disappear, the pulse is ended, so that the X electrodes and the Y electrodes are discharged. The electrode is Vs
Potential and only the address electrode is at ground potential. In that case, among the charges remaining in the space, positive charges are accumulated on the insulating layer on the address electrode side having the lowest potential, particularly on the address electrode side close to the Y electrode. Then, as a third step, erase discharge between the X electrode and the Y electrode is performed. Finally, selective write discharge is performed. At this time, since positive wall charges on the address electrode on the Y electrode side work effectively, the voltage Va of the address pulse applied from the outside is discharged at a relatively low value. It is possible.

12th Embodiment FIG. 36 FIG. 36 is a diagram showing drive waveforms according to the 12th embodiment of the present invention. Here, immediately after the all-cell write pulse applied from the X electrode, the narrow sustain discharge pulse is applied to all cells on all display lines. In this case also, the same driving state as that of the eleventh embodiment can be obtained by using the sustain discharge pulse after writing all cells as the narrow pulse.

According to the eleventh and twelfth embodiments described above, by making the sustain discharge pulse a narrow pulse, it is possible to accumulate the wall charge so that it works more effectively during the selective write discharge. 13th Embodiment FIG. 37 and FIG. 38 FIGS. 37 and 38 are diagrams showing a drive model and a drive waveform, respectively, of the 13th embodiment of the present invention. Until now, the configuration has been such that the write pulse is applied to the X electrode. However, as shown in FIGS. 37 and 38,
Even when the write pulse is applied to the Y electrode,
The accumulation of wall charges on the address electrode side can be expected as well.

Here, an example in which the wall charge storage operation of the present invention is applied to the brightness adjustment of an AC type PDP will be described with reference to the accompanying drawings. FIG. 52 is a timing diagram for explaining an example in which the wall charge accumulation operation of the present invention is applied to the brightness adjustment of an AC PDP. The present embodiment shows a driving mode in the case where the maximum sustain discharge frequency is 30.6 kHz (frame frequency is 60 Hz) in 256 gradation display.

In the figure, SF1 to SF8 indicate sub-frames forming one frame forming one screen.
The sub-frame SF1 is assumed to be the sub-frame having the maximum luminance weight, and the number of sustain discharge cycles (N _SF1 ) is 2.
It shall be set to 56 times. In the case of displaying at the maximum brightness, the number of cycles of the sub-frame SF1 is 256, and the number of cycles (N _SF2 ) of the next sub-frame (that is, the sub-frame having the second largest luminance weight) SF2 is ½ thereof. 128 times. In the same manner as above, the number of sustain discharge cycles N _{SF1 to} N _SF8 of each of the subframes _{SF1 to SF8} is determined in this procedure, and the result is as follows.

N _SF1 : N _SF2 : N _SF3 : N _SF4 : N _SF5 : N _SF6 : N _SF7 : N _SF8 = 256: 128: 64: 32: 16: 8: 4: 2: In the state thus determined For example, when it is desired to reduce the luminance by 10%, the number of sustain discharge cycles N _SF1 of the subframe _{SF1 is set} to 230 times (≈256 × 0.9).
The number of sustain discharge cycles N _{SF1 to} N _SF8 of each of the sub frames _{SF1 to SF8} is determined according to the procedure of halving the number of subsequent sub frames, and the result is as follows.

N _SF1 : N _SF2 : N _SF3 : N _SF4 : N _SF5 : N _SF6 : N _SF7 : N _SF8 = 230: 115: 57: 28: 14: 7: 3: 1 In this way, each sub-frame SF1 In SF8, the luminance is adjusted by increasing / decreasing the number of sustain discharge cycles (the number of sustain light emissions) at the same ratio (in this case, decreasing by 0.9 times). Therefore, when gradation display is performed in driving the PDP, multi-step brightness adjustment can be performed by digital control, and a display device closer to a CRT can be realized.

FIG. 53 shows a circuit configuration for determining the number of sustain discharge cycles in each subframe.
In the figure, 111 is an adjusting means (volume) for freely setting a brightness value from the outside, and 112 is a volume 1.
An A / D converter for converting the analog voltage signal set by 11 into an 8-bit digital signal, and 113 is an input A (A / D converter 112) in response to a selection signal SEL (output Y of a decoder 119 described later). Output) or input B
A selector for selecting any one of (the output Y of the divider 115 described later) and a clock input CK (the comparator 1 described later)
17 shows a latch that holds the output Y of the selector 113 in response to the output Y) of the selector 113. The latch is formed of a D-type flip-flop and holds a value that determines the number of sustain discharge cycles of the next subframe. Reference numeral 115 denotes a divider that divides the input A (output Q of the latch 114) into ½, and the divider is configured by using, for example, a shift register, and its output Y (= A / 2) is input to the selector 113. Supplied as B. In the divider 115, the input A is 1/2
If it is not divisible by, it will be “truncated”.

Reference numeral 116 denotes a 256-adic 8-bit counter, which has a clear input CLR (comparator 1
It is reset in response to the output Y of 17 and counts the number of sustain discharge cycles in response to the clock input CK (clock signal CKS from the drive waveform generation circuit). Reference numeral 117 denotes an input A (output Q of the latch 114) and an input B (counter 1).
16 outputs Q) are compared, and a comparator for activating its output Y when both match, 118 indicates an octal 3-bit counter, which responds to a clear input CLR (vertical synchronization signal VSYN) Then, the sub-frame is designated by counting the clock input CK (output Y of the comparator 117) by being activated by the enable signal ENA (output Y of the decoder 119). Reference numeral 119 denotes a NAND (nand) logic decoder responsive to the 3-bit outputs QA, QB and QC of the counter 118, 120 denotes an OR (or) logic decoder responsive to the 8-bit output of the selector 113, and 1
Reference numeral 21 denotes a latch that holds the output Y of the decoder 120 in response to the clock input CK (output Y of the comparator 117), and the output Q of the latch is supplied to the high voltage circuit as the enable signal D-ENA of the high voltage drive waveform. To be done.

Next, the operation of the circuit shown in FIG. 53 will be described. First, the A / D converter 1 is controlled by the volume 111.
The potential of the analog signal input to 12 is determined. Since the output from the A / D converter 112 is 8 bits, "255" is output as a digital value when the input signal level to the A / D converter 112 is the maximum. This "255" is a value that determines the number of sustain discharge cycles of the sub-frame SF1 having the maximum brightness, and each of the 256 count values counted from 0 to 255 in the counter 116 is the number of sustain discharge cycles.

At the stage of the sub-frame SF1, the counter 8 designating the sub-frame is immediately after being cleared by the vertical synchronizing signal VSYN, so its count value (QA
-QC) becomes "0". Therefore, MSF0 to MSF2 are all "0", and the output Y of the decoder 119 is "1" in NAND logic. As a result, the selector 113 selects the input B in response to the "1" level of the output Y (selection signal SEL) of the decoder 119. Prior to this, "0" was output from the decoder 119 at the time of subframe SF8 (final subframe) of the previous frame, and the input A (output of the A / D converter 2) was selected by the selector 113. It is temporarily stored in the latch 114.

The output Q of the latch 114 (currently "255") is input to the respective inputs A and B of the comparator 117 together with the output Q of the counter 116 (count value of the number of sustain discharge cycles) for comparison. . 2 sustain discharge cycles
When it is repeated 56 times, the count value of the counter 116 becomes “255”, the input A = B in the comparator 117, and the output Y thereof becomes active.

The comparator 117 in the active state
The output Y of increments the value of the counter 118. As a result, the subframe SF1 ends, and the process moves to the next subframe SF2. The latch 114 holds a new value, but the decoder 1
The output Y of 19 has changed to "1", and the selector 8 selects the input B. A value obtained by dividing the output Q of the latch 114 by 1/2 by the divider 115 is input to its input B. Therefore, at this point, the latch 114
The value held in is 1/2 of 255, which is “127”.

Similarly, when the sustain discharge of subframe SF2 is completed 128 times, the next subframe SF3 starts. When the sub-frames SF1 to SF8 are completed, the operation is suspended until the next frame starts due to the input of the vertical synchronization signal VSYN. When adjusting the brightness, the volume 111 is adjusted to adjust the A / D converter 112.
It suffices to change the analog voltage value input to.

In the brightness adjusting method of the present invention, when the brightness is lowered, there are subframes in which the number of sustain discharge cycles becomes zero. At this time, the number becomes 0 in order from the subframe having the smallest number of sustain discharge cycles. When the number of sustain discharge cycles is 0, the address period of the subframe is completely wasted. This is because even if a cell is selected by the address discharge, the sustain discharge is not accompanied, so that there is no light emission display. Further, in the above-mentioned conventional driving method by the addressing method, after erasing all cells, erasing discharge is generated in cells unnecessary for light emission display and the discharge is stopped. Therefore, even in a cell that does not perform light emission display in the address period, slight light emission (so-called “background light emission”) occurs, which causes a reduction in contrast. When the set brightness is large, the contrast does not matter so much because the difference between the maximum brightness and the background brightness is large, but when the brightness is set to low brightness, the background brightness does not change and the contrast is relatively low. As a result, the display quality is deteriorated and the display quality is deteriorated.

Therefore, in the application example of FIGS. 52 and 53,
In a subframe in which the number of sustain discharge cycles is 0, an operation (rewriting of display data) that should be performed in the address period of the subframe is not performed. The number of sustain discharge cycles of the next subframe is known during the period of the immediately preceding subframe. That is, when the output value Y of the selector 3 becomes 0 in the Nth subframe, the number of sustain discharge cycles in the next (N + 1) th subframe is one. Further, since the number of sustain discharge cycles of the next (N + 2) th subframe is naturally 0, it means that no address is required in the (N + 2) th subframe and thereafter.

The decoder 120 functions to perform this control. That is, since the logic of the decoder 120 is an OR of 8-bit inputs (A0 to A7), when the value (the output Y of the selector 113) that determines the number of sustain discharge cycles of the next subframe becomes 0, the next At the time of shifting to the subframe, the value is held in the latch 121. The output Q of the latch 121 is the enable signal DE of the high voltage drive waveform.
It becomes NA, which interrupts the application of the high-voltage drive waveform. In the subsequent subframes, the output Q of the latch 114, the output Y of the divider 5, the output Y of the selector 113, and the output Y of the decoder 120 are all 0, so the high-voltage drive waveform is enabled. Then, in the next frame, the enable is released in the period of the subframe SF1.

Thus, by interrupting the application of the high-voltage pulse in the sub-frame in which the sustain discharge is not performed,
It is possible to eliminate wasteful power consumption and drive with low power consumption. In addition, it is possible to prevent reduction in contrast due to useless power consumption, and it is possible to perform good display with high contrast even at low brightness. Further, in order to clarify the characteristics of the brightness adjusting method for the AC PDP according to the present invention, a general (conventional) brightness adjusting method for the AC PDP will be briefly described with reference to FIGS. 54 to 61 below. I will.

FIG. 54 shows a timing chart illustrating a driving method of a two-electrode PDP when general brightness adjustment is not performed (monochrome display). In the figure, W indicates a rewriting driving cycle, and in this cycle, writing discharge may be performed. Further, S indicates a drive cycle of only sustain discharge, and in this cycle, only the cells written in the W cycle are lit. s indicates a drive cycle of only the sustain discharge of the previous frame, and in this cycle, only the cells written in the W cycle of the previous frame are lit.

One cycle of driving is divided into address discharge, sustain discharge and erase discharge, which are performed within one frame. Here, in order to obtain the maximum brightness, erase discharge is not performed, and only new information is rewritten in the write cycle of the next frame. When it is desired to reduce the brightness with respect to the maximum value, there are the following two methods. One is a method of stopping the sustain discharge by performing the erase discharge by inserting the erase pulse after performing the sustain discharge of a certain cycle, and the other is a method of periodically thinning the sustain discharge.

FIG. 55 shows a timing chart illustrating the former method (method of inserting an erase pulse), and FIG. 56 shows a drive waveform corresponding thereto. In FIG. 55, the drive cycle W for rewriting and the drive cycle S for only sustain discharge are the same as in the case of FIG. Further, E represents a drive cycle in which erase discharge is performed by an erase pulse, and e represents a drive cycle in which only sustain discharge is performed. In this cycle e,
It does not light up because it was erased before that (lights off). In FIG. 56, indicates a write pulse applied to the Y electrode, and by this, write is performed to all cells for one line. And indicate the selective erase pulse applied to the Y electrode and the A electrode, respectively.
Only the cells selected by the pulse of are erased. Further, the pulses of are applied in the W cycle. Is E
The erase pulse applied to the cycle is shown.

In this method, since the sustain discharge period until the time of inserting the erase pulse after writing is the light emitting period, it is possible to control the luminance depending on the cycle in which the erase pulse is inserted after writing. Become. FIG. 57 shows a timing chart illustrating the latter method (method of thinning out the sustain discharge), and FIG. 58 shows a drive waveform corresponding thereto.

In FIG. 57, the W cycle and S cycle are the same as those in FIGS. 54 and 55. Also,
In the driving cycle in which the sustain discharge pulse is thinned out, only the rewriting is performed when it overlaps with the W cycle. Fig. 58
In regard to the pulses of, the same as in the case of FIG. Also, indicates a sustain discharge pulse, which is
It is not applied in the driving cycle in which the sustain discharge pulse in FIG. 57 is thinned out.

According to this method, when the thinning cycle is 8 cycles, the brightness can be adjusted in 8 steps. Both of the above-mentioned two methods are well-known methods that are often used as the brightness adjustment method of the AC PDP. Next, the brightness adjustment when performing gradation display will be described.

FIG. 59 shows general gradations for brightness adjustment (4 to 4).
A timing diagram illustrating a driving method of the PDP when displaying 16 gradations is shown. In the figure, the W cycle and the S cycle are the same as in the case of FIG. In this method, selection (address) of two lines in one drive cycle
Therefore, it is necessary to apply the selective erase pulse twice. Therefore, there is not enough time to insert the erase pulse, and in the end, the brightness adjustment is often performed by the method of thinning out the sustain discharge pulse.

Here, the period for thinning out the sustain discharge pulse is
In order to maintain the gradation ratio, the luminance weight is the minimum (LSB)
Must be a divisor of the number of subframe cycles. For example, in the case of 16-gradation display, if the driving cycle (corresponding to the cycle of the horizontal synchronizing signal) in one frame is 480 cycles, the ratio of each sub-frame becomes 1: 2: 4: 8, and 32 cycles each. It becomes 64 cycles, 128 cycles and 256 cycles. In this case, the number of cycles of the LSB subframe is 32, so 32
It is possible to adjust the brightness in stages.

When performing full-color display, 64 for each color
Since ~ 256 gradations are required, the conventional multiple address method as shown in FIG. 59 cannot be applied. In view of this, the applicant of the present application has previously proposed a panel driving method in which an address period and a sustain discharge (light emission) period are separated to control gray scale display (see Japanese Patent Laid-Open No. 4-195188).

FIG. 60 shows a timing chart exemplifying the method, and FIG. 61 shows the corresponding drive waveform. Referring to FIG. 60, each subframe SF1 to S
F4 is completely temporally separated on the entire screen, and in each subframe, an address period for rewriting the display data and a sustain light emission (discharge) period for performing light emission display based on the rewritten display data are provided. Separated. Note that N
_{SF1 to} N _SF4 indicate the number of sustain discharge cycles in each of the subframes _{SF1 to SF4} , and in the illustrated example, N _SF1 :
N _SF2 : N _SF3 : N _SF4 = 1: 2: 4: 8.

Next, referring to FIG. 61, in the driving waveform shown in the figure, all cells are first written, and then line-sequential scanning is performed line by line to selectively erase cells which are not to emit light in accordance with display data. Discharge. Then, after the selective erasing discharge is completed over all lines, the sustain discharge is performed. The number of cycles of this sustain discharge varies depending on each sub-frame, and in the case of 256 gradation display, the ratio is 1: 2 :.
It is 4: 8: 16: 32: 64: 128.

In a normal case, the number of sustain discharges is about 500 times in one frame. In this case, if one frame is 60 Hz, the sustain discharge frequency is 30 kHz. In addition to the method of changing the number of sustain discharge cycles of the subframe, there is a method of adjusting the brightness by changing the level of the input signal (display data). Most of parallel type display panels such as PDPs are digitally controlled. Therefore, when the input signal (display data) is an analog signal, the input signal is
It is common to digitize by D conversion and input to the control circuit. In this case, when adjusting the brightness, it is possible to control by the amplitude of the analog data immediately before AD conversion, and 0 can be applied to the digital data after AD conversion.
It is also possible to control the signal level by multiplying by -100%.

None of the general brightness adjustment methods as described above has a function of linearly controlling the brightness adjustment in each sub-frame while stabilizing the wall charges as in the present invention. It is difficult to adjust the brightness. When performing multi-step brightness control as described above, generally speaking, 256 gradation display for each color means 16
Display of 760,000 colors is possible. Normally, it is said that the color that the human eye can identify under the best environment is 10 million colors. This is the reason why 256 gradations are required for high definition TV. There are 2 million colors at 128 gradations, which is insufficient.

However, it is not necessary to realize 16.76 million colors (= 256 gradations) even when the brightness is lowered.
This is because the discrimination ability at the dark level is far below 10 million colors. Paying attention to this point, when the maximum brightness is 256 gradations, the maximum brightness is 128 at 128%.
Gradation display is also sufficient. Further, when the brightness is reduced to 10%, about 16 gradations (= 4096 colors) is sufficient.

According to the above idea, if the maximum 256 gradations can be accurately controlled, multi-step brightness control can be sufficiently performed.

[0176]

As described above, according to the present invention,
Before the selective writing discharge is performed in the display panel such as the AC type PDP, the wall charges effectively acting on the selective writing discharge are accumulated on the address electrode side (phosphor or dielectric layer). It is very effective in lowering the voltage of the address pulse and preventing write errors. As a means for realizing this wall charge storage operation, the above-described two steps of all-cell write discharge and all-cell erase discharge are executed.

Further, according to the present invention, before writing the display data, writing is performed to all the cells of the selected one display line, and then the erase discharge is performed to all the cells of the selected one display line. As a result, it is possible to make the state of all cells of the selected display line uniform.
In the line-sequential driving method, writing error can be avoided and good image display can be performed.

Furthermore, according to the present invention, before writing the display data, all the cells of the selected display lines are erased after writing to all the cells of the selected display lines. Because I am trying to discharge
It is possible to make the states of all cells of the selected plurality of display lines uniform, avoid writing errors in the multiple line sequential driving method, and perform good image display.

Furthermore, according to the present invention, before the display data is written, the erase discharge is performed in all the cells in all the display lines after writing in all the cells in all the display lines. The state of all cells on all display lines can be made uniform, and writing errors can be avoided in the address / sustain discharge separation driving method, and good image display can be performed.

Furthermore, according to the present invention, before writing the display data, after writing all the cells of all the display lines, the erase discharge is performed in all the cells of all the display lines. In addition, it is possible to make the state of all cells of all display lines uniform, avoid writing mistakes in the address / sustain discharge separate drive method, and perform good image display, and also select one display line. In each cell, the write discharge using the Y electrode and the address electrode is sequentially performed in the cells to be lit to write the display data, and immediately after that, the sustain discharge pulse is applied to the X electrode to stabilize the wall charge. Therefore, the wall charges can be stabilized until the sustain discharge period.

Furthermore, in the present invention, since the X electrodes are commonly connected to each block formed by dividing the display line into a plurality of blocks, writing errors can be avoided and good image display can be performed. As well as
The wall charges can be stabilized until the sustain discharge period, and further, the power consumption can be reduced by the sustain discharge pulse for stabilizing the wall charges in the address period. That is, during the address period for writing the display data, the sustain discharge pulse for stabilizing the wall charges is applied only to the X electrodes of the block including the display line for writing the display data, and the display line for writing is applied. It is not necessary to apply the sustain discharge pulse for stabilizing the wall charges to the X electrodes of the block not including the.

On the other hand, according to the present invention, the voltage applied to the second electrode of the non-selected line is made lower than the potential of the sustain discharge pulse or equal to the address voltage. The effective voltage applied to the discharge space can be suppressed below the discharge start voltage, and abnormal discharge between adjacent Y electrodes can be avoided. Further, according to the application example of the present invention, in the method of driving the display panel by separating the address period and the sustain emission (discharge) period, when performing multi-gradation driving for full color display, multi-step brightness adjustment is performed. Can be performed accurately.

Further, it is possible to reduce the reactive power when the brightness is reduced and to realize the low power consumption drive according to the brightness. Further, in the case of the AC type PDP that involves writing on the entire surface, the contrast at low luminance can be improved.
Further, according to the application example of the present invention, when multi-gradation driving for full color display is performed in the method of driving the display panel by separating the address period and the sustain light emission (discharge) period, multi-step brightness adjustment is performed. It can be carried out.

Further, it is possible to reduce the reactive power when the brightness is reduced and to realize the low power consumption drive according to the brightness. Further, in the case of the AC type PDP with all cell writing, the contrast at low brightness can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a drive model of the present invention.

FIG. 2 is a diagram showing a two-electrode type drive model and drive waveforms.

FIG. 3 is a diagram showing a general 3-electrode / self-erasing address type drive model and drive waveforms.

FIG. 4 is a diagram showing a general 3-electrode / selective write address type drive model and drive waveforms.

FIG. 5 is a waveform diagram showing the first embodiment of the present invention.

FIG. 6 is a waveform diagram showing a second embodiment of the present invention.

FIG. 7 is a waveform diagram showing a third embodiment of the present invention.

FIG. 8 is a waveform diagram showing a fourth embodiment of the present invention.

FIG. 9 is a time chart showing an example of a selection line selecting method according to the fourth embodiment of the present invention.

FIG. 10 is a waveform chart showing a fifth embodiment of the present invention.

FIG. 11 is a waveform diagram showing a sixth embodiment of the present invention.

FIG. 12 is a diagram showing a capacitance existing between an X electrode and a Y electrode.

FIG. 13 is a schematic plan view showing a seventh embodiment of the present invention.

FIG. 14 is a diagram showing a seventh embodiment (PDP) of the present invention and its peripheral circuits.

FIG. 15 is a waveform diagram showing a method for driving a seventh embodiment of the present invention.

FIG. 16 is a waveform diagram showing a method for driving a seventh embodiment of the present invention.

FIG. 17 is a waveform chart showing an eighth embodiment of the present invention.

FIG. 18 is an operation model diagram of the eighth embodiment of the present invention.

FIG. 19 is another waveform chart showing the eighth embodiment of the present invention.

FIG. 20 is an operation model diagram of the eighth embodiment of the present invention.

FIG. 21 is a block diagram of a PDP to which an eighth embodiment of the present invention is applied.

FIG. 22 is a configuration diagram including a Y scan driver and a Y driver.

FIG. 23 is an operation waveform diagram of FIG. 22.

FIG. 24 is a simplified diagram of FIG. 22.

FIG. 25 is a detailed diagram of an X driver.

FIG. 26 is a detailed diagram of an address driver.

FIG. 27 is another configuration diagram including a Y scan driver and a Y driver.

28 is an operation waveform diagram of FIG. 27.

FIG. 29 is a simplified diagram of FIG. 27.

FIG. 30 is yet another configuration diagram including a Y scan driver and a Y driver.

FIG. 31 is a cell cross-sectional view of a preferred PDP.

FIG. 32 is a diagram showing drive waveforms according to the ninth embodiment of the present invention.

FIG. 33 is a diagram showing drive waveforms according to the tenth embodiment of the present invention.

FIG. 34 is a diagram showing drive waveforms according to an eleventh embodiment of the present invention.

FIG. 35 is a diagram showing a drive model of the eleventh embodiment of the present invention.

FIG. 36 is a diagram showing drive waveforms according to a twelfth embodiment of the present invention.

FIG. 37 is a diagram showing a drive model according to the thirteenth embodiment of the present invention.

FIG. 38 is a diagram showing drive waveforms in FIG. 37.

FIG. 39 is a schematic plan view showing an example of a conventional PDP.

FIG. 40 is a schematic sectional view showing the basic structure of a cell.

41 is a diagram showing the conventional PDP shown in FIG. 39 and its peripheral circuits.

42 is a waveform chart showing a first example of a conventional method for driving the PDP shown in FIG. 39. FIG.

FIG. 43 is a time chart showing a selection line selection method.

FIG. 44 is a waveform diagram showing a second example of a conventional method for driving the PDP shown in FIG. 39.

[Fig. 45] Fig. 45 is a diagram for describing a method for performing 16-gradation display.

FIG. 46 is a waveform diagram showing a third example of the conventional method for driving the PDP shown in FIG. 39.

FIG. 47 is a layout diagram of an X-Y-Y-X array.

FIG. 48 is a first operation model diagram for explaining abnormal discharge.

FIG. 49 is a second operation model diagram for explaining abnormal discharge.

FIG. 50 is a third operation model diagram for explaining abnormal discharge.

FIG. 51 is a fourth operation model diagram for explaining abnormal discharge.

FIG. 52 is a timing diagram for explaining an example in which the present invention is applied to brightness adjustment of a PDP.

53 is a block diagram showing a circuit configuration for implementing the driving method of FIG. 52.

FIG. 54 is a timing diagram illustrating a method for driving a PDP when general brightness adjustment is not performed.

FIG. 55 is a timing diagram for explaining a driving method of a PDP when brightness is adjusted by general erase discharge.

56 is a drive waveform diagram corresponding to the drive method of FIG. 55.

FIG. 57 is a timing chart for explaining a method of driving a PDP when luminance is adjusted by thinning out general sustain discharge.

58 is a drive waveform diagram corresponding to the drive method of FIG. 56.

FIG. 59 is a timing diagram illustrating a method of driving a PDP when performing gradation display for general brightness adjustment.

FIG. 60 is a timing chart for explaining a method of driving a PDP when grayscale display is performed by separating an address period and a sustain discharge period.

61 is a drive waveform diagram corresponding to the drive method of FIG. 60.

[Explanation of Codes] 36 ... Write pulse 37 ... Sustain discharge pulse 38 ... Narrow erase pulse 39, 40 ... Address pulse 41, 42 ... Sustain discharge pulse SF1 to SF8 ... Subframe N that constitutes one frame forming one screen _{SF1 to} N _SF8 ... Number of sustain discharge cycles in each subframe 111 ... External adjusting means (volume) 112 ... A / D converter 113 ... Selector 114, 121 ... Latch 115 ... Divider 116, 118 ... Counter 117 ... Comparator 119, 120 ... Decoder

Claims (33)

(57) [Claims] 1. A first substrate is provided with first and second electrodes in parallel for each display line, and a second substrate opposed to the first substrate is provided with a third electrode. The display data is written to a cell of at least one display line which is arranged so as to intersect with the second electrode and which is selected by one of the first and second electrodes and the third electrode. AC type plasma display for repeatedly performing address discharge and sustain discharge for maintaining discharge based on display data written by the address discharge
In a display panel comprising a panel, before performing the address discharge, a first step of performing address discharge of all cells in all cells of at least one display line, and all cells of display lines subjected to address discharge of all cells so,
And a second step of the all-cell erasure discharge, by the second step, the write discharge at the cell
It is intended to leave wall charges to have the same polarity as the write pulse applied to Le on the electrode, the remaining wall charges, the writing during the writing discharge
Superposed on the pulse to bring about the address discharge,
A sustain discharge pulse for performing the sustain discharge is applied to the cell.
When applied, excluding the cells that have undergone the address discharge
A method for driving a display panel, wherein the amount is such that no sustain discharge occurs . 2. The plasma display panel
Is at least the second electrode for each display line
Independently, in the first step, the all-cell write discharge using the first and second electrodes is performed in all cells of the selected one display line, and in the second step, Thus in applying an erase pulse to the second electrode or the first electrode of one display line said selected to perform the all-cell erase discharge in all cells of one display line said selected 2. The driving method according to claim 1, wherein the display discharge is performed by causing the address discharge using the second and third electrodes for the cells to emit light. 3. The plasma display panel
Is at least the second electrode for each display line
Independently, in the first step, the all-cell write discharge using the first and second electrodes is performed in all cells of a plurality of selected display lines, and in the second step, wherein depending on applying an erase pulse to the second electrode or the first electrode of the selected plurality of display lines, to perform the all-cell erase discharge in all cells of the plurality of display lines said selected 2. The driving method according to claim 1, wherein the display discharge is performed by causing the address discharge using the second and third electrodes for the cells to emit light. 4. The plasma display panel
Is at least the second electrode for each display line
Independently, in the first step, the all-cell write discharge using the first and second electrodes is performed in all cells of all display lines , and in the second step, all display lines are in applying an erase pulse to the second electrode or the first electrode of
Then, the all-cell erasing discharge is performed on all the cells of all the display lines , and then the second and third electrodes are sequentially used for the cells to emit light for each selected one display line. actual writing of the display data said to perform the write discharge has been
Line and, after the completion of writing of the display data per all the display lines, claim to perform the sustain discharge using the first and second electrodes in the cell to emit light in all the display lines
1. The driving method described in 1 . 5. The plasma display panel
Is at least the second electrode for each display line
Independently, in the first step, the all-cell write discharge using the first and second electrodes is performed in all cells of all display lines , and in the second step, all display lines are in applying an erase pulse to the second electrode or the first electrode of
Then, the all-cell erasing discharge is performed on all the cells of all the display lines , and then the second and third electrodes are sequentially used for the cells to emit light for each selected one display line. The display discharge is performed by performing the address discharge described above, and immediately thereafter, a sustain discharge pulse is applied to the first electrode to perform the sustain discharge for stabilizing the wall charge , and the whole display is performed. After the writing of the display data for each line is completed, the sustain discharge using the first and second electrodes is performed in the cells to emit light in all the display lines.
1. The driving method described in 1 . 6. The first electrode is commonly connected to each block formed by blocking the display line into a plurality of blocks, and the second electrode is independently provided to each display line. The driving method according to claim 1. 7. The first electrode is commonly connected to each block formed by dividing the display line into a plurality of blocks, and the second electrode is independently provided for each display line. In a display panel composed of a plasma display panel, after performing all-cell write discharge using the first and second electrodes in all cells of all display lines, sustain discharge is performed or is caused to be performed. First, the erase pulse is applied to the second electrode or the first electrode of all the display lines to cause the all-cell erase discharge in all the cells of all the display lines, and then the selected one display. For each line, the write discharge using the second and third electrodes is sequentially performed in the cells to emit light to write the display data, and immediately thereafter A sustain discharge pulse is applied to the first electrode of the block including the cell to be caused to carry out sustain discharge for wall charge stabilization, and after the display data has been written to all display lines, all display lines are displayed. The first cell in which the light is emitted
The driving method according to claim 1, wherein the sustain discharge is performed by using the second electrode. 8. A plurality of adjacent two electrodes of the plurality of second electrodes that are continuously selected and driven for writing the display data have a plurality of electrodes driven by a single driver circuit. In a display panel composed of a plasma display panel arranged so as to be sandwiched between the first electrodes, a voltage applied to a second electrode of a non-selected display line causes a sustain discharge to be performed. The driving method according to claim 1, wherein the driving voltage is set to be lower than the pulse potential or equal to the address voltage required for the address discharge. 9. An erase discharge using the first and second electrodes immediately before the all-cell write discharge using the first and second electrodes is performed in all cells of the selected display line. The driving method according to claim 2, wherein 10. The first and second electrodes are used immediately before the all-cell write discharge using the first and second electrodes is performed in all cells of the selected plurality of display lines. The driving method according to claim 3, wherein erasing discharge is performed. 11. An erasing discharge using the first and second electrodes is performed immediately before the all-cell write discharge using the first and second electrodes is performed in all cells of all the display lines. The driving method according to claim 4, which is performed. 12. An erase discharge using the first and second electrodes is performed immediately before the all-cell write discharge using the first and second electrodes is performed in all cells of all the display lines. The driving method according to claim 5, which is performed. 13. An erase discharge using the first and second electrodes is performed immediately before the all-cell write discharge using the first and second electrodes is performed in all cells of all the display lines. The driving method according to claim 7, which is performed. 14. Immediately after performing the all-cell write discharge using the first and second electrodes in all the cells of the selected display line, a narrow pulse that does not cause an erase discharge is applied. The driving method according to claim 2, wherein the sustain discharge is performed by performing the sustain discharge. 15. Immediately after the all-cell write discharge using the first and second electrodes is performed in all the cells of the selected plurality of display lines, a narrow pulse that does not result in an erase discharge is generated. The driving method according to claim 3, wherein a sustain discharge is performed by applying the voltage. 16. Immediately after performing the all-cell write discharge using the first and second electrodes in all the cells of all the display lines, a narrow pulse that is not an erase discharge is applied. The driving method according to claim 4, wherein a sustain discharge is performed. 17. Immediately after performing the all-cell write discharge using the first and second electrodes in all the cells of all the display lines, a narrow pulse that does not cause erase discharge is applied. The driving method according to claim 5, wherein sustaining discharge is performed. 18. Immediately after performing the all-cell write discharge using the first and second electrodes in all the cells of all the display lines, a narrow pulse that does not cause an erase discharge is applied. The driving method according to claim 7, wherein the sustain discharge is performed. 19. One frame constitutes one screen, respectively.
Consists of multiple sub-frames with predetermined brightness, Each sub-frame includes the first sub-frame for performing the all-cell write discharge.
Step 1 and the second step of performing the all-cell erase discharge
Step and the writing to execute writing of display data
An address period in which discharge is performed for each display line,
Perform a sustain discharge that maintains the discharge based on the display data
Has a sustain discharge period, Grayscale display can be performed by selecting any subframe.
The driving method according to claim 1, further comprising: 20. The driving method according to claim 1, wherein the number of sustain discharges in each sub-frame is increased / decreased at the same ratio to control the luminance over the entire screen. 21. When the driving for the gradation display is performed, the number of sustain discharges in a sub-frame having the maximum luminance weight is determined, and the sub-pixel having the next largest luminance weight is determined based on the determined number. The number of sustain discharges in a frame is determined, and thereafter, the number of sustain discharges in the subframe is determined based on the number of sustain discharges in a subframe whose luminance weight is one rank higher. The driving method according to claim 20. 22. The claims magnitude of luminance weight the number of sustain discharges in the sub-frame is set to 1/2 of the number of sustain discharges in the sub-frame of one rank 21
The driving method described. 23. The driving method according to claim 22 , wherein when the number of sustain discharges is set to ½ when a fraction is obtained, the fraction is rounded down or rounded up. 24. The first and second electrodes are arranged in parallel for each display line on the first substrate, and the third electrode is provided on the second substrate facing the first substrate. The display data is written to a cell of at least one display line which is arranged so as to intersect with the second electrode and which is selected by one of the first and second electrodes and the third electrode. A display panel comprising an alternating-current plasma display panel that repeatedly performs a write discharge and a sustain discharge that maintains a discharge based on display data written by the write discharge, the first electrode, the second electrode, and the third electrode. Drive means for supplying a plurality of types of drive voltage pulses to the electrodes of the plurality of electrodes, and control means for controlling the order of supplying the plurality of types of drive voltage pulses, the control means comprising: By the means, before performing the address discharge, all-cell write discharge is performed in all cells of at least one display line, and then all-cell erase discharge is performed in all cells of the display line subjected to the all-cell write discharge, Writing applied to the cell during the writing discharge by
Wall charges have the same polarity as the pulse allowed to remain on the electrode
Is configured to that, the remaining wall charges, the writing during the writing discharge
Superposed on the pulse to bring about the address discharge,
A sustain discharge pulse for performing the sustain discharge is applied to the cell.
When applied, excluding the cells that have undergone the address discharge
Driving device for a display panel whose serial sustain discharge is characterized Ryodea Rukoto that does not cause. 25. The control means is driven by the drive means.
And applying an address pulse for performing the all-cell address discharge using the first and second electrodes in all the cells of the selected one display line , and then applying the selected pulse.
An erase pulse for performing the all-cell erase discharge is applied to the second electrode or the first electrode of one display line ,
After that, for the cells to be made to emit light, the address discharge for applying the address discharge using the second and third electrodes to apply the address pulse for addressing the display data is applied.
That controls claim 24 drive according. 26. The control means comprises the drive means.
And applying an address pulse for performing the all-cell address discharge using the first and second electrodes in all the cells of the selected plurality of display lines , and then applying the selected pulse.
An erasing pulse for performing the all-cell erasing discharge is applied to the second electrode or the first electrode of several display lines ,
After that, for the cells to be made to emit light, the address discharge for applying the address discharge using the second and third electrodes to apply the address pulse for addressing the display data is applied.
That controls claim 24 drive according. 27. The control means applies, by the driving means, an address pulse for performing the all-cell address discharge using the first and second electrodes in all cells of all display lines , and then the the erase pulse for performing the all-cell erasure discharge is applied to the second electrode or the first electrode of all the display lines, then, for each one display line selected, sequentially, per cell to emit light The second
And the address discharge Te row Align utilizing the third electrode
The writing of the display data by applying a write pulse line Utame, the display data write per more lines end
After completing the above, in the cells to be lit in all the display lines,
1 and the drive apparatus of claim 24 that controls so as to apply the sustain pulses for performing the sustain discharge using the second electrode. 28. An insulating layer is provided for isolating the third electrode from a discharge space formed between the third electrode and the first and second electrodes, and the insulating layer is provided on the insulating layer. The driving device according to claim 24, wherein the wall charges are configured to be accumulated. 29. Each one frame constituting one screen
Consists of multiple sub-frames with predetermined brightness, Each sub-frame consists of the all cell write discharge and all cell
Full data write / erase period to execute erase discharge and display data
The address discharge for executing the address write is applied to each display line.
Address period to be carried out and release based on the display data.
The sustain discharge period to carry out the sustain discharge
And Grayscale display can be performed by selecting any subframe.
25. The drive device according to claim 24. 30. First means (111 to 1) for determining the number of sustain discharges in a subframe having the maximum luminance weight.
25. The driving device according to claim 24 , further comprising: 13), and second means (115) for determining the number of sustain discharges in a sub-frame having the next largest luminance weight based on the determined number. 31. A means (120) for stopping an operation to be performed in the subframe when the number of sustain discharges in the subframe becomes 0 when the brightness adjustment is performed using the first and second means. , 121) further comprises claims 30 drive according. 32. Means (114) for holding data for determining the number of sustain discharges in the next subframe of the subframe, means (116) for counting the number of sustain discharges in the subframe, and the counting. The method further comprises means (117) for comparing the stored value with the held data, and means (118, 119) for instructing the transition to the next subframe when the two match based on the comparison. Item 32. The drive device according to Item 31 . 33. The first means, according to claim 3 in which the luminance weight is characterized by having a maximum arbitrarily settable means the number of sustain discharges in the sub-frame (111)
0 drive device.