JP2691258B2 - Manufacturing method of MIS field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a method for manufacturing a MIS field effect transistor.

[Prior art]

Conventionally, a method of manufacturing an MIS type field effect transistor, which will be described below with reference to FIG. 2, has been proposed. That is, a semiconductor substrate 1 made of, for example, single crystal Si and having, for example, p-type is prepared in advance (FIG. 2A). Then, on the semiconductor substrate 1, a relatively thin insulating layer 2 made of, for example, SiO ₂ and a conductive layer 3 made of, for example, polycrystalline Si or amorphous Si are sequentially formed in that order (FIG. 2B). Next, a mask layer 4 made of, for example, a photoresist is formed on the conductive layer 3 so as to divide the conductive layer 3 into two parts when viewed from above (FIG. 2C). Next, the conductive layer 3 is subjected to an etching process using the mask layer 4 as a mask to remove the conductive layer 3 from the mask layer 4.
The lower gate electrode layer 5 is formed (FIG. 2D). Next, the mask layer 4 is removed from above the gate electrode layer 5 (FIG. 2E). Next, a relatively thick insulating layer 6 made of, for example, SiO ₂ is formed on the insulating layer 2 so as to cover the gate electrode layer 5 by a deposition method.
Formed (FIG. 2F). Next, by the reactive ion etching treatment on the insulating layers 6 and 2, the insulating layers 7 and 8 extending from the insulating layer 6 on the opposite side surfaces of the gate electrode layer 5 respectively.
And the gate electrode layer 5 and the gate insulating layer 9 below the insulating layers 7 and 8 are formed from the insulating layer 2 (FIG. 2G). Next, the gate electrode layer 5 is sandwiched from the upper surface side in the semiconductor substrate 1 by ion implantation of nm-type impurities using the gate electrode layer 5 and the insulating layers 7 and 8 as a mask. At both positions, a source region 10 and a drain region 11 each having n-type are formed (FIG. 2H). In this case, the source region 10 and the drain region 11 may be obtained as activated by performing a heat treatment on the semiconductor substrate 1 during the ion implantation treatment or after that, or such a heat treatment is not performed. And is obtained as substantially non-activated. Next, the gate electrode layer 12, the source electrode layer 13 and the drain electrode layer 14 are formed on the gate electrode layer 5, the source region 10 and the drain region 11 respectively (FIG. 2I). In this case, the gate electrode layer 12, the source electrode layer 13 and the drain electrode layer 14 are selectively deposited on the gate electrode layer 5, the source region 10 and the drain region 11, respectively, by depositing a metal such as tungsten or molybdenum. ,
Either obtained as a metal layer made of the above-mentioned metal, or the gate electrode layer 5, the source region 10 and the drain region 11
By successively depositing the above-mentioned metal on the above, and then performing a heat treatment, the regions of the metal deposition layer on the gate electrode layer 5, the source region 10 and the drain region 11 are silicidized, and then the metal deposition layer is formed. The regions on the insulating layers 7 and 8 are removed by an etching process to obtain a metal silicide layer obtained by siliciding the metal described above. When the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are formed as the above-mentioned metal layer from the state where the source region 10 and the drain region 11 are activated, when forming the metal layer, In any after formation,
It is not necessary to perform heat treatment on the semiconductor substrate 1
When the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are formed as the metal silicide layer described above from the state where the source region 10 and the drain region 11 are activated, the metal silicide layer Since the semiconductor substrate 1 is heat-treated during formation, it is not necessary to perform heat treatment on the semiconductor substrate 1 either during or after the formation of the metal silicide layer, but the gate electrode layer 12 and the source electrode layer are not necessary. When the 13 and the drain electrode layer 14 are formed as the above-mentioned metal layer from the state where the source region 10 and the drain region 11 are not activated, the semiconductor substrate 1 should be heat-treated when the metal layer is formed. Or by forming a metal layer and then subjecting the semiconductor substrate 1 to a heat treatment.
10 and drain region 11 are obtained as activated. The above is the conventionally proposed method of manufacturing the MIS field effect transistor. Although it is clear that the MIS field effect transistor (FIG. 2I) manufactured by the conventional method for manufacturing a MIS field effect transistor shown in FIG. 10 and the drain region 11 do not use only the gate electrode layer 5 for the semiconductor substrate 1 as a mask, but include the gate electrode layer 5 including the insulating layers 7 and 8 formed on the opposite side surfaces of the gate electrode layer 5. Since the source region 10 and the drain region 11 are formed by the ion implantation process of the n-type impurity using the insulating layers 7 and 8 as masks, the source region 10 and the drain region 11 have their opposite side edges at the opposite side surfaces of the gate electrode layer 5. It is formed without unnecessarily extending inward of the bottom. Therefore, MI
Exhibits good function as an S-type field effect transistor. Further, according to the manufacturing method of the MIS field effect transistor described above with reference to FIG. 2, the source region 10 and the drain region 11 are
As described above, since the opposite side edges can be formed without unnecessarily extending inwardly below the opposite side surfaces of the gate electrode layer 5, the MIS field effect transistor can be formed with good performance. It can be manufactured as one having various characteristics.

[Problems to be solved by the invention]

In the case of the conventional MIS type field effect transistor manufacturing method shown in FIG. 2, on the insulating layer 2 formed on the semiconductor substrate 1,
After the step of forming the insulating layer 6 so as to cover the gate electrode layer 5 (FIG. 2F), the side surfaces of the insulating layer 6 facing each other of the gate electrode layer 5 are subjected to a reactive ion etching treatment on the insulating layer 6. Insulating layers 7 and 8 extending respectively are formed on the insulating layer 2 and the gate electrode layer 5 from the insulating layer 2.
Step of forming lower gate insulating layer 9 (FIG. 2G)
In the case where the gate electrode layer 5 has a pinhole, ions or radicals thereof used for the reactive ion etching process pass through the pinhole of the gate electrode layer 5 and pass through the gate electrode layer 5 of the insulating layer 2. Irradiate the lower region, and thus the gate insulating layer 9 may be formed as having a pinhole or a weak point, and thus the gate insulating layer 9 may be formed as having a low breakdown voltage. Had. Therefore, there is a possibility that the MIS field effect transistor may be manufactured with a low gate breakdown voltage. Further, the source region 10 and the drain region 11 are formed in the semiconductor substrate 1 from the upper surface side by ion implantation of n-type impurities into the semiconductor substrate 1 using the gate electrode layer 5 and the insulating layers 7 and 8 as a mask. After the step of forming (FIG. 2H), the step of forming the gate electrode layer 12, the source electrode layer 13 and the drain electrode layer 14 on the gate electrode layer 5, the source region 10 and the drain region 11 (FIG. 2) I), the gate electrode layer 12 and the source electrode layer are formed on the insulating layer 7.
The layer made of the material of 13 is the gate electrode layer 12 and the source electrode layer.
A layer made of the material of the gate electrode layer 12 and the drain electrode layer 14 is formed between the gate electrode layer 12 and the drain electrode layer 14 on the insulating layer 8 while being extended so as to short-circuit them. In addition, there is a fear that they may be formed by being extended so as to short them. Therefore, there is a fear that the MIS field effect transistor is manufactured as a device that does not have the function of the MIS field effect transistor. Therefore, the present invention proposes a method for manufacturing a novel MIS type field effect transistor which does not have the above-mentioned drawbacks.

[Means for Solving the Problems]

The manufacturing method of the MIS type field effect transistor according to the present invention is
The process has the following steps. That is, on the semiconductor substrate having the first conductivity type,
A step of sequentially forming a relatively thin first insulating layer, a conductive layer, and a nitride layer in that order; a step of forming a first mask layer on the nitride layer; Forming a second mask layer underneath the first mask layer from the nitride by a first etching process using the first mask layer as a mask for the layer; Forming a first gate electrode layer under the second mask layer from the conductive layer by a second etching process using the first and second mask layers as a mask; and the second mask layer. After removing the first mask layer from above, a heat treatment is performed on the first gate electrode layer using the second mask layer as a mask, so that the side surfaces of the first gate electrode layer that face each other are opposed to each other. Forming second and third insulating layers A step of, in the first insulating layer, a relatively thick fourth insulating layer, the second
And a step of forming the third insulating layer, the first gate electrode layer and the second mask layer so as to cover the first and fourth insulating layers, and the fourth step is performed by a reactive ion etching process for the first and fourth insulating layers. Of the fifth insulating layer and the third insulating layer extending from the insulating layer to the outer surface of the second insulating layer and the side surface of the second mask layer on the second insulating layer side. Forming a sixth insulating layer on the outer side surface and on a side surface of the second mask layer on the side of the third insulating layer, and from the first insulating layer to the first gate; Forming an electrode layer and a gate insulating layer under the second, third, fifth and sixth insulating layers; and the second mask layer for the semiconductor substrate, the second, third, fifth and Impurity giving a second conductivity type opposite to the first conductivity type using the sixth insulating layer as a mask Forming a source region and a drain region having a second conductivity type in the semiconductor substrate from the upper surface side at both positions sandwiching the first gate electrode layer by an ion implantation process; After removing the second mask layer from the first gate electrode layer, the second gate electrode layer, the source electrode layer and the drain electrode are provided on the first gate electrode layer, the source region and the drain region. Forming each layer.

[Action / Effect]

The MIS type field effect transistor manufactured by the manufacturing method of the MIS type field effect transistor according to the present invention is similar to the case of the MIS type field effect transistor manufactured by the conventional manufacturing method of the MIS type field effect transistor described in FIG. , MIS type field effect transistor, and the source region and the drain region are formed in accordance with the conventional MIS type field effect transistor manufacturing method described above with reference to FIG. Since the source region and the drain region are formed without unnecessarily extending their opposing side ends inwardly below the opposing side faces of the gate electrode layer, they function as a MIS field effect transistor. Is exhibited with good characteristics. Further, according to the method of manufacturing the MIS type field effect transistor of the present invention, as in the case of the method of manufacturing the conventional MIS type field effect transistor described above with reference to FIG. Since the opposite side edges of the gate electrode layer can be formed without unnecessarily extending inwardly below the opposite side surfaces of the gate electrode layer, MI
The S-type field effect transistor can be manufactured as having good characteristics. However, in the method of manufacturing the MIS type field effect transistor according to the present invention, a relatively thick fourth insulating layer is formed on the first insulating layer formed on the semiconductor substrate, and the second and third insulating layers, After the step of forming the first gate electrode layer and the second mask layer so as to cover the first and fourth insulating layers, a reactive ion etching process is performed on the first and fourth insulating layers to remove the second insulating layer from the fourth insulating layer. The fifth insulating layer extending on the outer side surface and the side surface of the second mask layer on the side of the second insulating layer, and the outer surface of the third insulating layer and the third insulating layer of the second mask layer. And a sixth insulating layer extending on the side surface on the layer side, and in the step of forming the gate insulating layer from the first insulating layer, the reactive ion etching process masks the second mask layer. Therefore, a pinhole is formed in the first gate electrode layer. Even if that, since ions or region under the gate electrode layer of the first insulating layer by the radicals is used in the reactive ion etching process is not irradiated, the gate insulating layer, conventional MIS described above in Figure 2
The field effect transistor has a higher breakdown voltage than that of the field effect transistor. Therefore, the MIS field effect transistor can be manufactured with a high gate breakdown voltage. Further, according to the method of manufacturing the MIS field effect transistor according to the present invention, after forming the source region and the drain region in the semiconductor substrate, the second gate electrode is formed on the first gate electrode layer and the source region and the drain region. In the step of forming the layer, the source electrode layer, and the drain electrode layer, respectively, the second gate electrode layer, the source electrode layer, and the warp electrode layer form a second gate electrode layer and a source electrode layer, and a second
The risk of being formed by short-circuiting the gate electrode layer and the drain electrode layer is significantly less than in the case of the conventional method for manufacturing a MIS field effect transistor described above with reference to FIG. Can be manufactured with good yield.

[Embodiment 1] Next, an embodiment of a method of manufacturing an MIS type field effect transistor according to the present invention will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The manufacturing method of the MIS type field effect transistor according to the present invention shown in FIG. 1 has the following sequential steps. That is, as in the case of the conventional MIS field effect transistor manufacturing method described above with reference to FIG. 2, a semiconductor substrate 1 made of, for example, single crystal Si and having, for example, p-type is prepared in advance (FIG. 1A). Then, on the semiconductor substrate 1, a relatively thin insulating layer 2 made of, for example, SiO ₂ , a conductive layer 3 made of, for example, polycrystalline Si or amorphous Si, and a nitride layer 21 made of, for example, silicon nitride are provided. The layers are sequentially formed (FIG. 1B). Next, a mask layer 4 made of, for example, a photoresist is formed on the nitride layer 21 so as to divide the conductive layer 3 into two parts when viewed from above (FIG. 1C). Next, the nitride layer 21 is removed from the mask layer 4 by an etching process using the mask layer 4 as a mask.
Another mask layer 22 below is formed (FIG. 1D). Next, the gate electrode layer 5 under the mask layer 22 is formed from the conductive layer 3 by etching the conductive layer 3 using the mask layers 4 and 22 as a mask (FIG. 1E). Next, the mask layer 4 is removed from the gate electrode layer 5 (FIG. 1F). Next, the insulating layers 23 and 24 are formed on the opposite side surfaces of the gate electrode layer 5 by heat treatment using the mask layer 22 for the gate electrode layer 5 as a mask (FIG. 1G). Next, a relatively thick insulating layer 6 made of, for example, SiO ₂ is formed on the insulating layer 2 by a deposition method, covering the mask layer 22, the insulating layers 23 and 24, and the gate electrode layer 5 (first method). (Figure H). Next, by performing a reactive ion etching process on the insulating layers 6 and 2, the insulating layer 7 is insulated from the insulating layer 6 extending on the outer surface of the insulating layer 23 and the side surface of the mask layer 22 on the insulating layer 23 side. The insulating layer 8 extending on the outer surface of the layer 24 and the side surface of the mask layer 22 on the insulating layer 24 side is formed, and from the insulating layer 2, the gate electrode layer 5, the insulating layers 23 and 7,
A gate insulating layer 9 is formed under the insulating layers 24 and 8 (FIG. 1I). Next, with respect to the semiconductor substrate 1, the mask layer 22 and the insulating layer 23
And 7 and the n-type impurity ion implantation process using the insulating layers 24 and 8 as masks, both have n-type in the semiconductor substrate 1 from the upper surface side at both positions sandwiching the gate electrode layer 5. A source region 10 and a drain region 11 are formed (FIG. 1J). In this case, the source region 10 and the drain region 11 may be obtained as activated by performing a heat treatment on the semiconductor substrate 1 during the ion implantation treatment or after that, or such a heat treatment is not performed. And is obtained as substantially non-activated. Next, the mask layer 22 is removed from the gate electrode layer 5 (K in FIG. 1), and then the gate electrode layer 12, the source electrode layer 13 and the gate electrode layer 5, the source region 10 and the drain region 11 are formed. Each drain electrode layer 14 is formed (FIG. 1L). In this case, the gate electrode layer 12, the source electrode layer 13 and the drain electrode layer 14 are selectively deposited on the gate electrode layer 5, the source region 10 and the drain region 11, respectively, by depositing a metal such as tungsten or molybdenum. ,
Either obtained as a metal layer made of the above-mentioned metal, or the gate electrode layer 5, the source region 10 and the drain region 11
By successively depositing the above-mentioned metal on the above, and then subjecting it to a heat treatment, the regions on the gate electrode layer 5, the source region 10 and the drain region 11 of the metal deposition layer are silicidized, and then the metal deposition is performed. The regions on the insulating layers 7 and 8 of the layer are removed by an etching process to obtain a metal silicide layer of the above-mentioned metal silicide. When the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are formed as the above-mentioned metal layer from the state where the source region 10 and the drain region 11 are activated, when forming the metal layer, In any after formation,
It is not necessary to perform heat treatment on the semiconductor substrate 1
When the gate electrode layer 12, the source electrode layer 13, and the drain electrode layer 14 are formed as the metal silicide layer described above from the state where the source region 10 and the drain region 11 are activated, the metal silicide layer Since the semiconductor substrate 1 is heat-treated during formation, it is not necessary to perform heat treatment on the semiconductor substrate 1 either during or after the formation of the metal silicide layer, but the gate electrode layer 12 and the source electrode layer are not necessary. When the 13 and the drain electrode layer 14 are formed as the above-mentioned metal layer from the state where the source region 10 and the drain region 11 are not activated, the semiconductor substrate 1 should be heat-treated when the metal layer is formed. Or by forming a metal layer and then subjecting the semiconductor substrate 1 to a heat treatment.
10 and drain region 11 are obtained as activated. The above is the embodiment of the method of manufacturing the MIS field effect transistor according to the present invention. The MIS field effect transistor manufactured by the embodiment of the method for manufacturing the MIS field effect transistor according to the present invention is the MIS field effect manufactured by the conventional method for manufacturing the MIS field effect transistor described above with reference to FIG. As in the case of the transistor, it is obvious that it exhibits the function as an MIS type field effect transistor, and the source region 10 and the drain region 11 are produced by the conventional MIS type field effect transistor manufacturing method described above with reference to FIG. The source region 10 and the drain region 11 are formed according to
Since the opposite side edges are formed without being unnecessarily extended inward from the lower side surfaces of the gate electrode layer 5 opposite to each other, the function as the MIS field effect transistor is exhibited with good characteristics. . Further, according to the manufacturing method of the MIS type field effect transistor according to the present invention shown in FIG. 2, the conventional MIS described in FIG.
As described above, the source region 10 and the drain region 11 need not have their opposite side edges inside the side surfaces of the gate electrode layer 5 which face each other, as in the case of the manufacturing method of the field effect transistor. Since it can be formed without being extended, the MIS field effect transistor can be manufactured as having good characteristics. Further, in the case of the manufacturing method of the MIS type field effect transistor according to the present invention shown in FIG. 2, a comparatively thick insulating layer 6 is formed on the insulating layer 2 formed on the semiconductor substrate 1.
4. After the step of forming the gate electrode layer 5 and the mask layer 22 so as to cover the insulating layers 2 and 6, the insulating layer 6 is removed from the insulating layer 6 on the outer surface of the insulating layer 23 and the mask layer 22 by a reactive ion etching process. The insulating layer 7 extending on the side surface on the insulating layer 23 side and the outer surface of the insulating layer 24 and the insulating layer of the mask layer 22.
In the step of forming the insulating layer 8 extending on the side surface on the side of 24 and forming the gate insulating layer 9 from the insulating layer 2, the reactive ion etching process is performed using the mask layer 22 as a mask. Even when the gate electrode layer 5 has a pinhole, the region under the gate electrode layer 5 of the insulating layer 2 is not irradiated with the ions or radicals used for the reactive ion etching treatment, so that the gate insulating layer 9 is As compared with the case of the conventional MIS type field effect transistor described above in the figure, it is formed to have a higher breakdown voltage. Therefore, the MIS field effect transistor can be manufactured with a high gate breakdown voltage. Further, according to the method for manufacturing the MIS field effect transistor of the present invention shown in FIG. 2, the source region is formed in the semiconductor substrate 1.
After forming the drain region 10 and the drain region 11, the gate electrode layer 5,
A gate electrode layer 12 on the source region 10 and the drain region 11,
In the step of forming the source electrode layer 13 and the drain electrode layer 14, respectively, the gate electrode layer 12 and the source electrode layer
There is a possibility that the gate electrode layer 12 and the source electrode layer 13 may be short-circuited between the gate electrode layer 12 and the source electrode layer 13 and the drain electrode layer 14 may be formed by short-circuiting between the gate electrode layer 12 and the drain electrode layer 14 as described above with reference to FIG.
Compared with the manufacturing method of the MIS type field effect transistor, the number is far less, and therefore, the MIS type field effect transistor can be easily manufactured with high yield. Further, in the case of the manufacturing method of the MIS type field effect transistor according to the present invention shown in FIG. 2, the gate electrode layer 12 includes the insulating layers 23 and 7 on the gate electrode layer 5 and the insulating layer 24.
And the insulating layers 23 and 24 are formed in a limited manner, and when the insulating layers 23 and 24 can be formed thickly, the gate electrode layer 12, the source electrode layer 13 and the drain electrode layer 14 are short-circuited. It can be easily formed without any fear. In the above description, only one example of the method for manufacturing the MIS field effect transistor according to the present invention is shown.
Various modifications and changes may be made without departing from the spirit of the present invention.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view in sequential steps showing an embodiment of a method for manufacturing a MIS field effect transistor according to the present invention. FIG. 2 is a schematic cross-sectional view in sequential steps showing a method for manufacturing a conventional MIS field effect transistor. 1 ... Semiconductor substrate 2 ... Insulating layer 3 ... Conductive layer 4 ... Mask layer 5 ... Gate electrode layer 6 ... Insulating layer 7 ... Insulating layer 8 ... Insulating layer 9 ... Gate insulating layer 10 ... Source region 11 …… Drain region 12 …… Gate electrode layer 13 …… Source electrode layer 14 …… Drain electrode layer 21 …… Nitride layer 22 …… Mask layer 23,24 …… Insulating layer

Claims (1)

(57) [Claims] 1. A step of sequentially forming a relatively thin first insulating layer, a conductive layer, and a nitride layer on a semiconductor substrate having a first conductivity type in that order, and the nitride layer. A step of forming a first mask layer thereon, and a first etching process for the nitride layer using the first mask layer as a mask, to remove the nitride layer from the nitride layer.
From the conductive layer by a step of forming a second mask layer under the first mask layer, and a second etching process using the first and second mask layers as a mask for the conductive layer, Forming a first gate electrode layer under the second mask layer; removing the first mask layer from the second mask layer, and then removing the first gate electrode layer from the second mask layer. Forming a second insulating layer and a third insulating layer on opposite side surfaces of the first gate electrode layer by heat treatment using the second mask layer as a mask; and forming a second insulating layer on the first insulating layer. A step of forming a relatively thick fourth insulating layer over the second and third insulating layers, the first gate electrode layer and the second mask layer, and the first and fourth insulating layers. By reactive ion etching treatment on the insulating layer And a fifth insulating layer extending from the fourth insulating layer to the outer surface of the second insulating layer and to the side surface of the second mask layer on the second insulating layer side. Forming a sixth insulating layer extending on an outer surface of the third insulating layer and a side surface of the second mask layer on the side of the third insulating layer, and from the first insulating layer Forming the first gate electrode layer and the gate insulating layer under the second, third, fifth and sixth insulating layers, the second mask layer for the semiconductor substrate, the second, By ion-implanting an impurity giving a second conductivity type opposite to the first conductivity type using the third, fifth and sixth insulating layers as a mask, in the semiconductor substrate, from the upper surface side thereof, At both positions sandwiching the first gate electrode layer,
Forming a source region and a drain region having a second conductivity type; and removing the second mask layer from the first gate electrode layer, and then forming the first gate electrode layer and the source. And a step of forming a second gate electrode layer, a source electrode layer and a drain electrode layer on the drain region and the drain region, respectively.