JP2690512B2 - Frequency multiplier circuit - Google Patents
Frequency multiplier circuitInfo
- Publication number
- JP2690512B2 JP2690512B2 JP63201250A JP20125088A JP2690512B2 JP 2690512 B2 JP2690512 B2 JP 2690512B2 JP 63201250 A JP63201250 A JP 63201250A JP 20125088 A JP20125088 A JP 20125088A JP 2690512 B2 JP2690512 B2 JP 2690512B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- constant current
- input
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は周波数てい倍回路に関し、特に遅延回路と排
他的論理和回路とによって周波数てい倍を行なう回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplication circuit, and more particularly to a circuit for frequency multiplication by a delay circuit and an exclusive OR circuit.
従来、この種の周波数てい倍回路は、第５図の回路図
に示すものがある。すなわち、入力端子１をインバータ
２の入力に接続し、インバータ２の出力をインバータ22
の入力の抵抗21を介して接続し、このインバータ22の入
力に、一端を接地したコンデンサ23の他端を接続し、イ
ンバータ22の出力と入力端子からの入力を入力する排他
的論理和（EX−OR）回路10の出力を出力端子11に接続す
る構成となっていた。Conventionally, this kind of frequency multiplication circuit is shown in the circuit diagram of FIG. That is, the input terminal 1 is connected to the input of the inverter 2, and the output of the inverter 2 is connected to the inverter 22.
Is connected via the resistor 21 of the input of the inverter, the other end of the capacitor 23 whose one end is grounded is connected to the input of this inverter 22, and the output of the inverter 22 and the input from the input terminal are input by the exclusive OR (EX The output of the (-OR) circuit 10 was connected to the output terminal 11.
上述した従来の周波数てい倍回路は、入力周波数ｆ
（Hz），抵抗21の抵抗値ＲΩ，コンデンサ23の容量Ｃ
（Ｆ），インバータ22の論理スレッショルド電圧V
TH（Ｖ），電源電圧Ｅ（Ｖ）とすると、出力デューティ
Dr（％）は次式で示される。The above-mentioned conventional frequency multiplier circuit has an input frequency f
(Hz), resistance value of resistor 21 RΩ, capacitance of capacitor 23 C
(F), logic threshold voltage V of inverter 22
If TH (V) and power supply voltage E (V), output duty
Dr (%) is shown by the following equation.
この式から出力デューティDrは、C,R,VTHの製造バラ
ツキの影響を直接受け、さらにf,Eの使用条件によって
も変動を受けるといった重大の欠点があった。 From this equation, the output duty Dr has a serious drawback that it is directly affected by the manufacturing variations of C, R, and V TH , and is also changed depending on the usage conditions of f and E.
本発明の目的は、このような問題を解決し、出力デュ
ーティがコンデンサの容量値，抵抗値等の製造バラツキ
に影響されず安定に出力される周波数てい倍回路の提供
することにある。An object of the present invention is to solve such a problem and to provide a frequency multiplying circuit whose output duty is stably output without being affected by manufacturing variations such as a capacitance value and a resistance value of a capacitor.
本発明の構成は、周期的信号である入力信号を遅延さ
せる遅延回路と、この遅延回路の出力信号と前記入力信
号との排他的論理和をとる排他的論理和回路とを有し、
この排他的論理和回路の出力を前記入力信号のてい倍出
力とした周波数てい倍回路において、前記遅延回路が、
定電流源と接続され前記入力信号により切換えられるス
イッチング回路とこのスイッチング回路の出力端に並列
接続される第１のコンデンサとからなる充放電回路と、
この充放電回路の出力端から第２のコンデンサを介して
結合されたコンデンサ結合増幅器とを備え、前記定電流
源が出力波形を積分した電圧により制御される圧制御型
定電流源からなることを特徴とする。The configuration of the present invention includes a delay circuit that delays an input signal that is a periodic signal, and an exclusive OR circuit that takes an exclusive OR of the output signal of the delay circuit and the input signal,
In the frequency multiplication circuit in which the output of the exclusive OR circuit is the multiplication output of the input signal, the delay circuit is
A charging / discharging circuit comprising a switching circuit connected to a constant current source and switched by the input signal, and a first capacitor connected in parallel to the output terminal of the switching circuit,
And a capacitor coupling amplifier coupled from the output end of the charging / discharging circuit via a second capacitor, wherein the constant current source is a pressure control type constant current source controlled by a voltage obtained by integrating an output waveform. Characterize.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明に関連する周波数てい倍回路の回路
図、第２図は第１図の動作を示すタイミング図である。
第１図で入力端子１はインバータ２の入力に接続され、
このインバータ２の出力とMOSトランジスタ3,4のゲート
が接続される。また、定電流源５を電源VDDとMOSトラン
ジスタ３のソースとの間に接続し、定電流源６をMOSト
ランジスタ４のソースと接地との間に接続し、MOSトラ
ンジスタ3,4の両ドレインを一端に接地したコンデンサ
７の他端と接続し、この両ドレインからコンデンサ８を
介して増幅器９の入力端と接続し、入力端子１と増幅器
９の出力とを入力とする排他的論理和10の出力を出力端
子11と接続している。FIG. 1 is a circuit diagram of a frequency multiplier circuit relating to the present invention, and FIG. 2 is a timing chart showing the operation of FIG.
In FIG. 1, the input terminal 1 is connected to the input of the inverter 2,
The output of the inverter 2 and the gates of the MOS transistors 3 and 4 are connected. Further, the constant current source 5 is connected between the power source V DD and the source of the MOS transistor 3, the constant current source 6 is connected between the source of the MOS transistor 4 and the ground, and both drains of the MOS transistors 3 and 4 are connected. Is connected to the other end of the capacitor 7 which is grounded at one end, is connected from both drains to the input end of the amplifier 9 via the capacitor 8, and the exclusive OR 10 is input to the input terminal 1 and the output of the amplifier 9. The output of is connected to the output terminal 11.
第１図の回路によれば、増幅器９の力波形は、第２図
に示す様に、定電流源5,6の値とコンデンサ７の値で定
まる傾斜を持った三角波となるため、増幅器９の入力で
はそのスレッショルド電圧VTHを境に傾斜部が対称とな
り、てい倍出力はデューティ50％の出力波形となる。According to the circuit of FIG. 1, the force waveform of the amplifier 9 becomes a triangular wave having a slope determined by the values of the constant current sources 5 and 6 and the value of the capacitor 7, as shown in FIG. At the input of, the sloped portion becomes symmetrical with the threshold voltage V TH as a boundary, and the doubled output has an output waveform with a duty of 50%.
なお、定電流値、コンデンサの容量値等に製造バラツ
キがあっても、三角波の波高値を変化させるだけであ
り、その傾斜部の対称性は損なわないので、出力デュー
ティはその影響を受けず、常に50％となる。Even if there are manufacturing variations in the constant current value, the capacitance value of the capacitor, etc., the crest value of the triangular wave is only changed, and the symmetry of the inclined portion is not impaired, so the output duty is not affected by it. Always 50%.
第３図は本発明の一実施例の回路図である。本実施例
は、第１図の定電流源5,6の代りに電圧制御型定電流源
５′,6′を用いて出力波形が50％のデューティとなるよ
うにフィードバック制御していることを特徴とする。す
なわち、入力端子１とインバータ２の入力を接続し、イ
ンバータ２の出力とMOSトランジスタ3,4のゲートを接続
し、一端を電源VDDに接続した電圧制御定電流源５′の
他端をMOSトランジスタ３のソースに接続し、一端を接
地した電圧制御定電流源６′の他端をMOSトランジスタ
４のソースに接続し、MOSトランジスタ3,4を両ドレンイ
ンと一端を接地したコンデンサ７の他端と、一端を増幅
器９の入力と接続したコンデンサ８の他端とを接続し、
入力端子１と増幅器９の出力を入力とする排他的論理和
10の出力を出力端子11とインバータ12の入力に接続し、
インバータ12の出力を入力とする積分器13の出力を比較
器14のプラス入力に接続し、基準電圧15を比較器14のマ
イナス入力に接続し、比較器14の出力を入力とする積分
器16の出力を電圧制御定電流源５′,6′の電圧制御入力
に接続する。この基準電圧15は電源電圧VDDの1/2として
いる。FIG. 3 is a circuit diagram of one embodiment of the present invention. In this embodiment, voltage controlled constant current sources 5'and 6'are used in place of the constant current sources 5 and 6 in FIG. 1 to perform feedback control so that the output waveform has a duty of 50%. Characterize. That is, the input terminal 1 is connected to the input of the inverter 2, the output of the inverter 2 is connected to the gates of the MOS transistors 3 and 4, and the other end of the voltage-controlled constant current source 5 ′ whose one end is connected to the power supply V DD is connected to the MOS. The other end of the voltage controlled constant current source 6 ', which is connected to the source of the transistor 3 and whose one end is grounded, is connected to the source of the MOS transistor 4, and the drains of the MOS transistors 3 and 4 and the other end of the capacitor 7 whose one end is grounded. And the other end of the capacitor 8, one end of which is connected to the input of the amplifier 9,
Exclusive OR with input terminal 1 and output of amplifier 9 as input
Connect the output of 10 to the output terminal 11 and the input of the inverter 12,
The output of the integrator 13 which receives the output of the inverter 12 is connected to the positive input of the comparator 14, the reference voltage 15 is connected to the negative input of the comparator 14, and the integrator 16 whose input is the output of the comparator 14 Is connected to the voltage control inputs of the voltage controlled constant current sources 5'and 6 '. The reference voltage 15 is 1/2 of the power supply voltage V DD .
この回路によれは、第４図の様に、出力端子11のデュ
ーティが50％を越えるときには、積分器13の出力は、基
準電圧15のVDD/2未満となり、比較器14の出力はロウレ
ベルとなり、積分器16の出力を徐々に低下させる。この
積分器16の出力が低下すると、電圧制御定電流源５′,
6′の電流値が小さくなり、遅延時間が長くなり出力デ
ューティを50％に近づけることができる。また、逆に出
力デューティが50％を下廻るときには、前述の場合と全
く反対の動作をし、積分器16の出力が徐々に上昇し、電
圧制御定電流源５′,6′の電流値を大きくし、遅延時間
が短くなり、出力デューティを50％に近づけることがで
きる。According to this circuit, as shown in FIG. 4, when the duty of the output terminal 11 exceeds 50%, the output of the integrator 13 becomes less than V DD / 2 of the reference voltage 15, and the output of the comparator 14 becomes low level. And the output of the integrator 16 is gradually decreased. When the output of the integrator 16 drops, the voltage controlled constant current source 5 ',
The current value of 6'becomes small, the delay time becomes long, and the output duty can be brought close to 50%. On the contrary, when the output duty is less than 50%, the operation is completely opposite to that described above, the output of the integrator 16 is gradually increased, and the current values of the voltage-controlled constant current sources 5'and 6'are changed. It can be increased, the delay time can be shortened, and the output duty can be brought close to 50%.
以上説明したように本発明は、コンデンサの充放電を
定電流源で行ない、その出力三角波をコンデンサ結合増
幅し、入力信号と増幅器出力の排他的論理和をとること
により、定電流値，コンデンサの容量値等の製造バラツ
キや使用条件によらず、出力デューティがほぼ50％の周
波数てい倍回路を得ることができるという効果がある。As described above, the present invention charges and discharges a capacitor by a constant current source, amplifies the output triangular wave by capacitor coupling, and obtains the exclusive OR of the input signal and the amplifier output to obtain the constant current value and the capacitor output. There is an effect that it is possible to obtain a frequency multiplying circuit with an output duty of approximately 50% regardless of manufacturing variations such as capacitance value and usage conditions.
第１図は本発明に関連する周波数てい倍回路の回路図、
第２図は第１図の動作タイミング図、第３図は本発明の
一実施例の回路図、第４図は第３図の動作タイミング
図、第５図は従来の周波数てい倍回路の一例の回路図で
ある。 １……入力端子、2,12,22……インバータ、3,4……MOS
トランジスタ、5,6……定電流源、５′,6′……電圧制
御型定電流源、7,8,23……コンデンサ、９……増幅器、
10……排他的論理和回路、11……出力端子、13,16……
積分器、14……比較器、15……基準電源、21……抵抗。FIG. 1 is a circuit diagram of a frequency multiplier circuit related to the present invention,
2 is an operation timing diagram of FIG. 1, FIG. 3 is a circuit diagram of an embodiment of the present invention, FIG. 4 is an operation timing diagram of FIG. 3, and FIG. 5 is an example of a conventional frequency multiplier circuit. It is a circuit diagram of. 1 …… Input terminal, 2,12,22 …… Inverter, 3,4 …… MOS
Transistor, 5,6 ... Constant current source, 5 ', 6' ... Voltage control type constant current source, 7,8,23 ... Capacitor, 9 ... Amplifier,
10 …… Exclusive OR circuit, 11 …… Output terminal, 13,16 ……
Integrator, 14 …… Comparator, 15 …… Reference power supply, 21 …… Resistance.
Claims (1)
延回路と、この遅延回路の出力信号と前記入力信号との
排他的論理和をとる排他的論理和回路とを有し、この排
他的論理和回路の出力を前記入力信号のてい倍出力とし
た周波数てい倍回路において、前記遅延回路が、定電流
源と接続され前記入力信号により切換えられるスイッチ
ング回路とこのスイッチング回路の出力端に並列接続さ
れる第１のコンデンサとからなる充放電回路と、この充
放電回路の出力端から第２のコンデンサを介して結合さ
れたコンデンサ結合増幅器とを有し、前記定電流源が出
力波形を積分した電圧により制御される圧制御型定電流
源からなることを特徴とする周波数てい倍回路。1. A delay circuit for delaying an input signal which is a periodic signal, and an exclusive OR circuit for exclusive ORing an output signal of the delay circuit and the input signal. In a frequency doubling circuit in which the output of the OR circuit is a doubling output of the input signal, the delay circuit is connected in parallel with a switching circuit connected to a constant current source and switched by the input signal, and in parallel to the output terminal of the switching circuit. And a capacitor coupling amplifier coupled from the output end of the charging and discharging circuit via the second capacitor, and the constant current source integrates the output waveform. A frequency doubling circuit comprising a voltage controlled constant current source controlled by voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63201250A JP2690512B2 (en) | 1987-11-06 | 1988-08-12 | Frequency multiplier circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28145587 | 1987-11-06 | ||
| JP62-281455 | 1987-11-06 | ||
| JP63201250A JP2690512B2 (en) | 1987-11-06 | 1988-08-12 | Frequency multiplier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0256112A JPH0256112A (en) | 1990-02-26 |
| JP2690512B2 true JP2690512B2 (en) | 1997-12-10 |
Family
ID=26512686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63201250A Expired - Lifetime JP2690512B2 (en) | 1987-11-06 | 1988-08-12 | Frequency multiplier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2690512B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5864246A (en) * | 1997-03-31 | 1999-01-26 | Lsi Logic Corporation | Method and apparatus for doubling a clock signal using phase interpolation |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53122351A (en) * | 1977-04-01 | 1978-10-25 | Hitachi Ltd | Generating circuit for double frequency signal |
| JPS59156017A (en) * | 1983-02-25 | 1984-09-05 | Nec Corp | Clock multiplying circuit |
-
1988
- 1988-08-12 JP JP63201250A patent/JP2690512B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0256112A (en) | 1990-02-26 |
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