JP2689456B2 - Image display size conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention uses a video signal read from an image memory composed of a plurality of dual port memories, and a circuit for converting the display size of an image when the image is displayed. It is about.

[Conventional technology]

When an image is displayed on a personal computer or the like by a cathode ray tube or the like, the video signal is temporarily stored in the image memory and the contents of the image signal are sequentially read to display the image. Normally, it is 640.times.400 dots or 320.times.200 dots, and the image memory is configured by using a plurality of 256.times.256.times.4 bit memories.

Therefore, the image memory is generally configured to have a capacity of 768 × 512 × 4 bits or 512 × 256 × 4 bits.

[Problems to be solved by the invention]

However, in the conventional configuration, there are problems that the unused portion in the image memory is large and it is uneconomical, the control circuit of the image memory becomes complicated, and the cost becomes high.

[Means for solving the problem]

In order to solve the above-mentioned problem, the present invention is constituted by the following means.

That is, a clock terminal to which a clock signal is supplied and an enable terminal that stops counting the clock signal in response to the supply of the signal of the first level and starts counting the clock signal in response to the supply of the signal of the second level. And a first counter having an output terminal for outputting the count value as a serial read clock pulse, an inverter having an output terminal connected to the enable terminal, a clock terminal to which a clock signal is supplied, and an inverter for the inverter. A carry output terminal that is connected to the input terminal and counts the supplied clock signal, and outputs a carry signal of the second level when the counted value reaches a predetermined value, and a load to which the output signal of the inverter is input. And a second counter having a terminal.

[Action]

Therefore, the first counter stops the counting operation for each constant of the clock pulse, and the cycle of the serial read clock pulse is extended in response to this, and according to this extension, the reading from the image memory is temporally performed. , And the size of the image display is converted accordingly.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing examples.

FIG. 1 is a block diagram showing the serial port 2 of the image memory 1 including a plurality of dual port memories.
Serial read clock pulse (hereinafter, read pulse)
Is provided with a first counter 3 for supplying the power, and a second counter 4 for controlling the operation thereof.
2 counts clock pulses (hereinafter, CLK). (A) as shown in the timing chart of FIG. 2 showing the waveform of each part, and the counter 3 generates the read pulse (e), while "5" is output, for example. Counter 4 set
Sets the carrier output CR to "H" (high level) every time five CLK (a) are counted and inverted by the inverter 5 to enable the terminals ET and E of the counter 3.
P is set to "L" (low level), its operation is stopped, "L" is also supplied to its own load terminal LD to set the set inputs A to D, and this is repeated. ing.

Therefore, the count output Q _C of the counter 3 is the second
The period shown in FIG. 6F is the period shown in FIG. 7F when the counting operation is not stopped, and the period of the read pulse E is extended to 5/4 times in this example. Video signal V _S read from serial port 2 of No. 1
If the first pixel is output twice in succession, then 5
Two count pixels are output in succession. That is,
When 5 counts are made, the same count value is output twice from the counter 3 so that the serial port 2 is skipped by 5 pixels.
Outputs the same two pixels. As a result, the horizontal direction changes by a factor of 5/4, and a video signal V _{S for} 640 dots is formed per horizontal scanning line.

Therefore, the configuration of the image memory 1 is sufficient with the capacity of 512 × 512 × 4 bits, the required capacity is reduced and the usage of the image memory 1 is economical, and the peripheral control circuit has a simple configuration. be able to.

〔The invention's effect〕

As is clear from the above description, according to the present invention, the clock terminal to which the clock signal is supplied and the count of the clock signal is stopped in response to the supply of the signal of the first level to supply the signal of the second level. A first counter having an enable terminal for starting counting of the clock signal in response to the output signal, an output terminal for outputting the count value as a serial read clock pulse, an inverter having the output terminal connected to the enable terminal, and the clock signal And a carry output terminal that is connected to the input terminal of the inverter and counts the supplied clock signal, and outputs a carry signal of a second level when the counted value reaches a predetermined value. A second counter having a load terminal to which the output signal of the inverter is input, By obtaining, together with the video signal read status from the image memory is temporally scaling, required capacity reduction and usage economy of the image memory is realized,
Since the configuration of the control circuit can be simplified, a remarkable effect can be obtained in image display using the image memory.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, FIG. 1 is a block diagram, and FIG.
FIG. 3 is a timing chart showing the waveform of each part in FIG. 1, and FIG. 3 is an explanatory view schematically showing a specific example of the video signal V _S (an example in which pixels are output in duplicate every 5 pixels). 1 ... Image memory, 3, 4 ... Counter, (a) ... Clock pulse, (e) ... Serial read clock pulse.

Claims (1)

(57) [Claims] 1. An image display size conversion circuit comprising an image memory composed of a plurality of dual port memories and a serial port, wherein a clock terminal to which a clock signal is supplied and a signal of a first level are supplied. A first counter having an enable terminal for stopping the counting of the clock signal and starting the counting of the clock signal in response to the supply of the second level signal; and an output terminal for outputting the count value as a serial read clock pulse , An inverter whose output terminal is connected to the enable terminal, a clock terminal to which a clock signal is supplied, and a clock signal which is connected to the input terminal of the inverter and are supplied are counted, and the counted value is a predetermined value. And a carry output terminal for outputting a carry signal of the second level, A second counter having a load terminal to which an output signal of the inverter is input, wherein the first counter counts the clock signal while a second level signal is supplied to the enable terminal. Then, the counted value is output from the output terminal, and the carry signal of the second level output from the second counter is inverted to the signal of the first level via the inverter and supplied to the enable terminal. A display size conversion circuit for an image, characterized in that the cycle of the serial read clock pulse is divided by stopping the count for one clock.