JP2685999B2 - Parallel execution method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel execution system for executing instructions in parallel.

[0002]

2. Description of the Related Art Conventionally, as a method for executing a plurality of instructions at the same time without paying attention to parallelism, for example, Japanese Patent Laid-Open No.
There is number 7129. This means that multiple instructions can be executed simultaneously in parallel by multiple arithmetic units, the execution result can be written to one shared register, and any arithmetic unit can use the processing result from this shared register by the next instruction. It was done.

[0003]

When a plurality of arithmetic units simultaneously process a plurality of instructions and store the results in the above-mentioned one shared register, the instructions cannot be executed in parallel because of interference between the instructions. When a program written in a language is expanded into instructions, it is expanded so that it can be executed in parallel. As described above, there is a problem in that expansion is required to avoid interference between instructions. It is desired to solve this problem and improve parallel execution performance.

An object of the present invention is to enable instructions to be executed in parallel by simultaneously executing instructions to be executed successively and reflecting the processing result when the correctness is verified.

[0005]

Means for solving the problem will be described with reference to FIG. In FIG. 1, an instruction analysis calculation unit 1 reads an instruction and executes it by referring to a register file 11 and a memory 10.

The determination unit 8 determines the validity of the processing result obtained by simultaneously executing a plurality of consecutive instructions by the plurality of instruction analysis operation units 1. The memory 10 stores instructions and values.

The register file 11 is a register file for storing processing results.

[0008]

According to the present invention, as shown in FIG. 1, a plurality of instructions are processed by the plurality of instruction analysis operation units 1 in the register file 11 respectively.
And the memory 10 to execute the processing, and the determination unit 8 verifies the validity of the processing result based on the reference destination of the previous instruction, the value and the output destination of the subsequent instruction, and the value. At the time of, the processing result of both is registered in the register file 11 or the memory 1.
On the other hand, when there is no validity, only the former processing result is reflected in the register file 11 and the memory 10.

Therefore, when the instructions to be executed successively are executed at the same time and the correctness thereof is verified, the processing result is reflected, so that even if there is interference between the instructions, there is no problem. Can be simultaneously executed to improve processing performance.

[0010]

Next, the structure and operation of an embodiment of the present invention will be sequentially described in detail with reference to FIGS.

In FIG. 1, the instruction analysis operation unit 1 reads an instruction from the instruction buffers 5 and 6, analyzes the instruction,
The shared register file 11 and the memory 10 are referred to, the values are read, the instructed arithmetic processing is performed, the result (output destination, value) is stored in the register file 11 and the memory 10, and the determination unit 8 is notified. Is. Here, the output destination and the value of the operation result are notified to the determination unit 8, and the correctness of the concurrency when the consecutive instructions are simultaneously executed is verified (see FIGS. 2 to 4).

The reference recording registers 3 and 4 record a reference destination and a value of a post-instruction when the instruction operation units (1) and (2) 1 simultaneously execute the instruction, notify the determination unit 8 and continue. This is for verifying the correctness when instructions are executed simultaneously (see FIGS. 2 to 4).

The instruction buffers 5 and 6 read out and store consecutive instructions to be executed simultaneously from the memory 10. In the instruction buffers 5 and 6, the instruction of the address stored in the PC counter (program counter) 7 is read from the memory 10 and stored, and P
The instruction at the address +1 (address of the next instruction) stored in the C counter 7 is read from the memory 10 and stored.

The PC counter 7 is a program counter, and when the determination unit 8 verifies the correctness of simultaneous execution of consecutive instructions, it increments by 2 (address of the next next instruction), while When the correctness is not verified, it is +1 (address of the next instruction) here. The instruction of the address stored in the PC counter 7 is read from the memory 10 and stored in the instruction buffer 5,
The next instruction consecutive from the one-address is read from the memory 10 and stored in the instruction buffer 6.

The determination unit 8 verifies the correctness when consecutive instructions are simultaneously executed. Here, the legitimacy of simultaneous execution is (1) after (2) when the reference destination (reference destination address) referenced by the subsequent instruction is different from the output destination (storage destination address) of the execution result of the previous instruction. When the reference destination referred to by the instruction is the same as the output destination of the execution result of the previous instruction, but the values are the same, it is determined (verified) as valid. In this (1), when two consecutive instructions are executed at the same time, the reference destination referred to by the subsequent instruction and the output destination outputting the execution result of the previous instruction are different, so there is no interference between the two instructions. No, they can be executed simultaneously. Further, in (2), although the reference destination referred to by the subsequent instruction and the output destination outputting the execution result of the previous instruction are the same, the value when the subsequent instruction refers and the value when the previous instruction outputs Since and are the same, there is interference between them, but since they have the same value, they can be executed simultaneously.

The result register 9 is used for the instruction analysis operation unit (2).
Result of execution by 1 (calculation result of subsequent instruction (storage destination, value))
Is a register for temporarily holding. The memory 10 stores instructions and data.

The register file 11 is a register file that stores a processing result and that can be accessed from a plurality of instruction analysis operation units (1) and (2). The plurality of instruction analysis operation units (1), (2), etc. perform an operation by referring to the shared register file 11, store the result, exchange data with each other, and perform high-speed processing. I am trying.

Next, a concrete example will be described in detail with reference to FIG. FIG. 2A shows an example of the instruction 1 and the instruction 2 to be continuously executed. Here, the instruction 1 is A ← A + B, and the value of the variable A and the value of the variable B are added and stored in the variable A.

The instruction 2 is C ← C + A, and the value of the variable C and the value of the variable A are added and stored in the variable C.

FIG. 2B shows the execution procedure. Here, before execution, A = 5, B = 0, C = 5, and PC = 0 (value of the PC counter 7). The side 1 represents the processing of the instruction analysis operation unit (1) 1 in FIG. 1, and the side 2 represents the processing of the instruction analysis operation unit (2) 1 in FIG.

Step: Read the instruction. 1 side: A ← A + B 2 side: C ← C + A Reference recording registers 3 ← C, 5 (Variable C (reference destination) and value “5” are stored, the same applies hereinafter) Reference recording register 4 ← A, Step 5: execute the instruction.

1 side: A '← 5 (the operation result of the step instruction "5" is the value of the temporary variable A', the same applies hereinafter) A ← A '(the value "5" of the temporary variable A'is , (Reflected (stored) in the variable A, and the same hereinafter).

2 side: C '← 10 Step: The judging section 8 compares and verifies the simultaneous executability of two instructions. Here, the output destination A of the calculation result on the 1 side matches the reference destination A of the contents “A, 5” (reference destination A, value 5) of the reference recording register 4 on the 2 side, and therefore the value “ 5 ”are compared, and both are matched here (that is, the value of A before and after execution of the step is matched with“ 5 ”), so it is determined that the concurrency is OK.

Step: Concurrency is O in step
Since it is determined to be K, the operation result C ′ on the side of 2 (the value of the variable C stored and held in the result register 9 of FIG. 1) is used as the actual C (variable C on the register file 11 or the memory 10). Reflect (store). Also, the value of the PC counter 7 is incremented by +2 and updated to the address of the next next instruction.

After execution, A = 5, B = 0, C = 10, PC = 2.

As described above, the two instructions in FIG. 2A are executed at the same time, and the output destination A of the result of the preceding instruction is the same as the reference destination A of the succeeding instruction. Since there is interference between the output destination and the reference destination between the two instructions because they match in 5 ", the values match and it is determined that the concurrency is OK. Therefore, here, the result of the subsequent instruction is instructed by the instruction. The two instructions are executed at the same time.

Next, the specific example of FIG. 3 will be described. FIG. 3A shows an example of the instruction 1 to the instruction 5 to be continuously executed. (B) of FIG. 3 and (b) of FIG.
Indicates an execution procedure. Before execution, A = 5, B = 0, C = 5, and PC = 0. The side 1 represents the processing of the instruction analysis operation unit (1) 1 in FIG. 1, and the side 2 represents the processing of the instruction analysis operation unit (2) 1 in FIG.

(1) One execution cycle Step: Read an instruction. 1 side: A ← A + B 2 side: C ← C + A Reference recording register 3 ← C, 5 (stores variable C (reference destination) and value “5”) Reference recording register 4 ← A, 5 step: Execute instruction .

1 side: A '← 5 (the calculation result "5" of the step instruction is a temporary variable A') A ← A '(the value "5" of the temporary variable A'is reflected in the variable A) (Store).

2 side: C '← 10 Step: The judging section 8 compares and verifies the simultaneous executability of two instructions. Here, the output destination A of the calculation result on the 1 side matches the reference destination A of the contents “A, 5” (reference destination A, value 5) of the reference recording register 4 on the 2 side, and therefore the value “ 5 ”are compared, and both are coincident with each other here, so it is determined that the concurrency is OK.

Step: A step has a concurrency of O.
Since it is determined to be K, the calculation result C ′ on the second side of is reflected (stored) in the actual C (variable C on the register file 11 or the memory 10). Also, the value of the PC counter 7 is incremented by +2 and updated to the address of the next next instruction.

After execution, A = 5, B = 0, C = 10, P
C = 2 (since the concurrency was OK, it is +2 as the amount of the preceding instruction and the succeeding instruction).

(2) One execution cycle Step: Read an instruction. 1 side: B ← B-1 2 side: C ← C + B Reference recording registers 3 ← C, 10 (variable C (reference destination),
Store value "10") Reference recording register 4 ← B, 0 Step: Execute instruction.

1 side: B '← -1 (the calculation result "-1" of the step instruction is a temporary variable B') B ← B '(the value "-1" of the temporary variable B'is a variable Reflected (stored) in B).

2 side: C '← 10 Step: The judging section 8 compares and verifies the simultaneous executability of two instructions. Here, the output destination B of the operation result on the 1 side coincides with the reference destination B of the content “B, 0” (reference destination B, value 0) of the reference recording register 4 on the 2 side, and therefore the value “ 0 "is compared, and both do not match here, so it is determined that the concurrency is NG.

Step: A step has concurrency N
Since it is determined to be G, the calculation result C ′ on the 2 side is not reflected (stored) in the actual C (variable C in the register file 11 or the memory 10). Then, the value of the PC counter 7 is incremented by 1 and updated to the address of the next instruction.

After execution, A = 5, B = -1, C = 10,
PC = 3 (because the concurrency is NG, only the previous instruction is incremented by 1).

(3) One execution cycle ((b) in FIG. 4) Step: Read an instruction. 1 side: C ← C + B 2 side: A ← A-1 Reference recording registers 3 ← A, 5 (store variable A (reference destination) and value “5”) Step: Execute instruction.

1 side: C '← 9 (calculate the operation result of the step instruction "9" as a temporary variable A') A ← A '(reflect the value "9" of the temporary variable A'in the variable A (Store).

2 side: A '← 4 Step: The judging section 8 compares and verifies the simultaneous executability of two instructions. Here, since the output destination C of the calculation result on the 1 side does not match the reference destination A of the contents “A, 5” (reference destination A, value 5) of the reference recording register 4 on the 2 side, there is no dependency. Yes, the concurrency is determined to be OK.

Step: Concurrency is O in step
Since it is determined to be K, the calculation result A ′ on the second side is reflected (stored) in the actual A (register file 11 or variable A in the memory 10). Also, the value of the PC counter 7 is incremented by +2 and updated to the address of the next next instruction.

After execution, A = 4, B = -1, C = 9, P
C = 5 (because the concurrency was OK, it is +2 as the amount of the preceding instruction and the succeeding instruction).

[0043]

As described above, according to the present invention,
When the instructions that should be executed in succession are executed at the same time and the correctness is verified, the processing result is reflected. It is possible to improve the execution performance by executing both simultaneously. As a result, when the output destination of the previous instruction is the reference destination of the subsequent instruction, it cannot be executed at the same time because there is coherence (dependency) between the two. The values between the two match and the validity is OK
It is possible to improve the execution performance by executing them simultaneously when it is determined that.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention.

FIG. 2 is a diagram (part 1) for explaining a specific example of the present invention.

FIG. 3 is a diagram (part 2) for explaining a specific example of the present invention.

FIG. 4 is a diagram (part 3) for explaining a specific example of the present invention.

[Explanation of symbols]

 1: Instruction analysis calculation unit 3, 4: Reference recording register 5, 6: Instruction buffer 7: PC counter (program counter) 8: Judgment unit 9: Result register 10: Memory 11: Register file

Claims (1)

(57) [Claims] 1. A parallel execution method for executing instructions in parallel, a register file (11) for storing a processing result, and a plurality of instructions for reading the instructions and executing the instructions by referring to the register file (11) and a memory. An analysis operation unit (1) and a determination unit (8) for determining the correctness of a processing result obtained by simultaneously executing a plurality of continuous instructions by the plurality of instruction analysis operation units (1) are provided, A plurality of instruction analysis operation units (1) execute processes in parallel with reference to the register file (11) and the memory, and the determination unit (8) outputs the output destination of the previous instruction and the value of the processing result with respect to these processing results. And the reference of the later instruction ,
Validity is verified based on the value of the processing result, and when there is validity, both processing results are reflected in the register file (11) and the memory, while when there is no validity, only the former processing result A parallel execution method characterized in that is configured to be reflected in the register file (11) and the memory.