JP2681425B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a plurality of wirings for transmitting power and signals on a semiconductor substrate.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, in order to meet the recent demand for higher density, the distance between wirings is shortened and the wirings are multi-layered.

For this reason, there arises a problem that a certain wiring malfunctions under the influence of electric charges flowing in the adjacent wiring and the wiring in the upper layer. Particularly, the signal wiring provided near the power supply wiring having a large current is easily affected by noise on the power supply wiring, and the noise on the signal wiring is likely to affect the power supply wiring.

FIG. 8 is a diagram showing an example of a layout of a conventional semiconductor integrated circuit device. Referring to FIG. 8, the semiconductor integrated circuit device includes a semiconductor substrate 1, a signal wiring S1 formed on the semiconductor substrate 1, and power supply wirings S2 and S3. The power supply lines S2 and S3 have a relationship in which, for example, one of them is set to the ground level and the other is set to the drive level. Here, the power supply line S3 is set to the ground level. Wiring capacitances C1, C2, and C3 exist between the signal wiring S1 and the power wiring S2, between the power wiring S2 and the power wiring S3, and between the signal wiring S1 and the power wiring S3, respectively.

FIG. 9 is an equivalent circuit diagram of FIG. 8 in consideration of wiring capacitance. Here, in order to clarify the problem of the conventional technique, the wiring capacitance C1 is assumed to be sufficiently larger than the wiring capacitance C2. The wiring capacitance C3 between the signal wiring S1 and the power supply wiring S3 is extremely small and can be ignored. In the state where there is such a magnitude relation of the wiring capacitance, the signal wiring S when the level of the power supply wiring S2 changes
FIG. 10 shows how the levels of 1 and the power supply line S3 change.

In FIG. 10, t1 is the time when the power supply level of the power supply wiring S2 drops, and t2 is the time when the power supply level of the power supply wiring S2 rises. At time t1,
When the level of the power supply wiring S2 drops, the wiring capacitances C1 and C2 exist, so that the signal wiring S1 and the power supply wiring S
The potential of 3 drops. At time t2, when the level of the power supply wiring S2 rises, the potentials of the signal wiring S1 and the power supply wiring S3 also rise. As described above, since the magnitude relationship of the wiring capacitance is C1 >> C2 (where C1 is much larger than C2), the influence of the signal wiring S1 and the power wiring S3 due to the level change of the power wiring S2 is: The signal wiring S1 is larger.

[0007]

In the conventional wiring layout, as described above, the minute level fluctuation (hereinafter referred to as noise) of the power supply wiring S2 due to the wiring capacitance causes the signal wiring S.
1 is transmitted. As a result, the circuit driven by the signal wiring S1 may malfunction.

On the contrary, the fluctuation of the signal level transmitted to the signal line S1 may be transmitted to the power supply line S2, resulting in malfunction of the circuit.

In general, since the integrated circuit device handles extremely weak signals in the high density and high electric field strength as described above, even a slight noise cannot be ignored.

The present invention has been made to solve the above problems, and provides a semiconductor integrated circuit device capable of suppressing the transmission of noise between a plurality of wirings provided on a semiconductor substrate. That is.

[0011]

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device formed on a semiconductor substrate, wherein wiring used for supplying a power supply current or transmitting a signal, each wiring is a wiring. First and second planar wiring boards that are provided above and below and fixed to a predetermined potential and shield the wiring, and the first and second planar wiring boards respectively at the sides of at least a part of the wiring. It is characterized in that it is provided with a plurality of columnar electrodes that are connected between two planar wiring boards and shield the wiring.

[0012]

In the semiconductor integrated circuit device according to the present invention, the first and second flat wiring boards for shielding are provided above and below the wiring used for supplying power, and the first wiring is provided on the side of the wiring. And, the second planar wiring boards are connected by a plurality of columnar electrodes for shielding. Therefore, a large capacitance is provided between the wiring and the first and second planar wiring boards, and a fluctuation component (noise) generated in the wiring is generated.
Can be attenuated, and noise can be suppressed from being transmitted from each wiring to another wiring. Further, since each wiring is shielded by the first and second planar wiring boards and the plurality of columnar electrodes, each wiring is not affected by noise generated in other wiring. Therefore, malfunction of the circuit due to noise can be suppressed, and the reliability of the device can be improved. Moreover, since it has a simple structure, it can be easily realized by the conventional technique.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a layout configuration of a semiconductor integrated circuit device of the present invention. The semiconductor integrated circuit device shown in FIG. 1 includes a signal wiring S1, a power supply wiring S2, and a power supply wiring S3 similarly to the semiconductor integrated circuit device of FIG. In addition, between the signal wiring S1 and the power supply wiring S2, the power supply wiring S2
Between the signal line S1 and the power supply line S3, and between the signal line S1 and the power supply line S3, respectively.
There are three. The power supply line S2 is surrounded by the insulator 2, and the insulator 2 is surrounded by the power supply line S3.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit device in consideration of wiring capacitance. FIG. 2 is the same as the circuit diagram of FIG. 9 described above, but the size relationship of the wiring capacitances C1, C2, and C3 is different. That is, as is apparent from FIG. 1, since the power supply line S2 is surrounded by the power supply line S3 via the insulator 2, the wiring capacitance C2 is much larger than the other wiring capacitances C1 and C3. The wiring capacitance C1 is the wiring capacitance C
Even when compared with 3, the size is very small and can be ignored.

Next, suppression of noise transmission by the semiconductor integrated circuit device of FIG. 1 will be described.

FIG. 3 is a diagram showing a level change of each wiring of FIG. 1 with respect to power source noise. In FIG. 3, N is noise that fluctuates slightly, and if this noise N is transmitted to the power supply line S2, the power supply line S2 is strongly coupled to the power supply line S3 (ground line) via the wiring capacitance C2. Therefore, the noise component becomes minute due to the wiring capacitance C2. This minute amount of variation causes the level of the power supply wiring S3 to slightly vary. Although the minute fluctuations of the power supply wiring S3 are transmitted to the signal wiring S1 via the wiring capacitance C3, since the wiring capacitance C3 is much smaller than the wiring capacitance C2, the noise transmitted to the power supply wiring is very small. Become. As a result, even if noise is transmitted to the power supply wiring S2, the signal wiring S1 is hardly affected.

FIG. 4 is a diagram showing a level change of each wiring in FIG. 1 with respect to a signal change. When the level of the signal wiring S1 greatly changes due to noise or a clock signal, the wiring capacitance C2 is much larger than the wiring capacitance C3, and the power supply wiring S2 is shielded by the power supply wiring S3. The wirings S2 and S3 are hardly affected by the level change of the signal wiring S1.

As described above, by enclosing the power supply wiring S2 with the insulator 2 and further enclosing it with the power supply wiring S3, it is possible to suppress the transmission of noise generated in the power supply and to transmit the noise to the signal wiring. It is possible to prevent malfunction due to a large-amplitude signal or noise. Such wiring is formed as follows.

FIG. 5 is a diagram for explaining a process of forming the power supply wiring S2 and the power supply wiring S3.

In FIG. 5A, the power supply line S3 is formed on the substrate, the insulator 2 is formed thereon, and the power supply line S2 is further formed thereon.

Next, in FIG. 5B, the power supply wiring S
After the resist film 4 is formed on the surface 2, the power supply wiring S2 is partially removed by etching.

Next, in FIG. 5C, the power supply wiring S
An insulating film 2 ′ is formed so as to surround 2.

In FIG. 5D, after forming a resist film 4'on the insulating film 2 ', a predetermined portion of the laminated insulating layers 2 and 2'is removed.

In FIG. 5E, the removed portion is deposited to form the wiring layer S3 '. Wiring layers S3 and S
3'may be the same substance, but may be of a different type as long as it has a bonding property.

Although the power supply wiring has been described with reference to FIGS. 1 and 5, the signal wiring may be surrounded by the power supply wiring or another signal wiring via an insulator.

In FIG. 1, the power supply wiring S3 (S3 ') is provided so as to entirely surround the power supply wiring S2, but the wiring capacitance between the wiring S2 and the wiring S3 (S3') is sufficient. If it can be enlarged, it does not necessarily have to surround all directions. This example is shown in FIGS. 6 and 7.

FIG. 6 is a layout diagram showing a modification of the power supply wiring shown in FIGS. 1 and 5. The wiring shown in FIG. 6 differs from the wirings of FIGS. 1 and 5 in that the wiring S3 and the wiring S3 ′ are connected by a plurality of contact holes 3. The contact hole 3 connects the wiring S3 and the wiring S3 ', and has a shield effect on the signal wiring (not shown) in the side direction.

As described above, providing the required number of contact holes has the same effect as enclosing the entire surface of the power supply wiring S2.

FIG. 7 shows another one of the power supply wirings of FIGS. 1 to 5.
It is a figure which shows one example of a change. Referring to FIG. 7, the difference between this power supply wiring and the power supply wiring of FIG.
That is, the contact hole 3 is provided only in a portion adjacent to.

Even in this case, the transmission of noise can be suppressed and the shield effect can be obtained as in the embodiment shown in FIGS. 1 and 6.

[0032]

As described above, according to the present invention, the first and second flat wiring boards for shielding are provided above and below the wiring, and the side end portions of the first and second flat wiring boards are provided. Are connected by a plurality of columnar electrodes for shielding, it is possible to shield each wiring and prevent noise transmission between the wirings. Therefore, malfunction of the circuit due to noise can be suppressed, and the reliability of the device can be improved. Moreover, since it has a simple structure, it can be easily realized by the conventional technique.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram considering a capacitance between respective wirings in FIG.

FIG. 3 is a diagram showing a relationship between power supply noise and a level change of each wiring.

FIG. 4 is a diagram showing a relationship between a level change of a signal wiring and a level change of a power supply wiring.

FIG. 5 is a diagram for explaining a step of forming power supply wiring.

FIG. 6 is a layout diagram showing an example of changing power supply wiring.

FIG. 7 is a layout diagram showing a modification example of power supply wiring.

FIG. 8 is a layout diagram of a conventional semiconductor integrated circuit device.

9 is a circuit diagram considering the wiring capacitance of FIG.

FIG. 10 is a diagram showing how the levels of the signal wiring and the power supply wiring change when the level of the power supply wiring changes.

[Explanation of symbols]

 1 semiconductor substrate 2 insulator 3 contact hole S1 signal wiring S2, S3 power wiring

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit device formed on a semiconductor substrate, wherein wiring used for supplying a power supply current or transmitting a signal, each of which is provided above and below the wiring and has a predetermined potential. Fixed to the first and second planar wiring boards for shielding the wiring, and each connected between the first and second planar wiring boards on the side of at least a part of the wiring. A semiconductor integrated circuit device comprising a plurality of columnar electrodes for shielding the wiring.