JPS63232353A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a crosstalk by surrounding part or all of a fine wire made of a conductor with an insulating film, enclosing the periphery of the film with a conductor, and using the wire disposed therein as a wiring. CONSTITUTION:The periphery of a signal line 20 made of a conductive layer is surrounded by an insulating film 30 and a shielding film 40 made of the conductive layer of metal or the like. Accordingly, even if a noise 50 is introduced into this region, it is shielded by the film 40 surrounding the line 20. That is, a coaxial cable wiring is formed in or on the semiconductor layer, and the wire inside is used as a signal line to reduce a crosstalk. The wiring and the shielding material are not limited to aluminum film, but may use Cu, W, Mo or silicide material.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device with a three-dimensional structure, and in particular to a wiring technology suitable for high-density three-dimensional multilayer wiring that reduces cross talk. Regarding.

[Conventional technology]

The basic process of shielded wiring is signal wire (metal).

(polycrystalline semiconductor, single-crystalline semiconductor) is surrounded by an insulating film, and on the next page, these regions are surrounded by metal or a low-resistance semiconductor. One technique for surrounding a single crystal semiconductor with an insulating film is discussed in the 47th Japan Society of Applied Physics (1986 Autumn) Academic Lecture Proceedings, 28P-N-4.

[Problem that the invention seeks to solve]

A three-dimensional structure LSI is a conventional two-dimensional LSI, in which the conventional single-layer LSI layer is stacked into multiple layers with an insulating film in between. It is expected that the functionality and degree of integration will be dramatically improved compared to LSI.

Here, in the LSI having the above structure, signal lines that electrically connect each element run vertically and horizontally in each layer, and there are also interlayer wirings that connect these layers.

Therefore, when focusing on one signal line, many other signal lines are located above, below, to the left, to the right, and mutual interference between signals, that is, cross talk, becomes a problem.

The purpose of this invention is to provide a new wiring method that solves this crosstalk problem.

[Means for solving problems]

The above object is achieved by shielding each signal line individually to prevent signals or noise from other signal lines from being mixed in. This will be explained using FIG. If the signal line 2o made of a conductive layer is surrounded by an insulating film 30 and a shield film 40 made of a conductive layer of metal or the like, even if noise 50 enters this area, the metal thin film 40 surrounding the signal a20 will be removed. It will be shielded by. In other words, if a coaxial cable-like wiring as shown in FIG. 2 is built inside the semiconductor layer or on its surface, and the inner wire is used as a signal line, the problem of crosstalk can be solved.

Taking an LSI made of a Si semiconductor as an example, conductors such as single crystal Si, polycrystalline Si, metals, and their silicides are used as materials for signal lines through which electrical signals are transmitted and wiring through which power is supplied. You can use it. Furthermore, it is effective to use a conductor such as metal or polycrystalline Si as a material for the thin film layer that shields signals that become noise from other wiring lines.

Of course, since the wiring such as a signal line and the shield layer are independent from each other, several types of wiring can be formed by combining the above-mentioned materials.

The process is different for each combination and is explained using the examples below.

〔Example〕

(Example 1) First, a case where both the signal line and the shield layer are formed of metal will be explained.

As shown in FIG. 1, an oxide film 2 with a thickness of 0.4 μm is formed on a P-type wheel crystal Si (100) substrate 1 by a normal thermal oxidation method.
was formed. After this, a 0.1 μm Afl film 12 is formed by sputtering, and a 0.4 μm oxide film 4 is formed by PCVD.
, AQ film 13 of 0.4 μm by sputtering method, and P
Oxide films 6 having a thickness of 0.4 μm were successively formed by the CVD method.

Next, a normal photoresist pattern 7 was formed on the portion that would become the wiring (a).

Next, using this pattern 7 as a mask, an oxide film 6° Aμ film 13. Then, the oxide film 4 was dry etched, and then the pattern 7 was removed. Furthermore, an oxide film 8 of 0.4 μm was deposited thereon by the PCVD method (b).

Thereafter, when the oxide film 8 is removed by sputter etching, the oxide film 8 remains only on the side surfaces of the pattern.

The structure is such that the periphery of the AQ film 13 is covered with an oxide film.

After a shielding AQ film 14 was deposited thereon, a photoresist pattern 10 covering the side surfaces of the pattern was formed, and the AQ film (12 and 14) was etched (c). Next, the photoresist 10 was removed.

Through the above steps, the wiring of the AQ film 13 is formed using an oxide film (4, 6
and 8), and its outer periphery is insulated with AQ film (12 and 1).
4) A shielded structure was obtained.

Thereafter, a 1 μm thick PIQ (polyimide resin) film was deposited to form the glabellar insulating film 11.

By repeating the above steps starting from depositing the AQ film 12 on this interlayer insulating film 11, 2! A shielded wiring of rl was formed (d), and this shielding made it possible to block the influence of noise between the wirings.

Further, by repeatedly using the interlayer insulating film 11, it is possible to form the required number of layers (for example, 10 layers) for wiring.

In this embodiment, an AQ film is used as the wiring and the shielding material, but the present invention is not limited thereto, and Cu, W, Mo, or silicide-based materials may be used.

(Example 2) Next, a case will be described in which a metal film is used as a signal line and a polycrystalline Si film is used as a shield film.

As shown in FIG. 3, an oxide film 2 with a thickness of 0.4 μm is formed on a P-type wheel crystal Si (100) substrate 1 by a normal thermal oxidation method.
was formed. After that, a polycrystalline Si film 21 for shielding with a thickness of 0.1 μm doped with As by the CVD method, and a PCv
Oxide film 4 with a thickness of 0.4 ttrm was formed by the D method, W film 22 with a thickness of 0.4 μm by the sputtering method, and 0.4 ttrm by the PCVD method.
A normal photoresist pattern 7 was formed on the portion that will become the primary wiring after successively forming the oxide film 6 with a thickness of .mu.m (a).

Next, using this pattern 7 as a mask, the oxide film 6 and the W film 2 are
2 and the oxide film 4 were dry etched, and then the pattern 7 was removed. Furthermore, an oxide film 8 of 0.4 μm was deposited thereon by the PCVD method (b).

Thereafter, when the oxide film 8 is removed by sputter etching, the oxide film 8 remains only on the side surfaces of the pattern, resulting in a structure in which the periphery of the W film 22 is covered with an oxide film. On top of that, A for shield
After depositing the polycrystalline Si film 23 doped with s, a photoresist pattern 10 was formed that covered the sides of the pattern, and the polycrystalline Si film (21 and 23) was etched (C).
Next, the photoresist 10 was removed.

Through the above steps, the wiring of the W film 22 is formed into an oxide film (4, 6
, and 8) a polycrystalline insulated with a doped outer periphery;
A shielded structure surrounded by Si films (21 and 23) was created.

After that, 1μm of 5iOz was deposited by bias sputtering method.
A film was deposited to form a glabellar insulating film 11.

Two layers of shielded wiring were formed on this interlayer insulating film 11 by repeating the above steps starting from depositing the polycrystalline Si film 21 (d).

This shield made it possible to block the effects of noise between wiring lines.

Further, by repeatedly using the interlayer insulating film 11, it is possible to form the number of layers (for example, 10 layers) required for wiring.

In this example, a W film was used as the wiring material, but polycrystalline S
It may be a metal or silicide-based material that can withstand heat treatment at an i-film formation temperature of 630°C or higher, and is not limited to As-doped polycrystalline Si, but may also include low-resistance polycrystalline Si.
In this case, the same effects as in the above embodiment can be obtained.

(Example 3) A case where polycrystalline Si is used for both the signal line and the shield film will be described.

As shown in FIG. 4, an oxide film 2 with a thickness of 0.4 μm is formed on a P-type wheel crystal Si (100) substrate 1 by a normal thermal oxidation method.
was formed. After this, a thickness of 0.1 μm doped with As
A shielding polycrystalline silicon film 31, a 0.4 μm thick oxide film 4, an As-doped wiring polycrystalline silicon film 32, and a 0.4 μm thick oxide film 6 were successively formed by CVD. Next, a normal photoresist pattern 7 was formed in the portion that would become the wiring (a).

Next, using this pattern 7 as a mask, the oxide film 6, polycrystalline silicon film 32, and oxide film 4 are dry-etched.
Pattern 7 was then removed. Furthermore, on top of that, CVD
An oxide film 8 of 0.4 μm was deposited by the method (b).

After that, when the oxide film 8 is removed by sputter etching, the oxide film 8 remains only on the side surfaces of the pattern, and the polycrystalline silicon 3
2 is surrounded by an oxide film. After depositing a polycrystalline silicon film 33 for shielding thereon, a photoresist pattern 10 covering the sides of the pattern was formed, and the polycrystalline silicon films (31 and 33) were etched (C).
.

Next, the signal line of the doped polycrystalline silicon film 32 is formed using an oxide film (
4, 6, and 8), and its outer periphery was surrounded by a doped polycrystalline silicon film (31 and 33) to create a shielded structure.

After that, a 1.5 μm thick SOG film was formed.

After further depositing a resist film of 2 μm, the entire surface was etched by 2.5 μm by sputtering to remove the interlayer insulating film 1.
1 was formed. By repeating the same process using the glabellar insulating film 11 thus flattened as the thermal oxide film 2, two layers of shielded wiring were formed as shown in FIG. 3(d).

This shield made it possible to block the effects of noise between wiring lines.

Furthermore, by repeatedly using the planarized interlayer insulating film 11, it is possible to form the number of layers (for example, 10 layers) required for wiring.

In this example, a polycrystalline silicon film doped with As was used as the electrode and the shield material.

The effects of the present invention are not limited to this, and similar effects can be obtained if the polycrystalline silicon film has a lower resistance.

<Embodiment 4> An embodiment in which polycrystalline Si is used as the signal line and metal is used as the shield film will be described.

As shown in FIG. 5, an oxide film 2 with a thickness of 0.4 μm is formed on a P-type wheel crystal Si (100) substrate 1 by a normal thermal oxidation method.
was formed. Thereafter, a 0.1 μm tungsten film 41 is formed by sputtering, a 0.4 μm oxide film 4 is formed by CVD, and a 0.4 μm thick polycrystalline silicon film 42 doped with As. Further, an oxide film 6 of 0.4 μm was formed by CVD method.

Next, a normal photoresist pattern 7 was formed on the portion that would become the wiring (a).

Next, using this pattern 7 as a mask, the oxide film 6° polycrystalline silicon film 42 and oxide film 4 were dry etched in a CFa+Oz atmosphere, and then pattern 7 was removed.

Furthermore, on top of that, a 0.4 μm oxide film 8 is formed using the CVD method.
(b).

Thereafter, when the oxide film 8 is removed by sputter etching, the oxide film 8 remains only on the side surfaces of the pattern, resulting in a structure in which the periphery of the polycrystalline silicon 42 is covered with an oxide film. A tungsten film 43 was deposited thereon, a photoresist pattern 10 covering the side surfaces of the pattern was formed, and the tungsten film (41 and 43) was etched (C).

Next, the wiring of the doped polycrystalline silicon film 42 is replaced with an oxide film (4
, 6 and 8), and the outer periphery is covered with a tungsten film (
41 and 43), a shielded structure was created.

After that, a 1.5 μm thick SOG film was formed, and 2
After a .mu.m thick resist film was deposited, the entire surface was etched away by 2.5 .mu.m by sputtering to form an interlayer insulating film 11. The interlayer insulating film 11 thus planarized was regarded as the thermal oxide film 2, and the same process was repeated to form a two-layer shielded wiring as shown in FIG. 3(d). This shield made it possible to block the effects of noise between wiring lines.

Furthermore, by repeatedly using the planarized interlayer insulation [11], it is possible to form the required number of layers (for example, 10 layers) for wiring.

In this example, tungsten W is used as the electrode shielding material.
However, the method is not limited to this, and is effective for all metals that can withstand heat treatment at a polycrystalline silicon film formation temperature of 630°C or higher.In the above embodiments, the signal line is made of metal or polycrystalline silicon. was being formed. By devising a process, even single crystal Si can be used as a signal line. Examples thereof will be shown in Examples 5 to 9 below.

[Example 5] A fifth embodiment will be explained based on FIG.

A second conductivity type impurity doped layer 51 with a depth of 0.35 μm is formed by doping impurities on the surface of the first conductivity type Si substrate 1, and a 0.3 μm thick layer 51 is formed on the surface of the second conductivity type Si substrate 1.
An ins film 2 was formed. Apply resist to this surface,
Patterned (a).

Next, using the resist 7 as a mask, the SiOx film 2 and the impurity doped layer 51 were etched (b).
A 5iOz film 4 was deposited to a thickness of 0.3 μm by method D.
), anisotropic etching was performed to remove the 5ins film 4 other than those attached to mu of the protrusions (d). At this time, the impurity-doped layer 51 of the second conductivity type is a conductor for wiring, and its surface is covered with the 5i()z films 2, 4, and it has a depletion layer at the boundary with the substrate 1, so it is electrically conductive. is insulated.

On top of this, a shielding polycrystalline Si film 52 doped with electrically active impurities at a high concentration and having a thickness of 0.1 μm was deposited (e). Thereafter, a resist film was formed only on the wiring area (f), and the polycrystalline Si film 52 was etched using this as a mask (g).

Through the above steps, the wiring of the doped single crystal 5i51 is insulated by the oxide films 2 and 4 and the depletion layer at the boundary with the substrate, and shielded by the doped polycrystalline Si film 31 covering the upper part and the Si substrate 1 below. A structure was created.

After that, a 1.5 μm thick SOG film was formed, and 2
After depositing a resist film with a thickness of .mu.m, the entire area was etched by 2.5 .mu.m by sputtering to form a passivation film 11 (h).

In this example, a low-resistance semiconductor was used as the shielding material, but aluminum, tungsten,
Metals such as titanium and molybdenum may also be used.

[Example 6] Using the method described in Example 5, the structure shown in FIG. 6(d) was formed.

Next, as shown in FIG. 7(a), a dopant of the same conductivity type as the substrate is introduced into the substrate surface by ion implantation 61, and as shown in FIG. A high impurity concentration layer 14 of the same conductivity type was formed. Thereafter, the steps described in Section 6@(e) and subsequent sections of Example 5 were carried out to obtain the structure shown in FIG. 7(c).

In the wiring fabricated in Example 5, if a very complete shielding is desired, not only the substrate 1 is connected to the ground, but also the shielding material (highly doped polycrystalline Si film S2) covering the top of the wiring is individually grounded. In comparison, the wiring fabricated in this example has a high impurity concentration layer 62 on the substrate surface, so ohmic contact between the substrate and the upper shield material 52 is good, and the As a result, board 1
only need to be connected to ground.

In this embodiment as well, metal may be used for the shield material as in the fifth embodiment.

[Example 7] As shown in FIG. 8, a first conductivity type high impurity concentration layer 64 is provided near the surface of the first conductivity type substrate 1, and a second conductivity type high impurity concentration layer 64 is formed above the first conductivity type high impurity concentration layer 64. In this case, a layer 51 is formed, and a 5ift film 2 and a resist pattern 10 are formed thereon (a).

5ins film2. The thickness of the second conductivity type high impurity concentration layer 51 and the first conductivity type high impurity concentration layer 64 are as follows:
They are 0.3 μm, 0.35 pm, and 0.2 μm.

The 5iOz film 2 and Si (51,64) were etched using the resist pattern 10 as a mask (b).

Thereafter, by performing the steps described from FIG. 6(c) onwards in Example 5, the structure shown in FIG. 8(c) was obtained.This example is also similar to Example 5.

Metal may be used for the shield material.

[Example 8] As shown in FIG. 9, a single crystal Si film 81 was formed on the substrate having the wiring produced in Example 5 using laser annealing technology.
was formed (a). The process in this case is the normal S-○
I (Silicon on insulator: Si (A
Therefore, SO using other electron beam annealing
I technology, SOI technology using in-phase growth, etc. may be used.

Thereafter, electrically active impurities were introduced into the single crystal Si film 81 at a high concentration by ion implantation (b).

This bale was subjected to the steps described in Example 5 to obtain a two-layer wiring structure (Q). By using this as a substrate and repeating the steps of this example, it is possible to create even more layers of shielded wiring. Since the same process is repeated, there is no limit to the number of layers, and multilayer wiring of 10 or 20 layers is also possible if necessary.

In this embodiment as well, metal may be used for the shield material as in the fifth embodiment.

[Example 9] As shown in FIG. 10, on the substrate having the wiring produced in Example 6, S
A single crystal Si film 15 was formed using OI technology (a).

Thereafter, by ion implantation, two layers of different conductivity types (in this example, a first conductivity type impurity doped layer 64 in the deep part and a second conductivity type impurity doped layer 51 on the surface side) are formed in the single crystal 5iBf481. ) was formed (b).

Next, by carrying out the steps of Example 7, a two-layer wiring structure was obtained (c). As in Example 8, it is possible to obtain even more layers by repeating this example, and as in Example 5, metal may be used for the shielding material.

Furthermore, in this embodiment, although the impurity doped layers 62 and 64J of the first conductivity type remain on the entire surface of the insulating film,
Areas other than necessary areas such as the vicinity of the area may be selectively removed.

[Example 10] The process flow described so far can be simplified by directly oxidizing or nitriding the surface of the conductor that forms signal lines and other wiring. .

As shown in FIG. 11, an oxide film (0,4
pm thickness) 83, conductive layer (0.1 μm thickness) 85. Oxide film(
0.4 μm thick) 84 and a conductive layer (0.4 μm thick) 86 are formed (a) The conductive layer can be made of any material such as metal, silicide, polycrystalline semiconductor, single crystal semiconductor, etc. good.

Next, an ordinary photoresist pattern was formed on the portion that would become the wiring, and using this as a mask, the conductive layer 86 was dry etched. Further, oxidation was then performed to form an oxide film 87 on the surface and side surfaces of the conductive layer (b).

Thereafter, a photoresist pattern 88 was formed to cover the surface and side surfaces of the oxide film 87, and (C) the oxide film 84 was etched. Thereafter, a conductive layer 89 was formed (d) using the same method as explained in FIG. 3(a).

Through the above steps, the wiring made of conductive M86 is formed into an oxide film 84.
A structure was obtained in which the conductive layers 89 and 85 were insulated and the outer periphery was surrounded and shielded by conductive layers 89 and 85.

In the above figure (d), the conductive layer 85, 89 is the oxide film 8.
Although it remains on the entire surface of 3, it may be selectively removed in areas other than necessary areas such as the vicinity of the wiring area. The conductive layer 85 is etched in areas other than the desired areas using a normal photoresist process and etching process.
．． The result of removing 89 is shown in the same figure (e).

By repeating the method described in Example 10 several times using the same method as described in Examples 1 to 10, that is, using polyimide resin or the like as an interlayer insulating film, the structure shown in FIG. It is possible to have multiple layers as shown in Figure (d) and Figure 3 (d).

[Embodiment 11] One of the important purposes of the shield is to prevent electromagnetic interaction between conductors. That is, signals running on other conductors may be prevented from acting as a noise source. In this case, interactions can be divided into those that occur via electromagnetic induction and those that occur via electrostatic induction. The noise voltage in the former is proportional to the magnitude of the magnetic flux linkage (for details, rotE =
-aB/at.

E is an induced electric field, and B is an interlinkage magnetic flux.) Therefore, when a plurality of conductive wires of interest are parallel to each other and the distance between them is small, the generation of noise becomes noticeable.

The noise voltage in the latter case is determined by the size of the parasitic capacitance between the noise source and the conducting wire of interest. That is, when the dielectric constant between the lines is large or the distance between the lines is small, noise becomes noticeable. In this case, taking actual wiring as an example to show where these noises are likely to occur, regardless of whether the conductors are parallel or orthogonal to each other,
This is the location indicated by reference numeral 95 in the figure.

Conversely, there is no particular need for shielding in areas other than these, so we created a multilayer wiring in which shielding was applied only to the necessary areas. Example 9 was used for the process, and the selective formation of the shield film was achieved by etching using a mask after the low resistance semiconductor was deposited on the entire surface.

The number of wiring layers is six including the substrate. In Figure 12,
A top view of the third layer 17 and fourth layer 18 of the produced multilayer wiring is shown. Shields (19, 96) are provided only near the location 95 where noise is likely to occur.

Although only the third layer 17 and fourth layer 18 are shown in FIG. 12, the shielding method described in this embodiment can generally be applied to the shield between the n-th layer and the m-th layer. (m and n are integers).

Further, for example, if noise between two lines is a problem, it is effective to shield only one of them.

Figure 2 is a schematic diagram showing the concept of wiring shield, Figure 12 is a schematic diagram showing the concept of wiring shield.
The figure is a plan view showing an embodiment of the present invention.

DESCRIPTION OF SYMBOLS 1...Si substrate, 2,4,6.8...Insulating film, 7°10...Resist film, 11...Insulating film, 12,13
゜14... Metal film, 17... Third layer signal line, 1
8... Fourth layer signal line, 19... Third layer shield, 2o... Signal line, 21.23... Polycrystalline 5O
122...Metal, 30...Insulating film, 31, 32, 3
3.42... Polycrystalline Si, 40... Shield film, 4
1.43... Metal, 50... Noise, 51... Impurity doped layer, 52... Polycrystalline Si, 61... Ion implantation, 62.64... Impurity doped layer, 81...
・SOI layer, 82...Low resistance Si, 83, 84.87
... Insulating film, 85, 86° 89 ... Conductive layer, 88.
...Resist film, 95... Wiring part where cross talk is likely to occur, 96... 4th layer 20... Signal line 30... Group "Damn 40... Shield ° Moon" Hi 50...Noise" Early 3rd part 4th figure 5th part 6th figure 6+... 7th concave (α small 11111hi 61 62゛-° 9% tvQf['n 64,,,; F blunt doped layer 9th mouth δ2・-i C(a ) 12th mouth

Claims (1)

[Claims] 1. A semiconductor device characterized in that a part or the entire area of a thin wire made of a conductor is surrounded by an insulating film, the periphery of the insulating film is wrapped with a conductor, and the thin wire located inside these is used as a wiring.