JP2677387B2 - Data conversion system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A data conversion system for performing a DMA transfer between a main body and a line adapter, in which data is mutually DMAed even when the CPUs between the main body and the line adapter are of different systems. In a data conversion system that converts the data format communicated between the CPU on the main unit side and the CPU on the adapter side for the purpose of enabling transfer, at the time of system startup, the main unit CPU and the adapter side If it is determined that the CPU types are different, the determining means for determining the CPU type and the converting means for converting the data format of the data transmitted to the main body side or the data received from the main body side, and the conversion means It is configured by including transmission means for transmitting data to the main body side CPU or the adapter side CPU, respectively.

[Field of Industrial Application] The present invention relates to a data conversion system for performing a DMA transfer between a main body and a line adapter.

[Prior Art] When constructing one line system, if one CPU has a task of controlling a line processing system and a task of controlling hardware such as a file, a printer, and a display,
The overhead of the OS (Operating System) increases, which affects the amount of data sent and received by the line hardware and the processing speed, and reduces line performance. FIG. 6 is a diagram showing a basic OS structure. Monitor 2 under CPU1
Disk drive 4 through interface (INT) 3, floppy disk 6 through interface 5, printer 8 through interface 7,
The displays 10 are connected to each other via the interface 9.

APL is an application program, PCP is a presentation control program, SCP is a session control program, TCP is a transport control program, NCP is a network control program, LCP is a logical link control program, MAiF is a media access interface program, and TRC-LAN is a token ring. The controller is a local area network. 11 is a disk control unit, 12 is a floppy disk control unit, 13 is a printer control unit, 14 is a display / keyboard control unit, and these control units are respectively connected to the corresponding interfaces 3, 5, 7, 9 respectively. . Reference numeral 15 is a timer control task, and 16 is a service task. The CPU 1 manages all the constituent elements shown in the figure, and the burden on the CPU 1 becomes extremely large.

Therefore, in order to reduce the load on the main CPU (OS) and suppress the pressure on the main resources, line processing tasks are moved to the line adapter side with independent resources (CPU, memory, I / O) to improve line performance. Is done. In this case, data is generally exchanged between the main body and the line adapter by DMA. FIG. 7 is a diagram showing a case where the OS processing is divided.
The OS on the main body side and the OS on the line adapter side are connected by DMA circuits 17 and 23, respectively. Of each program, APL, PCP,
SCP is included in the OS on the main unit side, and TCP, NCP, LCP are on the line adapter side
Included in OS. In addition, the main body side is connected to a printer or the like via each input / output handling task 18 and various interface circuits 19.

CiF is a channel interface connected to the DMA circuit 17, and MiF is a main interface connected to the DMA circuit 23. CiF includes the main body side DMA control program, and MiF includes the line adapter side DMA control program. 21 is a CPU on the side of the line adapter, and 22 is a monitor.
In this way, by having the CPU independently on the main body side and the line adapter side, the adapter side can concentrate on the line processing, and the main body side also processes other business tasks faster. Here, the line control function should be incorporated in the line adapter side as much as possible, but it is divided at a certain layer depending on how much memory resources such as the line adapter can be used as a common area. In the figure, it is divided into an S layer and a T layer.

[Problems to be Solved by the Invention] In the case of the line system shown in FIG. 7, as a result of the load on the main body side being distributed to the line adapter side, the load on the main body CPU1 is lightened and the processing speed can be increased. However, the system shown in FIG. 7 operates only when the main body side CPU 1 and the line adapter side CPU 21 are CPUs of the same system. For example, the main body CPU1 is Intel's i80286, line adapter side CPU2
If 1 is i80186, there is no problem because the data representation and handling on the memory are the same, although there are some differences in the functions. However, when the main body (or line adapter) side is, for example, the MC68000 manufactured by Motorola, the data representation and handling in the memory are different, so they cannot be connected to each other and communication is impossible.

FIG. 8 is a diagram showing a difference in data representation between both CPUs. Byte data 01H shown in (1) (H indicates hexadecimal)
In the case of, both CPUs have the same expression, but in the case of the word data 0123H shown in (2) and the double word data 01234567H shown in (3), the high (H) and low (L) data You can see that is replaced. In this way, if the CPU of the main unit and the CPU of the line adapter are different, there is no problem if all the DMA data is handled as 1-byte data, but the data handled by each task as control information is actually a word or double word. Since there are many cases, in order to perform processing with a valid value, it will be impossible to communicate unless the data representation that matches the own CPU is used.

The present invention has been made in view of such a problem, and it is possible to perform mutual DMA transfer of data even when the CPUs between the main body and the line adapter are of different systems. The purpose is to provide a data conversion system capable of

[Means for Solving the Problems] FIG. 1 is a principle block diagram of the present invention. In the figure, 30 is a main body, 40 is a line adapter, and 50 is a bus connecting the main body 30 and the line adapter 40. Reference numeral 31 is a CPU for controlling the main body 30, 32 is a buffer for storing data, and 33 is a DMA circuit for performing DMA transfer of data with the line adapter 40 side via the bus 50. 41 is a CPU that controls the line adapter 40,
42 is a buffer for storing data, 43 is a DMA circuit for performing DMA transfer of data with the main body 30 side via the bus 50, 44 is a CP
This is an H / L conversion unit for exchanging H and L of data when U31 and CPU 41 are separate systems. Although the H / L converter 44 is provided on the line adapter 40 side in the figure, it may be provided on the main body 30 side.

[Operation] When the CPU 31 on the main body 30 side and the CPU 41 on the line adapter 40 side are separate systems, after the data sent from the main body side via the DMA circuit 33 is received by the DMA circuit 43, H / H The L conversion unit 44 exchanges H and L data. The replaced data is stored in the buffer 42. If you want to transfer DMA data from the line adapter 40 side to the main unit 30,
After performing H / L conversion on the side, DMA transfer is performed to the main body 30. As a result, when the CPU 31 and the CPU 41 are separate systems, data transfer can be performed mutually.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In order to absorb the difference in data representation, it is necessary to replace the data at some timing, which can be done as follows.

(1) In the initial processing of iPL (initial program loading) of the line adapter system 51a stored in the external storage device 51 into the buffer memory 42 of the line adapter 40 via the main body 30 as shown in FIG. , CPU3
The identification of 1 is judged by any of system information, iPLROM45, and a setting pin by a hardware circuit.

FIG. 3 is a flowchart showing the process up to the identification of the main body CPU. First, the main body 30 loads the system (step 1), and then the main body 30 receives a start command (step 2). In this state, the CPU 31 of the main body is discriminated and its information is stored in the memory (step 3). Then, it has data from the main body 30 or the partner station (step 4).

(2) For the data to be (or will be) DMAd, the data conversion logic is incorporated into the task of handling the DMA only for the byte arrangement that differs, and H / L conversion is performed. D
The task of handling the MA is the H / L conversion unit 44 in FIG.
Is in. And H / L data conversion (replacement)
The data for which is completed is stored in the buffer 42. The conversion is performed after the DMA transfer to the line adapter 40 or before the DMA transfer from the line adapter 40 to the main body 30 as described above. As a result, the load on the main body CPU 31 can be reduced.
Needless to say, if the CPUs on the main unit side and the line adapter side are of the same system, no data conversion is necessary and DMA transfer can be performed as is.

FIG. 4 is a system configuration diagram showing an embodiment of the present invention. 1 are denoted by the same reference numerals.
In the figure, 34 is a channel interface (CiF) which is a DMA control program on the main body 30 side, and 45 is a line adapter 4
It is the main interface (MiF) that is the DMA control program on the 0 side. The H / L converter 44 shown in FIG. 1 is contained in the main interface 45. In such a system, H / L conversion is performed by DMA from the main unit 30 to the line adapter 40.
It is performed after the transfer or before the DMA transfer from the line adapter 40 to the main body 40. Therefore, in either case, H / L conversion of data is performed by the H / L conversion unit 44 in the main interface 45.

FIG. 5 is a diagram showing the timing of data conversion.
Shows the case of DMA from the main body, and (B) shows the case of DMA to the main body. In the case of (a), first, the main body side issues an interrupt request iRQ to the adapter side, and then when the adapter side is ready, DMA transfer is performed to the buffer on the adapter side. On the adapter side,
The received data is converted into data that matches the data format of the CPU on the adapter side, and the data that has been converted is stored in the buffer in sequence. When it finishes receiving the data, it sends a completion notification to the main unit. In the case of (b), the data is converted to the data format of the main unit CPU on the adapter side before DMA transfer, then DMA transfer is performed, and a completion notification is issued when the transfer is completed.

In the above description, the case where the line adapter side identifies the main body CPU is taken as an example. However, the present invention is not limited to this, and the main body side may identify the CPU on the line adapter side. The data conversion in this case is performed before the DMA transfer from the main body to the line adapter, or after the DMA transfer from the line adapter to the main body. Therefore, in this case, the above-mentioned H / L converter is provided on the main body side. Further, although the present invention has been described by taking the case of DMA transfer between the main unit and the line adapter as an example, the present invention can be similarly applied to the case of mounting various option boards on the terminal side and performing DMA transfer.

[Effects of the Invention] As described above in detail, according to the present invention, when the system of the CPU of the main body side and the CPU of the line adapter side are different, data conversion is performed and the data format is adjusted to the CPU on one side. It is possible to provide a data conversion system in which by performing processing, it is possible to mutually perform DMA transfer of data even when the CPUs between the main body and the line adapter are of different systems.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing iPL processing of a line adapter system, FIG. 3 is a flow chart showing processing up to CPU identification of the main body, and FIG. 4 is an embodiment of the present invention. Fig. 5 is a system configuration diagram showing Fig. 5, Fig. 5 is a diagram showing timing of data conversion, Fig. 6 is a diagram showing a basic OS structure, Fig. 7 is a diagram showing a case where the OS processing is divided, and Fig. 8 is both It is a figure which shows the difference of the data representation of CPU. In FIG. 1, 30 is a main body, 31 is a CPU, 32 is a buffer, 33 is a DMA circuit, 40 is a line adapter, 41 is a CPU, 42 is a buffer, 43 is a DMA circuit,
44 is an H / L converter.

Claims (1)

(57) [Claims] 1. A data conversion system for converting a data format to be communicated between a CPU on the main body side and a CPU on the adapter side, and a judging means for judging the types of the main body CPU and the adapter CPU at system startup. If it is determined that the types of these CPUs are different, conversion means for converting the data format of the data sent to the main body side or the data received from the main body side, and these converted data, respectively, main body side CPU or adapter A data conversion system comprising: a transmission means for transmitting to the side CPU.